CVAX CPU CHIP DESIGN SPECIFICATION DC 341 21-24674-01 Rev. 3.00 Contact: Andy Olesin (RICKS::OLESIN) C O M P A N Y C O N F I D E N T I A L Copyright (C) 1985, 1986, 1987 by Digital Equipment Corporation The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may occur in this document. This specification does not describe any program or product which is currently available from Digital Equipment Corporation. Nor does Digital Equipment Corporation commit to implement this specification in any product or program. Digital Equipment Corporation makes no commitment that this document accurately describes any product it might ever make. CVAX CPU CHIP DESIGN SPECIFICATION Page 2 TABLE OF CONTENTS CONTENTS 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . 3 1.1 Scope . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Applicable Documents . . . . . . . . . . . . . . . 3 1.3 CVAX CPU Chip Organization . . . . . . . . . . . . 3 1.3.1 Instruction Unit (I Box) . . . . . . . . . . . . 3 1.3.2 Execution Unit (E Box) . . . . . . . . . . . . . 3 1.3.3 Memory Translation Unit (M Box) . . . . . . . . 3 1.3.4 Bus Interface Unit (BIU) . . . . . . . . . . . . 4 1.3.5 Microsequencer . . . . . . . . . . . . . . . . . 4 1.3.6 Interrupt Logic . . . . . . . . . . . . . . . . 4 1.3.7 Control Store . . . . . . . . . . . . . . . . . 4 1.3.8 Cache . . . . . . . . . . . . . . . . . . . . . 4 1.3.9 Clock Logic . . . . . . . . . . . . . . . . . . 4 1.4 Block Diagram . . . . . . . . . . . . . . . . . . 4 2 INSTRUCTION (I) BOX . . . . . . . . . . . . . . . . 5 2.1 Prefetcher . . . . . . . . . . . . . . . . . . . . 5 2.1.1 Prefetcher Data Path . . . . . . . . . . . . . . 5 2.1.1.1 Instruction Prefetch Queue . . . . . . . . . . 6 2.1.1.2 Instruction Byte Rotator . . . . . . . . . . . 6 2.1.1.3 Instruction Data (ID) Register . . . . . . . . 6 2.1.2 Prefetch Controller . . . . . . . . . . . . . . 7 2.2 The Instruction PLA (IPLA) . . . . . . . . . . . . 7 2.3 Microaddress Generator . . . . . . . . . . . . . . 9 2.3.1 IID Dispatch (used When SPEC.CTR = 0) . . . . . 9 2.3.1.1 IID Exception Dispatch . . . . . . . . . . . . 9 2.3.1.2 IID Execution Dispatch . . . . . . . . . . . 10 2.3.1.3 Specifier Dispatch . . . . . . . . . . . . . 10 2.3.2 Second IID Dispatch ( Spec Counter = 0) . . . 11 2.3.3 Specifier Decode Dispatches . . . . . . . . . 12 2.3.4 MicroAddress Format . . . . . . . . . . . . . 13 2.3.5 Delta PC Logic . . . . . . . . . . . . . . . . 14 2.4 Miscellaneous Register Descriptions . . . . . . 15 2.4.1 Current Specifier / Register Number Latch (SPEC.RN) . . . . . . . . . . . . . . . . . . 16 2.4.2 FPU Present . . . . . . . . . . . . . . . . . 16 2.4.3 VAX Trap Request . . . . . . . . . . . . . . . 16 2.4.4 Specifier Counter . . . . . . . . . . . . . . 16 2.4.5 Data Length And Access Type . . . . . . . . . 17 2.4.6 PSL Bits . . . . . . . . . . . . . . . . . . . 17 2.4.7 Second IID Flag . . . . . . . . . . . . . . . 18 2.4.8 Index Expected Flag . . . . . . . . . . . . . 18 2.5 I Box Initialization At RESET Signal . . . . . . 18 2.6 I Box Related Microinstructions . . . . . . . . 18 2.7 Microcode Restriction Summary . . . . . . . . . 20 2.8 SN Output . . . . . . . . . . . . . . . . . . . 21 2.9 I Box Testability Hardware . . . . . . . . . . . 21 2.10 I Box Schematics And Their Functions . . . . . . 23 2.10.1 I_ADDRESS_GENERATOR (IAG) . . . . . . . . . . 23 2.10.2 I_AT_DL_REG (IAD) . . . . . . . . . . . . . . 23 2.10.3 I_DATAPATH (IDP) . . . . . . . . . . . . . . . 23 2.10.4 I_DP_DRIVERS (IDD) . . . . . . . . . . . . . . 23 2.10.5 I_DISPATCH_PLA (IP1) . . . . . . . . . . . . . 23 CVAX CPU CHIP DESIGN SPECIFICATION Page 3 TABLE OF CONTENTS 2.10.5.1 I_DISPATCH_PLA PLAD File . . . . . . . . . . 23 2.10.5.2 I_DISPATCH_PLA Binary File... . . . . . . . 27 2.10.6 I_FPA_BUFFERS (IFB) . . . . . . . . . . . . . 28 2.10.7 I_IID_LOGIC (IIL) . . . . . . . . . . . . . . 28 2.10.8 I_IPLA (IPL) . . . . . . . . . . . . . . . . . 28 2.10.9 I_MIB_DECODE (IMD) . . . . . . . . . . . . . . 29 2.10.10 I_MISC_STATE (IMS) . . . . . . . . . . . . . . 29 2.10.11 I_OP_MUX (IOM) . . . . . . . . . . . . . . . . 29 2.10.12 I_OTHER_MIB_DECODER (IM2) . . . . . . . . . . 29 2.10.13 I_PFQ_CONTROL (IQC) . . . . . . . . . . . . . 29 2.10.14 I_SECOND_IPLA (I2P) . . . . . . . . . . . . . 30 2.10.15 I_SPEC_COUNTER (ISC) . . . . . . . . . . . . . 30 2.10.16 I_SPEC_RN_REG (ISR) . . . . . . . . . . . . . 30 2.10.17 I_SPUR_UTEST_DRIVE (ISU) . . . . . . . . . . . 30 2.11 Tables . . . . . . . . . . . . . . . . . . . . . 31 2.11.1 Dispatch Types, STALL And UTrap Behavior . . 31 2.11.2 NOTE ON UPDATING I BOX STATE . . . . . . . . . 31 2.11.3 CVAX IPLA Assignments . . . . . . . . . . . . 33 2.11.4 Other Opcodes . . . . . . . . . . . . . . . . 42 2.11.5 Internal/External Signal Timing . . . . . . . 43 2.12 Glossary Of Mnemonics . . . . . . . . . . . . . 87 2.13 CHANGE REQUESTS THAT HAVE BEEN INCLUDED HERE . . 88 2.14 ISSUES . . . . . . . . . . . . . . . . . . . . . 88 3 EXECUTION (E) BOX . . . . . . . . . . . . . . . . 91 3.1 Register File . . . . . . . . . . . . . . . . . 93 3.1.1 Triple Ported Registers (W Registers) . . . . 93 3.1.2 Dual Ported Registers (GP Registers) . . . . . 93 3.1.2.1 Data-Length Dependent Writes . . . . . . . . 93 3.1.3 Dual Ported Registers (T Registers) . . . . . 94 3.1.4 Functional Summary . . . . . . . . . . . . . . 94 3.1.4.1 Register File Addressing . . . . . . . . . . 94 3.1.4.2 Source Control . . . . . . . . . . . . . . . 96 3.1.4.3 Implementation Notes . . . . . . . . . . . . 96 3.1.4.4 Destination Control . . . . . . . . . . . . 97 3.1.4.5 Timing Of Writes And Control Signals From The M BOX . . . . . . . . . . . . . . . . . . . 97 3.1.5 W_Bus . . . . . . . . . . . . . . . . . . . . 97 3.1.6 Zero Extension . . . . . . . . . . . . . . . . 97 3.1.7 W_SPUR . . . . . . . . . . . . . . . . . . . . 98 3.1.8 Microcode Restrictions . . . . . . . . . . . . 99 3.2 Program Counter (PC Register) . . . . . . . . . 100 3.2.1 PC Register . . . . . . . . . . . . . . . . . 100 3.2.2 PC Adder . . . . . . . . . . . . . . . . . . . 101 3.2.3 BPC Register . . . . . . . . . . . . . . . . . 101 3.2.4 Microcode Restrictions . . . . . . . . . . . . 101 3.3 Constant Generator . . . . . . . . . . . . . . . 102 3.3.1 Constants . . . . . . . . . . . . . . . . . . 102 3.3.1.1 KDL Constants . . . . . . . . . . . . . . . 102 3.3.1.2 SHIFT Microinstruction Constants . . . . . . 102 3.3.1.3 CONSTANT Microinstruction Constants . . . . 102 3.3.1.4 A_Bus Constants . . . . . . . . . . . . . . 103 3.3.2 Microcode Restrictions . . . . . . . . . . . . 103 3.4 Shift Counter (SC) . . . . . . . . . . . . . . . 104 3.4.1 Functional Summary . . . . . . . . . . . . . . 104 CVAX CPU CHIP DESIGN SPECIFICATION Page 4 TABLE OF CONTENTS 3.4.2 UTest And The SC . . . . . . . . . . . . . . . 104 3.4.3 Microcode Restrictions . . . . . . . . . . . . 105 3.5 Shifter . . . . . . . . . . . . . . . . . . . . 106 3.5.1 Functional Summary . . . . . . . . . . . . . . 106 3.5.1.1 Implementation Note . . . . . . . . . . . . 107 3.5.2 Raw SHFT Condition Codes . . . . . . . . . . . 107 3.5.3 Microcode Restrictions . . . . . . . . . . . . 107 3.6 Arithmetic Logic Unit (ALU) . . . . . . . . . . 108 3.6.1 Functional Summary . . . . . . . . . . . . . . 108 3.6.1.1 ALU Implementation Notes . . . . . . . . . . 109 3.6.1.2 SMUL Step Definition . . . . . . . . . . . . 110 3.6.1.3 UDIV Step Definition . . . . . . . . . . . . 111 3.6.1.4 Raw ALU Condition Codes . . . . . . . . . . 112 3.6.2 Microcode Restrictions . . . . . . . . . . . . 113 3.7 Multiplier Quotient Register . . . . . . . . . . 114 3.7.1 Functional Summary . . . . . . . . . . . . . . 114 3.7.2 Microcode Restrictions . . . . . . . . . . . . 114 3.8 PSL Logic . . . . . . . . . . . . . . . . . . . 115 3.8.1 I BOX Usage Of The PSL And Trace Logic . . . . 115 3.8.2 M BOX, INT_CTRL And BIU Usage Of PSL . . . . . 115 3.8.3 PSL Distribution . . . . . . . . . . . . . . . 115 3.8.4 PSL<3:0> - Condition Code Bits . . . . . . . . 116 3.8.5 Microcode Restrictions . . . . . . . . . . . . 116 3.9 Condition Code Logic . . . . . . . . . . . . . . 117 3.9.1 PSL CC Register, PSL<3:0> . . . . . . . . . . 118 3.9.1.1 Loading Of The PSL CC Register . . . . . . . 118 3.9.1.2 PSL Condition Code Map . . . . . . . . . . . 119 3.9.2 ALU CC Register . . . . . . . . . . . . . . . 119 3.9.3 VAX Restart Flag . . . . . . . . . . . . . . . 120 3.9.4 Integer Overflow Logic . . . . . . . . . . . . 121 3.9.5 Branch Test Logic . . . . . . . . . . . . . . 121 3.9.6 Microcode Restrictions . . . . . . . . . . . . 122 3.10 RLOG . . . . . . . . . . . . . . . . . . . . . . 123 3.10.1 Implementation Notes . . . . . . . . . . . . . 123 3.10.2 Microcode Restrictions . . . . . . . . . . . . 123 3.11 State Logic . . . . . . . . . . . . . . . . . . 124 3.11.1 Microcode Restrictions . . . . . . . . . . . . 125 3.12 Opcode Register . . . . . . . . . . . . . . . . 126 3.12.1 Microcode Restrictions . . . . . . . . . . . . 126 3.13 Summary Of E BOX Microcode Restrictions . . . . 127 3.13.1 Register File . . . . . . . . . . . . . . . . 127 3.13.2 Program Counter (PC Register) . . . . . . . . 127 3.13.3 Constant Generator . . . . . . . . . . . . . . 127 3.13.4 SC Logic . . . . . . . . . . . . . . . . . . . 127 3.13.5 Shifter . . . . . . . . . . . . . . . . . . . 127 3.13.6 ALU . . . . . . . . . . . . . . . . . . . . . 128 3.13.7 Q Register . . . . . . . . . . . . . . . . . . 128 3.13.8 PSL Logic . . . . . . . . . . . . . . . . . . 128 3.13.9 CC Logic . . . . . . . . . . . . . . . . . . . 128 3.13.10 RLOG . . . . . . . . . . . . . . . . . . . . . 128 3.13.11 STATE . . . . . . . . . . . . . . . . . . . . 129 3.13.12 OPCODE REGISTER . . . . . . . . . . . . . . . 129 3.14 E BOX Microcode Visible State . . . . . . . . . 130 3.15 E BOX Schematic Inventory . . . . . . . . . . . 131 CVAX CPU CHIP DESIGN SPECIFICATION Page 5 TABLE OF CONTENTS 3.16 E BOX Global Signal Timing . . . . . . . . . . . 133 3.17 E BOX Internal Signal Timing . . . . . . . . . . 140 3.18 Change Requests (ECO) . . . . . . . . . . . . . 171 3.19 ISSUES . . . . . . . . . . . . . . . . . . . . . 172 4 MEMORY (M) BOX . . . . . . . . . . . . . . . . . . 173 4.1 M Box Overview . . . . . . . . . . . . . . . . . 173 4.1.1 Introduction . . . . . . . . . . . . . . . . . 173 4.1.2 Microinstruction Control Of The M Box . . . . 173 4.1.2.1 Memory Requests . . . . . . . . . . . . . . 174 4.1.2.2 Non Memory Request Microinstructions . . . . 178 4.1.3 Translation Buffer Description . . . . . . . . 178 4.1.4 Microcode Flows . . . . . . . . . . . . . . . 179 4.1.4.1 Longword References . . . . . . . . . . . . 180 4.1.4.2 Memory References That Use DL . . . . . . . 181 4.1.5 Registers . . . . . . . . . . . . . . . . . . 182 4.2 Function Descriptions . . . . . . . . . . . . . 183 4.2.1 Memory Address Logic . . . . . . . . . . . . 184 4.2.1.1 VA (Virtual Address) Register . . . . . . . 184 4.2.1.2 VAP (VA Prime) Register . . . . . . . . . . 184 4.2.1.3 VIBA (Virtual Instruction Buffer Address) Register . . . . . . . . . . . . . . . . . . 185 4.2.1.4 + 4 Adder . . . . . . . . . . . . . . . . . 185 4.2.2 TB . . . . . . . . . . . . . . . . . . . . . . 185 4.2.2.1 PTEs . . . . . . . . . . . . . . . . . . . . 186 4.2.2.2 NLU . . . . . . . . . . . . . . . . . . . . 188 4.2.2.3 TB Data Path . . . . . . . . . . . . . . . . 188 4.2.2.4 TB Fills From Memory . . . . . . . . . . . . 190 4.2.2.5 TB Invalidate Logic . . . . . . . . . . . . 191 4.2.2.6 TB Miss Logic . . . . . . . . . . . . . . . 191 4.2.2.7 TB Summary . . . . . . . . . . . . . . . . . 191 4.2.3 Access Logic . . . . . . . . . . . . . . . . . 193 4.2.3.1 Privilege Check Logic . . . . . . . . . . . 193 4.2.3.2 Length Check Logic . . . . . . . . . . . . . 193 4.2.3.3 Inhibit IB Fill Logic . . . . . . . . . . . 194 4.2.3.4 MMGT.STATUS . . . . . . . . . . . . . . . . 194 4.2.3.5 MBOX.STATUS . . . . . . . . . . . . . . . . 195 4.2.3.6 MREF.STATUS . . . . . . . . . . . . . . . . 196 4.2.4 Memory Management Microtrap Logic . . . . . . 196 4.2.4.1 Partial PSL Logic . . . . . . . . . . . . . 196 4.2.4.2 Cross Page Detection Logic . . . . . . . . . 197 4.2.4.3 Microtrap And Abort Determination Logic . . 197 4.2.5 Memory Management Controller . . . . . . . . . 199 4.2.5.1 Trap Disable Logic . . . . . . . . . . . . . 199 4.2.5.2 Reexecute Reference Logic . . . . . . . . . 199 4.2.5.3 REPROBE Flag - . . . . . . . . . . . . . . . 200 4.2.5.4 Memory Management Enable Logic . . . . . . . 200 4.2.6 Second IDAL Cycle Detection Logic . . . . . . 200 4.2.6.1 REQ_2ND_REF Logic . . . . . . . . . . . . . 201 4.2.7 M Box Data Latches And Positioners . . . . . . 201 4.2.7.1 M Box Data Latch And Byte Rotator . . . . . 201 4.2.7.2 Internal Byte Mask . . . . . . . . . . . . . 202 4.2.8 Control Signals Sent To BIU . . . . . . . . . 203 4.2.8.1 BIU_NOP . . . . . . . . . . . . . . . . . . 203 4.2.9 IB_FILL_VALID . . . . . . . . . . . . . . . . 203 CVAX CPU CHIP DESIGN SPECIFICATION Page 6 TABLE OF CONTENTS 4.2.10 MBOXBM . . . . . . . . . . . . . . . . . . . . 204 4.2.11 Control Signals Sent To E Box . . . . . . . . 204 4.2.11.1 WSEL_UPDATE_H . . . . . . . . . . . . . . . 204 4.2.11.2 REG_WRITE_H . . . . . . . . . . . . . . . . 204 4.2.11.3 SET_RESTART . . . . . . . . . . . . . . . . 204 4.2.11.4 NOT_MEM_REQ_R_H . . . . . . . . . . . . . . 204 4.2.11.5 MW_TO_W_H . . . . . . . . . . . . . . . . . 205 4.3 M Box Intersection And Intrasection Signals . . 205 4.3.1 M BOX Global Signal Timing . . . . . . . . . . 205 4.3.2 M BOX Internal Signal Timing . . . . . . . . . 214 4.4 ISSUES . . . . . . . . . . . . . . . . . . . . . 251 5 CACHE . . . . . . . . . . . . . . . . . . . . . . 253 5.1 Ram Array And Sense Amps . . . . . . . . . . . . 254 5.2 Address Selection And Decode . . . . . . . . . . 255 5.3 Tag Data Path . . . . . . . . . . . . . . . . . 256 5.3.1 M Box Address Latch . . . . . . . . . . . . . 258 5.3.2 Parity Generator/Checker . . . . . . . . . . . 258 5.3.3 Match Address Latch . . . . . . . . . . . . . 258 5.3.4 Address Match Detection . . . . . . . . . . . 258 5.3.5 Tag Write Mux . . . . . . . . . . . . . . . . 258 5.4 Data Array Drivers . . . . . . . . . . . . . . . 259 5.4.1 IDAL Input Buffer . . . . . . . . . . . . . . 260 5.4.2 Data Multiplexer . . . . . . . . . . . . . . . 261 5.4.3 IDAL Output Buffer . . . . . . . . . . . . . . 261 5.5 Cache Control . . . . . . . . . . . . . . . . . 261 5.5.1 Operation Decode . . . . . . . . . . . . . . . 262 5.5.2 Set Selection . . . . . . . . . . . . . . . . 263 5.5.3 Multiple Write Control . . . . . . . . . . . . 264 5.5.4 Refresh Counter . . . . . . . . . . . . . . . 264 5.6 Cache Timing . . . . . . . . . . . . . . . . . . 264 6 BUS INTERFACE UNIT (BIU)- . . . . . . . . . . . . 266 6.1 BIU Controlled Pins . . . . . . . . . . . . . . 266 6.1.1 Internal Pin Names . . . . . . . . . . . . . . 267 6.2 BIU Controlled Internal Bus - IDAL BUS (G_S%IDAL_H<31:0>) . . . . . . . . . . . . . . . 267 6.3 BIU Logic Blocks . . . . . . . . . . . . . . . . 267 6.3.1 IDAL Control Machine . . . . . . . . . . . . . 267 6.3.2 DAL Control Machine . . . . . . . . . . . . . 268 6.3.3 Cache Disable Register (CADR) . . . . . . . . 268 6.3.4 Low Memory System Error Register (MSER) . . . 269 6.3.4.1 DAL H Parity . . . . . . . . . . . . . . . 270 6.3.5 MIB Decoder . . . . . . . . . . . . . . . . . 271 6.3.6 CFPA Machine . . . . . . . . . . . . . . . . . 272 6.4 Descriptions Of BIU Cycles . . . . . . . . . . . 272 6.4.1 DMA Cycle - . . . . . . . . . . . . . . . . . 273 6.4.2 Data Read Cycle - . . . . . . . . . . . . . . 273 6.4.3 Data Write Cycle - . . . . . . . . . . . . . . 274 6.4.4 CFPA Cycles - . . . . . . . . . . . . . . . . 274 6.4.4.1 Passing Opcode Information To The CFPA . . . 274 6.4.4.2 Passing Operands To The CFPA . . . . . . . . 276 6.4.4.3 Passing Results Back From The CFPA . . . . . 277 6.4.4.4 POLY Protocol . . . . . . . . . . . . . . . 278 6.4.4.5 CFPA Present Indication . . . . . . . . . . 279 6.4.4.6 CFPA Forced Termination . . . . . . . . . . 279 CVAX CPU CHIP DESIGN SPECIFICATION Page 7 TABLE OF CONTENTS 6.4.4.7 Sample CFPA Timing . . . . . . . . . . . . . 279 6.4.4.8 CFPA Interface Overhead . . . . . . . . . . 285 6.4.5 Instruction Stream Read Cycle . . . . . . . . 287 6.4.6 IDLE Cycle - . . . . . . . . . . . . . . . . . 288 6.4.7 Output Pin Status On RESET L . . . . . . . . . 288 6.4.8 Table Of Interesting Pad Values And Chip Functions During Memory Cycles . . . . . . . . 288 6.5 IDAL State Machine Definition . . . . . . . . . 289 6.6 DAL State Machine Definition . . . . . . . . . . 291 6.7 Stall And Trap Behavior Of The BIU - A Summary . 292 6.7.1 Mbox_stall - What It Means And When It's Used 292 6.7.2 Stall . . . . . . . . . . . . . . . . . . . . 293 6.7.3 BIU Trap Request . . . . . . . . . . . . . . . 293 6.7.4 BIU Trap Vectors . . . . . . . . . . . . . . . 293 6.7.5 CFPA Trap Request . . . . . . . . . . . . . . 293 6.7.6 CFPA Exception Trap Vectors . . . . . . . . . 294 6.8 BIU Internal Signal Timing . . . . . . . . . . . 295 6.9 BIU Internal Signal Timing . . . . . . . . . . . 296 7 MICROSEQUENCER . . . . . . . . . . . . . . . . . . 333 7.1 Busses . . . . . . . . . . . . . . . . . . . . . 333 7.1.1 Microaddress Bus (MAB) <10:0> . . . . . . . . 333 7.1.2 I Box Microaddress Bus (IMAB) <10:0> . . . . 333 7.1.3 Microtest Bus (UTEST) <2:0> . . . . . . . . . 334 7.1.4 Microinstruction Bus (MIB) <40:0> . . . . . . 334 7.1.5 Current Microaddress Bus (CMAB) <10:0> . . . . 334 7.1.6 Incremented Current Microaddress Bus (ICMAB) <10:0> . . . . . . . . . . . . . . . . . . . . 334 7.1.7 Microstack Input Bus (USIB) <10:0> . . . . . . 334 7.1.8 Microstack Data Bus (USDB) <10:0> . . . . . . 335 7.1.9 Microstack Output Bus (USOB) <10:0> . . . . . 335 7.1.10 Test_MAB Bus (TEST_MAB) <10:0> . . . . . . . . 335 7.1.11 Microtrap Address Bus (UTRAB) <6:4> . . . . . 335 7.2 Microsequencer Sections . . . . . . . . . . . . 335 7.2.1 Microstack (USTACK) [0:7] . . . . . . . . . . 335 7.2.2 Current Microaddress Latch (CMAL) . . . . . . 336 7.2.3 Current Microaddress Incrementer And Latch (CMAI) . . . . . . . . . . . . . . . . . . . . 336 7.2.3.1 Microcode Notes (MICROCODE ALLOCATION RESTRICTION) . . . . . . . . . . . . . . . . 336 7.2.4 Microstack Input Mux (USIM) . . . . . . . . . 336 7.2.5 Microstack Write Buffer (USWB) . . . . . . . . 337 7.2.6 Microaddress Bus Mux (MAB Mux) . . . . . . . . 337 7.2.7 Microaddress Bus Latch (MAB Latch) . . . . . . 338 7.2.8 Microtrap Address Generator (UTRAG) . . . . . 338 7.2.9 STALL Latch (SL) . . . . . . . . . . . . . . . 338 7.3 Control Logic . . . . . . . . . . . . . . . . . 339 7.3.1 MAB Mux Control Logic . . . . . . . . . . . . 339 7.4 Timing Summary . . . . . . . . . . . . . . . . . 340 7.5 Functional Description . . . . . . . . . . . . . 340 7.5.1 Microsequencer Control Interpretation . . . . 340 7.5.2 Branch Format . . . . . . . . . . . . . . . . 341 7.5.3 Branch Offset (BO) MIB<6:0> . . . . . . . . . 341 7.5.4 Branch Condition Select (BCS) MIB<11:7> . . . 342 7.5.5 Jump Format . . . . . . . . . . . . . . . . . 342 CVAX CPU CHIP DESIGN SPECIFICATION Page 8 TABLE OF CONTENTS 7.5.6 Subroutine Control Bit (SB) MIB<11> . . . . . 343 7.5.7 Jump Address Field MIB<10:0> . . . . . . . . . 343 7.5.8 Microtrap Mechanism . . . . . . . . . . . . . 343 7.5.9 Microsequencer Test Mode . . . . . . . . . . . 344 7.6 Microsequencer Test Hooks . . . . . . . . . . . 344 7.7 Microsequencer Global Signal Dictionary . . . . 345 7.8 Microsequencer Internal Signal Dictionary . . . 348 7.9 Microsequencer Block Diagram . . . . . . . . . . 351 7.10 Change Requests ( ECO ) . . . . . . . . . . . . 352 7.11 ISSUES . . . . . . . . . . . . . . . . . . . . . 352 8 CONTROL STORE . . . . . . . . . . . . . . . . . . 354 8.1 Functional Summary . . . . . . . . . . . . . . . 354 8.2 MIB Latch/MIB Drivers . . . . . . . . . . . . . 355 8.3 Control Store Test Hooks . . . . . . . . . . . . 355 8.4 Control Store Block Diagram . . . . . . . . . . 356 8.5 Control Store Signal Dictionary . . . . . . . . 357 8.6 Change Requests ( ECO ) . . . . . . . . . . . . 359 8.7 Issues . . . . . . . . . . . . . . . . . . . . . 359 9 INTERRUPT LOGIC . . . . . . . . . . . . . . . . . 361 9.1 Interrupt Latches . . . . . . . . . . . . . . . 361 9.2 Highest Software Interrupt Register (HSIR). . . 361 9.3 Interrupt Priority Encoder . . . . . . . . . . 362 9.4 Interrupt IPL And Comparator . . . . . . . . . . 363 9.5 Microcode Notes . . . . . . . . . . . . . . . . 363 9.6 Microcode Restrictions . . . . . . . . . . . . . 364 9.7 Block Diagram . . . . . . . . . . . . . . . . . 365 9.8 OPEN ISSUES . . . . . . . . . . . . . . . . . . 366 10 CLOCK LOGIC . . . . . . . . . . . . . . . . . . . 367 10.1 Clock Input Buffer - Phase Separator . . . . . . 368 10.2 RESET_L Input Buffer . . . . . . . . . . . . . . 368 10.3 Phase Select Logic . . . . . . . . . . . . . . . 368 11 CONTROL FIELDS SUMMARY . . . . . . . . . . . . . . 369 11.1 Data Path Control Formats . . . . . . . . . . . 369 11.2 Microsequencer Control Formats . . . . . . . . . 369 11.3 General Fields . . . . . . . . . . . . . . . . . 371 11.3.1 B_Bus Select (B) Field . . . . . . . . . . . . 371 11.3.2 Destination (DST) Field . . . . . . . . . . . 371 11.3.3 Condition Code (CC) Field . . . . . . . . . . 371 11.3.4 A_Bus Select (A) Field . . . . . . . . . . . . 372 11.3.5 Miscellaneous (MISC) Field . . . . . . . . . 372 11.4 BASIC Microinstruction . . . . . . . . . . . . . 374 11.4.1 BASIC Function (BASIC.FNC) Field . . . . . . . 374 11.4.2 Length (L) Field . . . . . . . . . . . . . . . 375 11.5 CONSTANT Microinstruction . . . . . . . . . . . 376 11.5.1 CONSTANT Position (POS) Field . . . . . . . . 376 11.5.2 CONSTANT Destination (DS) Field . . . . . . . 376 11.5.3 CONSTANT Function (CONST.FNC) Field . . . . . 376 11.6 SHIFT Microinstruction . . . . . . . . . . . . . 378 11.6.1 SHIFT Value (SHIFT.VAL) Field . . . . . . . . 378 11.6.2 SHIFT Function Fields (SHIFT.DIR, DST) . . . . 378 11.7 MEM REQ Microinstruction . . . . . . . . . . . . 379 11.7.1 MEM REQ Function (MEMREQ.FNC) Field . . . . . 379 11.7.2 MEM REQ Length (L) Field . . . . . . . . . . . 380 11.7.3 MEM REQ Read/Write (RW) Field . . . . . . . . 380 CVAX CPU CHIP DESIGN SPECIFICATION Page 9 TABLE OF CONTENTS 11.7.4 MEM REQ Access Control (MEMREQ.ACC) Field . . 380 11.8 SPECIAL Microinstruction . . . . . . . . . . . . 383 11.8.1 SPECIAL Condition Code (MISC1) Field . . . . . 383 11.8.2 SPECIAL Function (MISC2) Field . . . . . . . . 383 11.8.3 SPECIAL Control Flags (MISC3) Field . . . . . 384 11.9 BRANCH Microinstruction . . . . . . . . . . . . 385 11.9.1 Branch Condition Select (BCS) Field . . . . . 385 11.9.2 Branch Offset (BO) Field . . . . . . . . . . . 386 11.10 JUMP Microinstruction . . . . . . . . . . . . . 387 11.10.1 Subroutine (SB) Field . . . . . . . . . . . . 387 11.10.2 Jump Address Field . . . . . . . . . . . . . . 387 12 TEST LOGIC . . . . . . . . . . . . . . . . . . . . 388 12.1 Observability Logic . . . . . . . . . . . . . . 388 12.1.1 CWB Logic . . . . . . . . . . . . . . . . . . 388 12.2 Control Logic . . . . . . . . . . . . . . . . . 388 12.2.1 Normal State . . . . . . . . . . . . . . . . . 389 12.2.2 Test State . . . . . . . . . . . . . . . . . . 389 12.2.2.1 TEST Pin . . . . . . . . . . . . . . . . . . 389 12.2.2.2 Internal MAB . . . . . . . . . . . . . . . . 389 12.2.2.3 External MAB . . . . . . . . . . . . . . . . 389 12.2.2.4 Force Broadcast . . . . . . . . . . . . . . 389 12.2.2.5 Configuration Latch . . . . . . . . . . . . 390 12.2.2.6 Loading Configuration Latch . . . . . . . . 390 12.3 Shift Register Locations . . . . . . . . . . . . 390 12.3.1 MIB (Shift Register #1) . . . . . . . . . . . 390 12.3.2 I Box IPLA (Shift Register #2) . . . . . . . . 391 12.3.3 Cache Refresh Address Generator/Reducer (Shift Register #3) . . . . . . . . . . . . . . . . . 392 12.3.4 Main Reducer (Shift Register #4) . . . . . . . 392 12.4 Test Control Pins . . . . . . . . . . . . . . . 393 12.5 Block Diagram . . . . . . . . . . . . . . . . . 394 13 APPENDIX: GLOBAL SIGNAL DICTIONARY . . . . . . . . 395 14 APPENDIX: BLOCK DIAGRAM . . . . . . . . . . . . . 414 15 APPENDIX: CHIP INTERCONNECT DIAGRAM . . . . . . . 416 CVAX CPU CHIP DESIGN SPECIFICATION Page 10 REVISION HISTORY REVISION HISTORY ---------------- REV DATE REASON --- ---- ------ 3.00 Pass 3.00 changes incorporated into spec. 2.00 20-Feb-87 Pass 2.00 changes incorporated into spec. 1.06 23-Jun-86 ALL ECOs (as of 1-Jun-86) incorporated into spec. 1.05 28-Oct-85 ALL ECOs (as of 15-Oct-85) incorporated into spec. Section 6: rewritten to reflect microarchitecture. Section 12 : Renamed TEST_0 to TEST and TEST_1 to TEST_OUT (mux'ed with CWB, all registers now sample on PHI1. Section 14 : deleted CM and BR, added CWB, INHIB_CP_OUT and MW_TO_W, changed TEST_0 to TEST, TEST_1 to TEST_OUT, FPU_CC<2:0> to FPU_CCZ, FPU_CCV, FPU_CCN changed timing on LOAD_PSL 1.04 6-Sep-85 Section 12.4.3 : Changed BROADCAST bit definition to forcing BASIC_BROADCAST only. Section 14 : deleted BCOND_TRUE, added all test reducer outputs and scan/reducer controls added TEST_BRO and ONE_SLOT_FREE. 1.03 20-Aug-85 All ECOs (as of 5-14-Aug-85) incorporated into spec. Section 9 : changed microcode restriction on use of BRANCH IID after changing HSIR,IPL, or ICCS<6>, changed value of WSPUR<7:4> during a READ HSIR to 111, added restrictions on what kind of cycle can immediately follow a READ INT.ID Section 14 : add LD_VIBA_AND_PC, remove WILL_LOAD_VIBA and WILL_LOAD_PC, modify waveforms on IID_IRQ and FPD_INT_PENDING, assertion of IB_FILL_ERR is now LOW Section 14 : added ICCS_6, deleted DPC_VALID, modified timing of DELTA_PC,IB_FILL_REQ,IID_LD 1.02 26-Jun-85 Section 2 : fixed address specifications, added WSN definition, fixed testability stuff Section 3.9 : Change CC Logic to reflect FPU CCs being mapped through CC Map. Also added ACBD, ACBF, and ACBD to Branch Test Logic. Section 3.11 : Change State Logic to reflect bit clearing groups. Section 3.14 : Updated Microcode Restrictions for Q Register, PSL and RLOG. Section 9 : modified spec to reflect redefinition of SISR to HSIR Section 10 : modified spec to reflect change in method of inplementing phase synchronization Section 14 : added G_S%FLUSH_H chged CLK1_IN to CLKA and CLK2_IN to CLKB and LD_PSL_FROM_FPU to LOAD_FPU_CC Section 14 : added G_S%FPD_INT_PENDING_H AND G_S%FP_INTEGER_H deleted IBOX_TRAP_DRY and IBOX_TRAP_HLT Section 14 : added G_S%PSL_T and G_S%READ_HIT 1.01 3-May-85 Section 2 : edits based on RMS's comments...notably integer overflow, 2.1.2 was wrong, syntax problems Sections 2.3.1,2.3.4 : Changed I-box microaddress format for execution dispatch, specifier dispatch Section 3.1.4.1: Removed dual A-Bus addresses where not needed Section 3.5.1: Changed default ALU operation to PASS.B for MEMREF/MXPR/READ. Section 3.5.1.3: Defined PSL.V for SMULS Step Section 3.8.3: Removed notes section and added PSL Distribution Section Section 3.9.4: Modified Integer Overflow Logic. It is now a trap line to uSEQ. Section 9.* : Added SISR to spec Section 9.2 : Changed MXPS[INT.ID] to read out to W_SPUR<4:0> Section 9.4 : Added MEMERR and CRD to verbal description Section 11.* : Control field summary changed to reflect actual microcode Section 12.3 : Added internal pull-down resistor on TEST_0 Section 12.6 : Changed CP to CP.STA and CP.DAT Section 13.0 : Eliminated from Design Specification Section 14.* : Added BIU <-> CACHE signals Section 14.* : Added WILL_LOAD_VIBA,chg'd LD_PSL_FROM_FPU,LOAD_PSL,READ_DATA_PRS Section 14.* : Added MBOX_BM,MW_BUS,MW_DRIVE to signal list, chg assertion of all traps and STALL to '_L', chg spacing to allow longer names. Added chip pins, and bus capacitance removed MBOX from IB_DATA_PRS dest. 1.00 26-Mar-85 Preliminary version. CVAX CPU CHIP DESIGN SPECIFICATION Page 11 INTRODUCTION 1 INTRODUCTION 1.1 Scope This document specifies the design of a CMOS/VLSI chip (CVAX) that implements a VAX central processor. This specification describes the internal organization and characteristics of the CPU chip. This specification does not describe the operation of CVAX. For further information, the applicable documents should be consulted. 1.2 Applicable Documents VAX Architecture Standard (DEC Standard 032) CVAX CPU Chip Engineering Specification CVAX Clock Chip Engineering Specification CVAX Microcode 1.3 CVAX CPU Chip Organization The CVAX CPU chip consists of the following major sections. 1.3.1 Instruction Unit (I Box) - The Instruction Unit contains the instruction prefetch buffer, the initial decode PLA, and associated logic. It prefetches the instruction stream, generates microprogram fork addresses, and provides instruction data to the E Box. 1.3.2 Execution Unit (E Box) - The Execution Unit contains the VAX register file, the microcode scratch register file, the page table base registers, the arithmetic/logical unit (ALU), and other computational facilities. It performs address and data computations for executing VAX instructions and address translations. 1.3.3 Memory Translation Unit (M Box) - The Memory Translation Unit contains the translation buffer, the page table length registers and comparators, and the address translation logic. It performs virtual to physical address translations. In addition, the M Box controls the incoming and outgoing data latches, rotators, and swappers. CVAX CPU CHIP DESIGN SPECIFICATION Page 12 INTRODUCTION 1.3.4 Bus Interface Unit (BIU) - The Bus Interface Unit controls the arbitration of the major intrachip data bus (IDAL); the protocol on the external interface; and the operation of the Cache. 1.3.5 Microsequencer - The Microsequencer determines the address of the next microword to be fetched and executed from the Control Store. It also oversees the generation and execution of microtraps. 1.3.6 Interrupt Logic - The Interrupt Logic mediates hardware interrupt requests against the current IPL and generates an interrupt request to the I Box, if necessary. 1.3.7 Control Store - The Control Store contains 1600 x 41 words of microcode which direct all operations in the chip. 1.3.8 Cache - The onchip Cache contains 1k bytes of high-speed memory for local storage of frequently referenced memory data. 1.3.9 Clock Logic - The Clock Logic shapes the two MOS level input clocks into the four precision internal clocks. 1.4 Block Diagram A block diagram of the chip may be found at the end of this specification. CVAX CPU CHIP DESIGN SPECIFICATION Page 13 INSTRUCTION (I) BOX 2 INSTRUCTION (I) BOX The I Box controls instruction sequencing and prefetching. During the microcycle, the I box predicts what the next dispatch should be. Once the microinstruction arrives, the I Box executes the appropriate dispatch and state changes. The I Box cycle begins when the Microsequencer issues a microinstruction with a DEC.NEXT code in the Branch Condition Select (BCS) field and the specifier counter is set to 0 (by the completion of a previous instruction or the execution of a LOAD_V&PC microinstruction). At IID, the I Box selects a microcode address to drive to the Microsequencer. This microcode address points to the start of the microprogram for the instruction being processed. If the instruction has specifiers, the microaddress dispatches to the appropriate Specifier Decode routine. If there are no specifiers, the microaddress points at the execution flow for the instruction, and the execution phase happens immediately. The specifier flows end with a microinstruction that contains another DEC.NEXT command in the BCS field. At this point, the I Box sends either the address for the routine to analyze the second specifier, or, if there are no other specifiers, the address of the execution microcode for the instruction. The specifier flows are called for each specifier in the instruction. Once all specifiers have been decoded, the I box sends a dispatch address for the execution flow for the instruction. The I Box instruction prefetcher operates in parallel with the execution hardware on the chip. Whenever a longword in the queue is empty, the queue is not halted, and the BIU has free cycles, a request is issued to read the next aligned longword in the instruction stream. This longword is copied into the PFQ. When a LOAD_V&PC microinstruction is detected, the PFQ is flushed, and new instructions must be fetched before the processor can proceed. In this case, the I Box sends a dummy address as a reply to any DEC.NEXT request, and microcode casing handles all LOAD_ID requests. In either case, the microcode enters a loop until instruction data arrives at the I Box. The I Box has four sections: the Prefetcher, the IPLA, the Next Address Generator, and some miscellaneous registers and control. 2.1 Prefetcher 2.1.1 Prefetcher Data Path - The Prefetcher Data Path handles I Stream data. It holds up to 3 prefetched longwords from memory, rotates the instructions to bring the opcode to the front, and stores literals and displacements for the E Box. The datapath is maintained by the Prefetcher Control and consists of the following blocks: CVAX CPU CHIP DESIGN SPECIFICATION Page 14 INSTRUCTION (I) BOX 2.1.1.1 Instruction Prefetch Queue - The Instruction Prefetch Queue consists of three longword registers, each of which can hold an aligned longword from memory. The registers comprise a three-entry queue. Data is loaded into the tail of the queue from the the Internal DAL and stored in the empty register closest to the head of the queue. 2.1.1.2 Instruction Byte Rotator - The Instruction Byte Rotator can select up to six contiguous bytes in the Prefetch Queue (for example, an opcode, a specifier, and four bytes of data) starting at any byte in the lowest longword. The position of the starting byte is specified by the IB Pointer (low two bits of the PC). 2.1.1.3 Instruction Data (ID) Register - This longword register is the mechanism by which the E Box data path gets data from the instruction stream (displacements, etc.). Data is loaded from the Byte Rotator, either automatically by the I Box or explicitly by the microinstruction; it is sign extended to longword in the same cycle in which it is loaded. The ID register is automatically loaded by the I Box when: o The Microaddress Generator detects that the opcode is a branch instruction (opcodes 10-15,18-1F,30-31). The IDR is loaded with the byte or word branch displacement and sign extended to longword length. o The Microaddress Generator detects that the specifier mode is byte, word, or longword displacement (specifier mode A, B, C, D, E, F). The bytes containing the byte, word, or longword displacement are loaded. The register is then sign extended to longword length. NOTE: Specifiers of type 8F are NOT included here. Immediate operands must be explicitly moved to the IDR by microcode. o The Microaddress Generator detects that the specifier byte is 9F (absolute). The four bytes containing the address of the operand are loaded into the ID register. Explicit loads of the ID register can be done by microcode CASE. The amount of data extracted from the instruction stream is based on the Data Length register. When LOAD ID CASE is issued, any of three things may happen. The IDR may be loaded properly, not loaded because the PFQ is dry and not halted, or not loaded because the PFQ is dry and halted. In the second case, the microcode cases to a location which contains another LOAD ID case, forcing a loop. In the third case, a different case target is CVAX CPU CHIP DESIGN SPECIFICATION Page 15 INSTRUCTION (I) BOX used; the target address contains a call to a subroutine to resolve the prefetching problem. The ID register is sign extended based on the value of the DL register. Note that the sign extension may change from its original value if DL is changed before the data is read. For example: suppose the ID register was loaded with a word offset for a branch. Now suppose that the MISC field DL.BYTE is issued before the data is read to the B-bus. The data in the ID register will now look like a sign- extended byte, effectively destroying half of the offset data. Now suppose the DL register is changed to WORD again before the data is read. In this case, there will be no change in the ID register contents, and it will still look like a sign-extended byte. The ID register may be read to the B-bus. It is addressed through the B port as register 0A#16. 2.1.2 Prefetch Controller - The BIU fetches I stream data whenever the Prefetch Controller requests it and the DAL is available. The Prefetch Controller signals the BIU that it wants I Stream data by asserting the IB_REQ line. It asserts IB_REQ only when the PFQ has an empty longword AND the prefetcher is not halted. If the I Stream read results in any kind of error (TB miss, data parity error, etc.), the Hardware Prefetch Halt Bit is set and no more prefetching is done. This prevents prefetching from interfering with memory management operations. When the Prefetch Stack runs out of data, a special microaddress (IE.IB.HALTED) is sent to the Microsequencer; a microcode subroutine then handles the problem. The I Box does not react immediately to prefetching errors because the prefetched data may not be used. The Hardware Prefetch Halt Bit is cleared by the RESTART PREFETCH command, and as a side effect of the MISC fields that load VIBA and PC. The microcode can stop prefetching by setting the Microcode Prefetch Halt Bit in the I Box. This microcode-controllable bit can be set and cleared by the commands DISABLE PREFETCH and ENABLE PREFETCH. It is cleared by the RESTART PREFETCH command. A four bit register called the IB Pointer is kept to point to the next valid byte in the lowest longword of the Prefetch Queue. As data is drawn out of the stack by the Microaddress Generator, this pointer is incremented by Delta PC. When the macroinstruction stream branches, nothing in the stack is usable. It is flushed as a side effect of the MISC fields that load VIBA and PC. Prefetching is started up again, and the IB Pointer is set to the start of the new instruction ,i.e. it is set equal to bits <1:0> of the PC. 2.2 The Instruction PLA (IPLA) The IPLA contains information about VAX macroinstructions. IPLA inputs are the eight-bit opcode and a ninth bit called XFD, which indicates an CVAX CPU CHIP DESIGN SPECIFICATION Page 16 INSTRUCTION (I) BOX extended opcode. The IPLA stores the following data for all valid opcodes with one or more specifiers: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 +-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ | FPO | FPA | Execution Dispatch Address |Data Length|Data Length|Data Length| |Instr|Instr| | spec 1 | spec 2 | spec 3 | +-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 8 7 6 5 4 3 2 1 0 +-----+-----+-----+-----+-----+-----+-----+-----+-----+ |Access Type|Access Type|Access Type| Number of | | spec 1 | spec 2 | spec 3 | Specifiers | +-----+-----+-----+-----+-----+-----+-----+-----+-----+ <23> The FPO bit is true if the instruction is an integer instruction that is accelerated via the FPA. This bit is used in conjunction with the F Box Instruction bit and the FPA Present bit to enable data broadcasts to the FPA. <22> The F Box Instruction bit is true if the opcode is for an F, D, or G floating point instruction. It is NOT true if the opcode is served by the CFPA but included in "warm" FPA functions. This prevents an illegal opcode dispatch on optimized integer instructions when there is no FPA in the system. If this bit is true and there is no FPA present, an illegal opcode dispatch is taken. <21:15> These bits represent 7 of 11 bits for the execution dispatch address. <14:3> The IPLA has a multiplexor on some of its outputs. This mux selects one of the six Data Length fields and one of the six Access Type fields. This data is loaded into the AT/DL Register. <2:0> The specifier counter field contains the number of operands the instruction requires. At IID, this value is loaded into the specifier counter, which is decremented every time a specifier dispatch is given. When the counter reaches 1, an execution dispatch is done. When the counter reaches 0, an IID is executed. EXTRA AT/DL PLA There is a supplementary PLA which holds the AT and DL values for specifiers four through six if an instruction has more than three operands. CVAX CPU CHIP DESIGN SPECIFICATION Page 17 INSTRUCTION (I) BOX 2.3 Microaddress Generator The Microaddress Generator creates microaddresses for entry points into microcode flows for instruction execution, illegal opcodes, and specifier decode. During PHI2 and PHI3, the Microaddress Generator predicts the next dispatch based on the data in the Prefetch Queue (PFQ). The next values of important I Box state registers are also predicted. At PHI4, the microinstruction is decoded and selection from the possible choices begins. 2.3.1 IID Dispatch (used When SPEC.CTR = 0) - The IID dispatch takes one of three forms: exception dispatch, if an unusual condition is pending when IID is detected; execution dispatch, if the IID PLA shows that an instruction has no operands or the instruction is a simple branch; and first specifier dispatch, which is used for all other cases. Priority for IID dispatches is determined from the following list: o Exception dispatches, as ordered in the exception dispatch table o Execute dispatches for zero operand instructions as per the execution dispatch table o Specifier dispatches as per the specifier dispatch table 2.3.1.1 IID Exception Dispatch - Several exception conditions are checked by the I Box prior to an IID dispatch. If one of these conditions is present, a special microaddress is driven to handle the problem. Note that IID is not asserted for these cases. The following table shows the exceptional conditions recognized and the dispatch taken for each: | VAX |INTERRUPT|PSL| IB | uADDR | TRAP | PENDING | | DRY | (hex) | REQUEST | | | | | | | | | +----------+---------+-------+--------+----------------------------------- | 1 | x | x | x | IE.VAX.ARITH.TRAP 280 | 0 | 1 | x | x | IE.VAX.INTERRUPT 302 | 0 | 0 | 1 | x | IE.VAX.TRACE.TRAP 200 | 0 | 0 | 0 | 1 | IE.IID.STALL 7FE CVAX CPU CHIP DESIGN SPECIFICATION Page 18 INSTRUCTION (I) BOX 2.3.1.2 IID Execution Dispatch - If no exceptions are pending at IID and the IID PLA output indicates that the instruction being decoded has no operands, an execution dispatch is issued immediately. Note that an opcode of FD will be treated as a zero-operand instruction. An illegal opcode dispatch occurs if the instruction is a floating point type and there is no FPU present in the system, or if the opcode is illegal. Note that illegal opcodes are treated as zero operand instructions by the I Box. The table below shows dispatch addresses for execution flows reachable from IID, in order of decreasing priority: (PC) | PSL.FPD | ADDRESS | DELTA PC | IDR FUNCTION | COMMENTS ------------+-----------+-----------------------+----------+--------------+------------------ XXXXXXXX | X | RSRV.INST.FLT 282 | 0 | NONE | ILLEGAL OPCODE DISPATCH ------------+-----------+-----------------------+----------+--------------+------------------ NOT FD#16 | 1 | FPD 380 | 1 | NONE | FIRST PART DONE DISPATCH ------------+-----------+-----------------------+----------+--------------+------------------ 00000XXX | 0 | SEE TABLE OF "OTHER | 1 | NONE | 0 OPERAND INSTRUCTIONS 00X10000 | 0 | OPCODES" IN SECTION | 1 + b,w | IDR <-IB(b,w)| BSBB...BSBW 00X10001 | 0 | 2.10.4 | "" | " | BRB...BRW 0001001X | 0 | | | | 0001010X | 0 | | "" | " | ALL BRANCH INSTRUCTIONS 00011XXX | 0 | | | | 00000011 | 0 | | 1 | NONE | BPT INSTRUCTION 11111100 | 0 | | 1 | NONE | XFC INSTRUCTION 11111101 | X | | 1 | NONE | XFD (TWO BYTE OPCODES) 2.3.1.3 Specifier Dispatch - If an instruction has specifiers, detection of an IID will cause a dispatch to the general specifier flows based on the first specifier. The table below describes the dispatch possibilities: CVAX CPU CHIP DESIGN SPECIFICATION Page 19 INSTRUCTION (I) BOX <7:4> <3:0> Specifier Type | Spec | RN | Dispatch Address | Delta PC | IDR LOAD | | | | |(add 1 at IID)| FUNCTION | -------------------+--------+-----+-----------------------------+--------------+-------------------+ short literal | 0-3 | 0-F | SPEC.SH.LIT 080 | 1 | NONE | index | 4 | 0-E | SPEC.INDEX 082 | 1 | NONE | index | 4 | F | SPEC.RSRV.ADDR 08A | 1 | NONE | register | 5 | 0-E | SPEC.REG 084 | 1 | NONE | register | 5 | F | SPEC.RSRV.ADDR 08A | 1 | NONE | register deferred | 6 | 0-E | SPEC.REG.DEFER 086 | 1 | NONE | register deferred | 6 | F | SPEC.RSRV.ADDR 08A | 1 | NONE | autodecrement | 7 | 0-E | SPEC.AUTODEC 088 | 1 | NONE | autodecrement | 7 | F | SPEC.RSRV.ADDR 08A | 1 | NONE | autoincrement | 8 | 0-E | SPEC.AUTOINC 08C | 1 | NONE | autoincrement def | 9 | 0-E | SPEC.AUTOINC.DEFER 090 | 1 | NONE | displacement | A,C,E | 0-F | SPEC.BWL.DISP 094 | 2,3,5 | IDR <- IB(BWL).SXT| displacement def | B,D,F | 0-F | SPEC.BWL.DISP.DEFER 096 | 2,3,5 | IDR <- IB(BWL).SXT| immediate | 8 | F | SPEC.IMMEDIATE 08E | 1 | NONE | absolute | 9 | F | SPEC.ABSOLUTE 092 | 5 | IDR <- IB(LW) | -------------------+--------+-----+-----------------------------+--------------+-------------------+ The following table shows the dispatch addresses for INDEXED operands: <7:4> <3:0> Specifier Type | Spec | RN | Dispatch Address | Delta PC | IDR LOAD | | | | |(add 1 at IID)| FUNCTION | -------------------+--------+-----+-----------------------------+--------------+-------------------+ short literal | 0-3 | 0-F | INDEX.SH.LIT 0C0 | 1 | NONE | index | 4 | 0-E | INDEX.INDEX 0C2 | 1 | NONE | index | 4 | F | INDEX.RSRV.ADDR 0CA | 1 | NONE | register | 5 | 0-E | INDEX.REG 0C4 | 1 | NONE | register | 5 | F | INDEX.RSRV.ADDR 0CA | 1 | NONE | register deferred | 6 | 0-E | INDEX.REG.DEFER 0C6 | 1 | NONE | register deferred | 6 | F | INDEX.RSRV.ADDR 0CA | 1 | NONE | autodecrement | 7 | 0-E | INDEX.AUTODEC 0C8 | 1 | NONE | autodecrement | 7 | F | INDEX.RSRV.ADDR 0CA | 1 | NONE | autoincrement | 8 | 0-E | INDEX.AUTOINC 0CC | 1 | NONE | autoincrement def | 9 | 0-E | INDEX.AUTOINC.DEFER 0D0 | 1 | NONE | displacement | A,C,E | 0-F | INDEX.BWL.DISP 0D4 | 2,3,5 | IDR <- IB(BWL).SXT| displacement def | B,D,F | 0-F | INDEX.BWL.DISP.DEFER0D6 | 2,3,5 | IDR <- IB(BWL).SXT| immediate | 8 | F | INDEX.IMMEDIATE 0CE | 1 | NONE | absolute | 9 | F | INDEX.ABSOLUTE 0D2 | 5 | IDR <- IB(LW) | -------------------+--------+-----+-----------------------------+--------------+-------------------+ 2.3.2 Second IID Dispatch ( Spec Counter = 0) - If the opcode at IID is FD, the microcode branches to a location which reissues the IID. Furthermore, the E Box sets the opcode register to 0FD CVAX CPU CHIP DESIGN SPECIFICATION Page 20 INSTRUCTION (I) BOX and increments PC by 1. When the second IID is executed, the opcode register is set to 1xx, where xx is the second opcode byte. With second.iid set, the I Box interprets an IID operation differently. This special IID acts much like the normal one, but interrupts and the trace bit are ignored. Furthermore, second IID prevents the backup PC from being loaded with the current PC (this is an E Box function). This keeps the backup PC from pointing to the second byte of a two-byte opcode. Second IID is also used by microcode while waiting for the PFQ to fill after a dispatch to XFD (due to PFQ dry and not halted condition) takes place. The following table describes the dispatch possibilities at Second IID time, in order of decreasing priority: Specifier Type | Dispatch Address | Delta PC | IDR LOAD | or Condition | | | FUNCTION | ----------------------------------+------------------------------+--------------+-------------------+ PFQ DRY, NOT HALTED | XFD 7FE | 0 | NONE | PFQ DRY, HALTED | DEC.NEXT.HALTED 382 | 0 | NONE | ----------------------------------+------------------------------+--------------+-------------------+ Execute Dispatch | As per IID dispatch | 0 | NONE | ----------------------------------+------------------------------+--------------+-------------------+ SPECIFIER DISPATCH | SEE SPECIFIER DISPATCH TABLE (TREAT AS IID) | ----------------------------------+-----------------------------------------------------------------+ 2.3.3 Specifier Decode Dispatches - The specifier dispatch causes the I Box to examine the specifier byte. As described above, if the spec counter is 1, the dispatch will be to the execution flows. If the spec counter is 2, the dispatch logic must examine the specifier mode and dispatch to optimized execution flows if the mode is 5 (register). Otherwise, the dispatch will be to the specifier flows. If the dispatch is to the execution flows, the address will look like this: Specifier Type| Dispatch Address | Comments ==============+============================+=========== Register Mode | 10xxxxxxx10 | optimized Other Mode | 10xxxxxxx00 | similar to IID opcode dispatch The dispatch will be from the following table, in order of decreasing priority: CVAX CPU CHIP DESIGN SPECIFICATION Page 21 INSTRUCTION (I) BOX Specifier Type | Dispatch Address | Delta PC | IDR LOAD | or Condition | | | FUNCTION | ----------------------------------+---------------------+--------------+-------------------+ EXECUTE (SPEC COUNTER = 1) | EXECUTION FROM IPLA | 0 | NONE | ----------------------------------+---------------------+--------------+-------------------+ PFQ DRY, NOT HALTED | DEC.NEXT.STALL | 0 | NONE | PFQ DRY, HALTED | DEC.NEXT.HALTED | 0 | NONE | ----------------------------------+---------------------+--------------+-------------------+ OPTIMIZE | DISP. TO OPTIMIZED | | | (SPEC.MODE = 5,SPEC.CTR = 2) | EXECUTION FLOWS | 1 | NONE | NOTE: THIS CLEARS SPEC COUNTER | AS PER ABOVE TABLE | | | ----------------------------------+---------------------+--------------+-------------------+ SPECIFIER DISPATCHES | SEE SPECIFIER DECODE TABLE | -------------------------------------------------------------------------------------------+ Illegal addressing modes The illegal mode/access combinations are Register Mode (5) with access type of Address (A) and Short Literal (0-3) with access types of Address, Modify, or Field (A,M, or V). If such a condition is detected, the MICROCODE will go to RSRV.ADDR.FLT. * The index mode prefix is treated as a one-byte specifier. The microcode issues a DEC.NEXT to parse the real specifier; the I box sets a flag at index dispatch time that indicates to the next cycle I box decode the presence of the index mode specifier. 2.3.4 MicroAddress Format - The following table shows the format for the I box microaddress bus contents. CVAX CPU CHIP DESIGN SPECIFICATION Page 22 INSTRUCTION (I) BOX Dispatch Type Spec Counter Microaddress Comments ---------------------+-------------+------------------------------------+------------------------------------- Exception | 0 | Fixed CONSTANTS | SEE TABLE IN SECTION 2.3.1.1 Execute | 1 | 10xxxxxxx00 | SEE TABLE IN SECTION 2.10.3 Optimized Execute | 2 | 10xxxxxxx10 | SEE TABLE IN SECTION 2.10.3 0-operand Execute | 0 | 001100xxxx0 | SEE TABLE IN SECTION 2.10.3 Illegal Opcode | 0 | RSRV.INST.FLT 282 | IB Dry | any | DEC.NEXT.STALL 300 | IB Halted & Dry | any | DEC.NEXT.HALTED 382 | Normal Specifier | > 1 | 000100xxxx0 | SEE TABLE IN SECTION 2.3.1.3 Indexed Specifier | > 1 | 000110xxxx0 | SEE TABLE IN SECTION 2.3.1.3 ---------------------+-------------+------------------------------------+------------------------------------- 2.3.5 Delta PC Logic - The Delta PC logic is integrated with microaddress generation. It generates a three bit value to be added to the PC when the next piece of instruction data is used. Whenever data is not being requested from the Prefetch Stack, delta PC must be zero. Delta PC is used by the PC function of the E Box data path, and by the Prefetch Controller. The controller uses it to increment the IB Pointer that specifies the next byte to be used in the Prefetch Stack. PREFETCH QUEUE DRY CALCULATION These values for Delta PC may also be interpreted as the minimum number of valid bytes which must be in the PFQ prior to a dispatch for the dispatch to be succesful and the PFQ to be considered NOT dry. CVAX CPU CHIP DESIGN SPECIFICATION Page 23 INSTRUCTION (I) BOX Condition Delta PC -------------------------------- IID forks ( spec counter = 0 ): Exceptions 0 FPD 1 Opc = Branch byte disp. 2 Opc = Branch word disp. 3 Opc = FD (hex) 1 Zero operand opc. 1 First Specifier see note ( + 1 for opcode) PFQ dry 0 Specifier forks ( spec counter > 0 ): Specifier Decode see note Optimize (CTR=2,MODE=5) 1 (to skip over register specifier) Execute (CTR = 1) 0 NOTE: OPTIMIZE DISPATCH CLEARS SPEC COUNTER PFQ dry 0 LOAD ID: DL=0 (BYTE) 1 DL=1 (WORD) 2 DL=2 (LONG) 4 DL=3 (QUAD) 4 PFQ DRY 0 NOTE: In these cases the amount of data taken out of the Prefetch Stack depends on the specifier mode. Spec Mode Spec Code Delta PC ------------------------------------------- byte disp. A 2 byte disp. deferred B 2 word disp. C 3 word disp. deferred D 3 longword disp. E 5 longword disp. def. F 5 ABSOLUTE 9(F) 5 other 0-9 1 If this is an IID fork, delta PC is increased by 1 to account for the opcode. 2.4 Miscellaneous Register Descriptions This section describes some of the registers in the I Box. CVAX CPU CHIP DESIGN SPECIFICATION Page 24 INSTRUCTION (I) BOX 2.4.1 Current Specifier / Register Number Latch (SPEC.RN) - The Current Specifier / Register Number Latch holds the address mode and GPR address of the last specifier decoded. It is also used with the RLOG facility in the E Box data path section. When RLOG is pushed, RN supplies four bits of the data that is pushed. The SPEC.RN register can be read via a mem_req microinstruction; RN can be written via a mem_req microinstruction, as well. SPEC.RN is loaded during any DEC.NEXT when the specifier counter is not = 1 with bits <7:0> of the specifier. Note that when the specifier is short literal (modes 0-3), the SPEC.RN register holds the entire specifier. Microcode gets the literal by reading it from this register. The RN.OLD register is also part of the SPEC.RN logic. RN.OLD is updated only when the specifier being decoded may be a destination address for the instruction in progress. There is also a microcode command to load RN with RN.OLD . 2.4.2 FPU Present - Whenever RESET is asserted, one of the CP_STA lines is pulled down by the CFPA if it is present. If the CFPA is not present, that CP_STA line will be pulled up by an external resistor. The status of this pin will be sensed by the FPA logic on CVAX, which will assert the signal G_S%FPU_IS_THERE_H if the FPA is present. The I box will set the FPU_PRESENT bit only if RESET is asserted and G_S%FPU_IS_THERE_H is asserted. If the FPU_PRESENT bit is set, floating point instructions will cause a normal GSD dispatch at IID. If this bit is clear and the IID PLA entry for an instruction specifies F Box execution, an illegal opcode dispatch occurs. 2.4.3 VAX Trap Request - This bit can be set or cleared by SPECIAL MISC1 microinstructions. When set, the I Box's next IID dispatch will be to a trap routine. The VTR bit must be cleared by the handling routine before normal execution can be resumed. 2.4.4 Specifier Counter - This facility indicates which specifier is presently being decoded. During an IID dispatch (spec counter = 0) where a normal dispatch happens, the specifier counter is loaded with the number of specifiers for the instruction as listed in the IPLA. At each specifier dispatch, it is decremented. When the counter reaches 1, the next dispatch will be to the execution flow. When the counter reaches 0, the next dispatch will be an IID. The specifier counter is also used to address the working registers CVAX CPU CHIP DESIGN SPECIFICATION Page 25 INSTRUCTION (I) BOX for specifier decode addressing. The specifier counter is not decremented at index mode dispatches (i.e. dispatches where INDEX_EXPECTED is set). SPEC.CTR is cleared at execution of any microinstruction which loads VIBA and PC. It is also cleared whenever a register-mode optimized execute dispatch is generated. 2.4.5 Data Length And Access Type - The data length and access type of the specifier presently being worked on are kept in the AT/DL register. The codes for the access type are: 0 A Address Source 1 V Field Source 2 R Read Source 3 M Modify Source The access type portion of the AT/DL register may be written only on specifier dispatches with a value from the IPLA. The data length portion of the AT/DL register may be written in the following ways: o Automatically with a value from the IPLA on specifier dispatches. o Forced by the MISC field. o Forced to byte (00) at execution dispatches for four instructions: SOBGTR,SOBLEQ,BLBC,BLBS. The codes for the data lengths are: 0 BYTE 1 WORD 2 LONG 3 QUAD 2.4.6 PSL Bits - The following PSL bits are shadowed in the I Box: < 4> T <27> FPD <30> TP These bits are loaded whenever A port address 28 is detected as a destination. CVAX CPU CHIP DESIGN SPECIFICATION Page 26 INSTRUCTION (I) BOX MICROCODE NOTE IID may not occur during or FOR 2 CYCLES after a microinstruction in which these bits (T,FPD,TP) are changed. 2.4.7 Second IID Flag - This flag is set whenever the I box detects that it is dispatching to address XFD or IE.IID.STALL . It is cleared during a succesful dispatch. 2.4.8 Index Expected Flag - This flag is set whenever the I box dispatches to an index mode specifier. It is cleared at a succesful dispatch. 2.5 I Box Initialization At RESET Signal The following state bits of the I Box are initialized when RESET is asserted: STATE INITIALIZED TO -----------------------------------------------------+-------------------------- PFQ VALID BITS <2:0> | 0 HARDWARE PREFETCH HALT | 1 DELTA_PC <2:0> | 0 VAX TRAP REQUEST BIT | 0 FD bit | 0 SPECIFIER COUNTER | 0 INDEX EXPECTED | 0 SECOND IID EXPECTED | 0 2.6 I Box Related Microinstructions In the B field: Code Operation Comment -----+-----------------+-------------------------------------------------------- 0A B port is ID register (read only when B port is source, not dest) CVAX CPU CHIP DESIGN SPECIFICATION Page 27 INSTRUCTION (I) BOX In the MISC field: Code Operation Comment -----+-----------------+-------------------------------------------------------- 05 RESTART.PREFETCH clear both prefetch disable bits (at phi1) 06 DISABLE.PFQ.PREF set ucode prefetch disable bit ( at phi1) 07 ENABLE.PFQ.PREF clear ucode prefetch disable bit ( at phi1) 08 CLEAR.RN clear RN register (master at phi1, slave at phi3) 09 RN.MINUS.1 decrement RN register (master at phi1, slave at phi3) 0A RN.PLUS.1 increment RN register (master at phi1, slave at phi3) 0B RN.PLUS.DL.Q increment RN if DL=quad (master at phi1, slave at phi3) 0C DL.BYTE DL <-- byte (master at phi1, slave at phi3) 0D DL.WORD DL <-- word (master at phi1, slave at phi3) 0E DL.LONG DL <-- long (master at phi1, slave at phi3) 0F DL.QUAD DL <-- quad (master at phi1, slave at phi1) 17 RN.LOAD.OLD LOAD RN with RN.OLD during PHI3 (slave only) In the SPECIAL MISC1 field: MIB<37:33> Operation Comment ----------+-----------------------+-------------------------------------------- 1xx1x CLEAR.VAX.TRAP.REQ clear VAX TRAP REQUEST bit (master at phi1, slave at phi3) 0xx1x SET.VAX.TRAP.REQUEST set VAX TRAP REQUEST bit (master at phi1, slave at phi3) In the MEMREQ.REG field: (NOTE: These registers may be read via the W-spur; only RN may be written via the SPUR) Code Operation Comment ----+-----------------------+------------------------------------------------------------------ 03 OPCODE OPCODE.REG in bits <7:0> (Drive of spur is done by E Box) 04 SPEC.RN SPECIFIER MODE in bits <7:4>, RN in bits <3:0> In the BR.BCS field (Branch Microinstruction Only) Code Operation Comment ----+----------------------------------+--------------------------------------------------------- 28 DEC.NEXT request for decoder next dispatch 2A DL.BWL.AND.AT.RVM_DEC.NEXT IF DL = B,W, OR L AND AT R, V, OR M DEC.NEXT ELSE GOTO 2B AT.RVM_DEC.NEXT IF AT R, V, OR M DEC.NEXT ELSE GOTO 2C DL.BWL.AND.AT.R_DEC.NEXT IF DL = B,W, OR L AND AT = R DEC.NEXT ELSE GOTO 2D AT.R_DEC.NEXT IF AT = R DEC.NEXT ELSE GOTO 2E AT.AV_DEC.NEXT IF AT = AV THEN DEC.NEXT ELSE GOTO 2F DL.BWL_DEC.NEXT IF DL = B,W, OR L THEN DEC.NEXT ELSE GOTO 3B FPU/DL FPU.PRESENT,DL<1:0> = UTEST<2:0> (drive utest at phi2) 3C I I Box STATUS (FPD.IRQ, RMODE.OLD, RMODE) = UTEST<2:0> (drive utest at phi2) 3D OPCODE2-0 OPCODE<2:0> = UTEST<2:0> (drive utest at phi2) (Drive is done by E Box) 3E LOAD.ID CAUSES LOAD OF ID REGISTER, CASE ON WHETHER OR NOT THERE WAS ENOUGH. AT<1>,PFQ DRY & HALTED,PFQ DRY (whether halted or not) = UTEST<2:0> CVAX CPU CHIP DESIGN SPECIFICATION Page 28 INSTRUCTION (I) BOX 2.7 Microcode Restriction Summary o A recoverable microtrap may not happen in the same cycle as a CASE.ID.LOAD operation. o There must be 2 cycles after a change of the PSL before a DECNEXT operation can be done. o A load of VIBA and PC must be done after a PC<-BPC operation before any I Box call. o The following I Box state bits may be changed by the microcode in the same cycle as, or immediately before, any I Box dispatch or IDR load function, but the requested dispatch or load function will be based on the value of these bits BEFORE the requested change: FPU Existence bit Vax Trap Request bit o A case on PSL bits cannot immediately follow a write to the PSL bits o Loading of the PC in the same cycle as an I Box dispatch is allowed only in the case of the conditional branch code to enable a one-cycle branch-not-taken to be implemented. o The LOAD.IDR command can only use the DL register. The FORCE.LONG field is ignored. o Execution dispatch addresses for opcodes SOBGTR, SOBLEQ, BLBC, BLBS (addresses SOBX, BLBX) must differ in only one bit position. This is negotiable if there is STRONG need. o MXPS0[OPCODE] may be done in the same cycle as DEC.NEXT, but the results will be unpredictable. o MISC field operations INCR.RN, DECR.RN, and INCR.RN.IF.DL.Q may not occur in the same microinstruction as any operation that may cause a recoverable microtrap. o Note that SPEC.RN will keep its previous value for 1 microinstruction after a write.rn is executed. o Further detail and other restrictions can be found in the following ECO's: 1. Undefined W-spur bits are not driven and therefore return the precharged value, 1 (ECO 5JUN01PIR.1). 2. Invert MIB<12> (ECO 5JUL01AO.1). 3. Redefinition of global IID signal (ECO 5AUG01DWA.1). CVAX CPU CHIP DESIGN SPECIFICATION Page 29 INSTRUCTION (I) BOX 4. The PSL (PSL) and psl cannot be changed in the same cycle as, or the cycle before, DEC.NEXT (RMS 26-Jul-1985 memo). 6. The IPL part of the PSL cannot be changed in the same cycle as, or the cycle before, DEC.NEXT, or the cycle before that (interrupt) (RMS 26-JUL-1985 memo). 7. MISC.ENABLE.PREFETCH, MISC.DISABLE.PREFETCH, and MISC.RESTART.PREFETCH must not happen in the same cycle as or in the cycle before and I Box dispatch (DEC.NEXT or CASE.ID.LOAD) 2.8 SN Output The I Box must generate a working register address for use by the E Box. This value is dependent on the specifier counter, and is updated whenever an I Box dispatch is done. The following table shows the working register address as a function of the current specifier number. Specifier WR Value sent to E Box Number number as G_S%SN_H<2:0> ---------------------------------------------------- 1 0 0 2 2 2 3 4 5 4 7 4 5 3 7 6 1 6 2.9 I Box Testability Hardware There will be a LFSR attached to the outputs of the IPLA sense amp for testing the contents of the IPLA ROM. The order of bits in this LFSR will be the same as the order described above for the IPLA outputs. The CVAX CPU CHIP DESIGN SPECIFICATION Page 30 INSTRUCTION (I) BOX feedback taps in the LFSR are located as follows: PRIMITIVE SEARCH PROGRAM VERSION 1.3 MARCH 9, 1986 DATE = 04-24-86 TIME = 09:14 HRS No. of Stages in LFSR = 12 No. of XOR Gates used for feedback = 3 Primitive Table: |==========================================================================| || # | POLYNOMIAL * | FEEDBACK TAP POSITIONS || |==========================================================================| || 1 | 1000001101001 B1 | 12 6 5 3 || || 2 | 1000010011001 B1 | 12 7 4 3 || || 3 | 1110000000101 B1 | 12 11 10 2 || || 4 | 1000110000101 B1 | 12 8 7 2 || || 5 | 1001000001101 B1 | 12 9 3 2 || |==========================================================================| || 5 primitives found in 40 trials || |==========================================================================| LFSR DESIGN ACCEPTED -- .-.-.-.-.-.-.-.-.-.-.-.-. <--| | | | | | | | | | | | |<-- `+`-`-`+`-`-`-`-`-`+`+`-` | | | | CVAX CPU CHIP DESIGN SPECIFICATION Page 31 INSTRUCTION (I) BOX 2.10 I Box Schematics And Their Functions 2.10.1 I_ADDRESS_GENERATOR (IAG) - The address generator creates addresses on the IMAB (G_S%IMAB_H) based on dispatch information from the dispatch pla (see I_DISPATCH_PLA) and the IID logic (see I_IID_LOGIC). 10 bits of address are generated, and bit <0> of the IMAB is always 0. 2.10.2 I_AT_DL_REG (IAD) - This schematic contains two 2-bit registers for storing the access type and data length of the current specifier. It also includes a multiplexor which chooses one of six possible AT and DL values from the outputs of the IPLA (see I_IPLA). The multiplexor is controlled by a value based on the specifier counter and the number of specifiers the current instruction has. 2.10.3 I_DATAPATH (IDP) - The datapath receives instruction data from the IDAL bus and stores it in three longword registers. The datapath also sorts this data and selects the next six bytes of the instruction stream for processing. Some of this data is loaded into the Instruction Data Register for use by the E Box. The first two bytes of the instruction data are decoded by the I Box control hardware to determine the correct I Box dispatch for the next DEC.NEXT operation. 2.10.4 I_DP_DRIVERS (IDD) - This logic is primarily composed of large drivers for controlling the datapath. Inputs come mainly from the prefetch queue controller (see I_PFQ_CONTROL). 2.10.5 I_DISPATCH_PLA (IP1) - The dispatch PLA determines what kind of dispatch will be done at the next DEC.NEXT operation. It is a self-timed PLA, needing only one clock to operate. The programming file for the dispatch PLA is found below in both PLAD and binary format. Note that some outputs of this PLA are taken directly from product terms, so the number of true PLA outputs is less than the number indicated in the PLAD format data. 2.10.5.1 I_DISPATCH_PLA PLAD File - ! ! Description for the address prediction PLA in the I-box ! CVAX CPU CHIP DESIGN SPECIFICATION Page 32 INSTRUCTION (I) BOX INPUT ILLEGAL_OPCODE, ! INDICATES AN ILLEGAL OPCODE CONDITION, I.E. UNDEFINED OPCODES, FP OPS WHEN NO FPA, ! FPD WHEN FPD IS ILLEGAL. NO_SPECIFIERS, ! INDICATOR FROM IID LOGIC THAT OPCODE HAS NO SPECIFIERS ! NOTE: VALID ONLY IF SPEC_CTR EQ 0 BRANCH_BYTE, ! INDICATOR FROM IID LOGIC THAT OPCODE IS A BRANCH WITH ! BYTE DISPLACEMENT...AGAIN, ONLY VALID IF SPEC_CTR EQ 0 BRANCH_WORD, ! SAME AS ABOVE, FOR BRANCHES W/ WORD DISPLACEMENT SECOND_IID_EXPECTED, ! FLAG UPDATED ON EVERY DISPATCH, SET IF DISPATCH ADDRESS IS XFD.., CLEARED OTHERWISE ! VALID ONLY IF SPEC_CTR EQ 0 SPEC_CTR_0, ! COUNTER HOLDING NUMBER OF SPECS FOR INSTRUCTION...AT IID, SPEC_CTR GETS SET TO VALUE ! PROVIDED BY IID LOGIC...AT EACH DISPATCH, SPEC_CTR GETS DECREMENTED. WHEN SPEC_CTR ! EQ 2, THE SPECIFIER MODE HAS TO BE CHECKED TO ENABLE OPTIMIZED DISPATCH...WHEN SPEC_CTR SPEC_CTR_GE_2, ! EQ 1, THE NEXT DISPATCH WILL BE EXECUTE...WHEN SPEC_CTR EQ 0, THE NEXT DISPATCH IS IID ! NOTE: IF AN OPTIMIZED EXE DISPATCH IS TAKEN, SPEC_CTR MUST GET CLEARED. FPD_DISPATCH, ! SAME AS FPD_BIT BYTES_REQUIRED<1:0>, ! OUTPUT OF SOME LOGIC THAT LOOKS AT: SPECIFIER MODE, ACCESS TYPE, SPEC_CTR EQ 0, REGISTER EQ PC, ! OUTPUTS NUMBER OF BYTES REQUIRED FOR A SPECIFIER DISPATCH UNDER THOSE CONDITIONS HAVE0, HAVEATL1, HAVEATL2, HAVEATL3, HAVEATL4, HAVEATL5, HAVEATL6, I_PSL_TP, ! TRACE PENDING BIT...VALID ONLY WHEN SPEC_CTR EQ 0 INT_PENDING, ! INTERRUPT PENDING BIT...SAME AS ABOVE VAX_TRAP_REQUEST, ! VAX TRAP REQUEST PENDING BIT...SAME AS ABOVE INDEX_EXPECTED, ! FLAG SET ON ANY DISPATCH WHICH SENDS THE GSD.INDEX ADDRESS...INDICATES THAT NEXT DECNEXT ! WILL BE A DECNEXT.INDEX PFQ_HALTED, SPEC_CTR_1; OUTPUT I_S%DISP_ADR_CHOICE<10:0> /DEFAULT=00000000000, ! CHOOSES ADDRESS IID_THINGS_OK, I_S%EN_IDR_EFF_DL_H<1:0>, I_S%EN_NEW_DELTA_PC_H<5:0>, I_S%EN_ADD_TO_IB_PTR_H /DEFAULT=0, ! I_S%EN_RESET_SPEC_CTR_H /DEFAULT=0, I_S%EN_DECR_SPEC_CTR_H /DEFAULT=0, I_S%EN_LOADING_IDR_H /DEFAULT=0; CONSTANT BYTES_REQUIRED (NEED1 = 00, NEED2 = 01, NEED3 = 10, NEED5 = 11); CONSTANT I_S%DISP_ADR_CHOICE ( CVAX CPU CHIP DESIGN SPECIFICATION Page 33 INSTRUCTION (I) BOX IB_HLT = 00000000001, VTR_ADR = 10000000000, INT_ADR = 01000000000, TBIT_ADR = 00100000000, XFD_ADR = 00000000000, FPD_ADR = 00010000000, ILLEGAL_OPC = 00001000000, USE_EXE_ADR = 00000100000, USE_IID_EXE_ADR = 00000010000, USE_SPEC_ADR = 00000001000, USE_SPEC_ADR_NDX = 00000000100, IB_DRY = 00000000010); CONSTANT I_S%EN_IDR_EFF_DL_H (IDR_BYTE = 00, IDR_WORD = 01, IDR_LONG = 10); CONSTANT I_S%EN_NEW_DELTA_PC_H (DPC_0 = 000000, DPC_1 = 001000, DPC_2 = 001100, DPC_3 = 001110, DPC_4 = 001111, DPC_5 = 100111, DPC_6 = 110011); BEGIN ! PROCEED THROUGH VARIOUS VALUES OF SPEC_CTR, GROUPING STATEMENTS FOR EACH VALUE TOGETHER ! FOR SPEC_COUNTER = 0 ! THIS MEANS THAT THE IBOX IS READY TO DO AN IID DISPATCH...VALID CASES ARE: ! ! VAX TRAP REQUEST SET !#0 SPEC_CTR_0,VAX_TRAP_REQUEST,^SECOND_IID_EXPECTED / VTR_ADR; !#1 SPEC_CTR_0,^VAX_TRAP_REQUEST,INT_PENDING,^SECOND_IID_EXPECTED /INT_ADR; !#2 ! 2/3/86 took ^FPD_DISPATCH out of term # 2 below SPEC_CTR_0,^VAX_TRAP_REQUEST,^INT_PENDING,^I_PSL_TP,^HAVE0,^ILLEGAL_OPCODE / IID_THINGS_OK; !#3 SPEC_CTR_0,^VAX_TRAP_REQUEST,^INT_PENDING,I_PSL_TP,^SECOND_IID_EXPECTED / TBIT_ADR; !#4 SPEC_CTR_0,HAVE0,SECOND_IID_EXPECTED,PFQ_HALTED / IB_HLT; !#5 SPEC_CTR_0,^VAX_TRAP_REQUEST,^INT_PENDING,^I_PSL_TP,^HAVE0,ILLEGAL_OPCODE / ILLEGAL_OPC; !#6 SPEC_CTR_0,^VAX_TRAP_REQUEST,^INT_PENDING,^I_PSL_TP,^HAVE0,FPD_DISPATCH,^ILLEGAL_OPCODE / FPD_ADR,I_S%EN_ADD_TO_IB_PTR_H,DPC_1; !#7 SPEC_CTR_0,^VAX_TRAP_REQUEST,^INT_PENDING,^I_PSL_TP,HAVEATL2,^FPD_DISPATCH,^ILLEGAL_OPCODE,NO_SPECIFIERS,BRANCH_BYTE / USE_IID_EXE_ADR,IDR_BYTE,I_S%EN_ADD_TO_IB_PTR_H,DPC_2,I_S%EN_LOADING_IDR_H; !#8 CVAX CPU CHIP DESIGN SPECIFICATION Page 34 INSTRUCTION (I) BOX SPEC_CTR_0,^HAVEATL2,^FPD_DISPATCH,^ILLEGAL_OPCODE,NO_SPECIFIERS,BRANCH_BYTE,SECOND_IID_EXPECTED,PFQ_HALTED / IB_HLT; !#9 SPEC_CTR_0,^VAX_TRAP_REQUEST,^INT_PENDING,^I_PSL_TP,HAVEATL3,^FPD_DISPATCH,^ILLEGAL_OPCODE,NO_SPECIFIERS,BRANCH_WORD / USE_IID_EXE_ADR,IDR_WORD,I_S%EN_ADD_TO_IB_PTR_H,DPC_3,I_S%EN_LOADING_IDR_H; !#10 SPEC_CTR_0,^HAVEATL3,^FPD_DISPATCH,^ILLEGAL_OPCODE,NO_SPECIFIERS,BRANCH_WORD,SECOND_IID_EXPECTED,PFQ_HALTED / IB_HLT; !#11 SPEC_CTR_0,^VAX_TRAP_REQUEST,^INT_PENDING,^I_PSL_TP,^HAVE0,^FPD_DISPATCH,^ILLEGAL_OPCODE,NO_SPECIFIERS,^BRANCH_BYTE,^BRANCH_WORD / USE_IID_EXE_ADR,I_S%EN_ADD_TO_IB_PTR_H,DPC_1; !#12 SPEC_CTR_0,^VAX_TRAP_REQUEST,^INT_PENDING,^I_PSL_TP,^FPD_DISPATCH,^ILLEGAL_OPCODE,^NO_SPECIFIERS,NEED1,HAVEATL2 / USE_SPEC_ADR, I_S%EN_ADD_TO_IB_PTR_H,DPC_2,I_S%EN_RESET_SPEC_CTR_H; !#13 SPEC_CTR_0,^ILLEGAL_OPCODE,^FPD_DISPATCH,^NO_SPECIFIERS,NEED1,^HAVEATL2,SECOND_IID_EXPECTED,PFQ_HALTED / IB_HLT; !#14 SPEC_CTR_0,^VAX_TRAP_REQUEST,^INT_PENDING,^I_PSL_TP,^FPD_DISPATCH,^ILLEGAL_OPCODE,^NO_SPECIFIERS,NEED2,HAVEATL3 / USE_SPEC_ADR, I_S%EN_ADD_TO_IB_PTR_H,DPC_3,I_S%EN_RESET_SPEC_CTR_H,IDR_BYTE,I_S%EN_LOADING_IDR_H; !#15 SPEC_CTR_0,^ILLEGAL_OPCODE,^NO_SPECIFIERS,^FPD_DISPATCH,NEED2,^HAVEATL3,SECOND_IID_EXPECTED,PFQ_HALTED /IB_HLT; !#16 SPEC_CTR_0,^VAX_TRAP_REQUEST,^INT_PENDING,^I_PSL_TP,^FPD_DISPATCH,^ILLEGAL_OPCODE,^NO_SPECIFIERS,NEED3,HAVEATL4 / USE_SPEC_ADR, I_S%EN_ADD_TO_IB_PTR_H,DPC_4,I_S%EN_RESET_SPEC_CTR_H,IDR_WORD,I_S%EN_LOADING_IDR_H; !#17 SPEC_CTR_0,^ILLEGAL_OPCODE,^NO_SPECIFIERS,NEED3,^HAVEATL4,^FPD_DISPATCH,SECOND_IID_EXPECTED,PFQ_HALTED / IB_HLT; !#18 SPEC_CTR_0,^VAX_TRAP_REQUEST,^INT_PENDING,^I_PSL_TP,^FPD_DISPATCH,^ILLEGAL_OPCODE,^NO_SPECIFIERS,NEED5,HAVEATL6 / USE_SPEC_ADR, I_S%EN_RESET_SPEC_CTR_H,I_S%EN_ADD_TO_IB_PTR_H,DPC_6,IDR_LONG,I_S%EN_LOADING_IDR_H; !#19 SPEC_CTR_0,^ILLEGAL_OPCODE,^NO_SPECIFIERS,NEED5,^HAVEATL6,^FPD_DISPATCH,SECOND_IID_EXPECTED,PFQ_HALTED /IB_HLT; ! ! FOR SPEC_COUNTER = 1 ! IN THIS CASE, THE DISPATCH IS TO EXECUTION FLOWS ONLY...NONE OF THIS SPECIFIER JUNK. !#20 SPEC_CTR_1 / USE_EXE_ADR,I_S%EN_DECR_SPEC_CTR_H; ! ! FOR SPEC_COUNTER >= 2 ! IN THIS CASE,THE DISPATCH WILL BE TO A SPECIFER FLOW IF THERE IS ENOUGH DATA...IF NOT, THE DISPATCH WILL BE TO EITHER: ! IB_HLT, IF THE DISPATCH IS A NORMAL DECNEXT AND THE PFQ IS DRY AND HALTED ! IB_DRY, IF THE DISPATCH IS A NORMAL DECNEXT AND THE PFQ IS DRY BUT NOT HALTED ! REMEMBER TO DECREMENT SPEC COUNTER,LOAD THE SPEC_RN REGISTER,UPDATE AT AND DL, SET IDR_EFF_DL, NEW_DELTA_PC, ENABLE IDR LOAD, ! ENABLE ADDING TO IB_PTR, SET IDR_LOAD_INDEX !#21 SPEC_CTR_GE_2,^INDEX_EXPECTED,NEED1,HAVEATL1 / USE_SPEC_ADR,I_S%EN_ADD_TO_IB_PTR_H,DPC_1,I_S%EN_DECR_SPEC_CTR_H; !#22 SPEC_CTR_GE_2,NEED1,^HAVEATL1,^PFQ_HALTED / IB_DRY; !#23 SPEC_CTR_GE_2,NEED1,^HAVEATL1,PFQ_HALTED / IB_HLT; !#24 SPEC_CTR_GE_2,INDEX_EXPECTED,NEED1,HAVEATL1 / USE_SPEC_ADR_NDX,I_S%EN_ADD_TO_IB_PTR_H,DPC_1,I_S%EN_DECR_SPEC_CTR_H; !#25 SPEC_CTR_GE_2,^INDEX_EXPECTED,NEED2,HAVEATL2 / USE_SPEC_ADR,I_S%EN_ADD_TO_IB_PTR_H,DPC_2,I_S%EN_DECR_SPEC_CTR_H, I_S%EN_LOADING_IDR_H,IDR_BYTE; CVAX CPU CHIP DESIGN SPECIFICATION Page 35 INSTRUCTION (I) BOX !#26 SPEC_CTR_GE_2,NEED2,^HAVEATL2,^PFQ_HALTED / IB_DRY; !#27 SPEC_CTR_GE_2,NEED2,^HAVEATL2,PFQ_HALTED / IB_HLT; !#28 SPEC_CTR_GE_2,INDEX_EXPECTED,NEED2,HAVEATL2 / USE_SPEC_ADR_NDX,I_S%EN_ADD_TO_IB_PTR_H,DPC_2,I_S%EN_LOADING_IDR_H,IDR_BYTE, I_S%EN_DECR_SPEC_CTR_H; !#30 SPEC_CTR_GE_2,^INDEX_EXPECTED,NEED3,HAVEATL3 / USE_SPEC_ADR,I_S%EN_ADD_TO_IB_PTR_H,DPC_3,I_S%EN_DECR_SPEC_CTR_H, I_S%EN_LOADING_IDR_H,IDR_WORD; !#31 SPEC_CTR_GE_2,NEED3,^HAVEATL3,^PFQ_HALTED / IB_DRY; !#32 SPEC_CTR_GE_2,NEED3,^HAVEATL3,PFQ_HALTED / IB_HLT; !#33 SPEC_CTR_GE_2,INDEX_EXPECTED,NEED3,HAVEATL3 / USE_SPEC_ADR_NDX,I_S%EN_ADD_TO_IB_PTR_H,DPC_3, I_S%EN_LOADING_IDR_H,IDR_WORD,I_S%EN_DECR_SPEC_CTR_H; !#34 SPEC_CTR_GE_2,^INDEX_EXPECTED,NEED5,HAVEATL5 / USE_SPEC_ADR,I_S%EN_ADD_TO_IB_PTR_H,DPC_5,I_S%EN_DECR_SPEC_CTR_H, I_S%EN_LOADING_IDR_H,IDR_LONG; !#35 SPEC_CTR_GE_2,NEED5,^HAVEATL5,^PFQ_HALTED / IB_DRY; !#36 SPEC_CTR_GE_2,NEED5,^HAVEATL5,PFQ_HALTED / IB_HLT; !#37 SPEC_CTR_GE_2,INDEX_EXPECTED,NEED5,HAVEATL5 / USE_SPEC_ADR_NDX,I_S%EN_ADD_TO_IB_PTR_H,DPC_5, I_S%EN_LOADING_IDR_H,IDR_LONG,I_S%EN_DECR_SPEC_CTR_H; END; 2.10.5.2 I_DISPATCH_PLA Binary File... - i 23 o 18 p 37 x x x x x x 1 x 1 1 x x x x x 1 x x x x 1 x x 0 0 1 0 0 0 1 0 1 0 0 1 1 1 1 0 1 1 x x x x x x 1 x 1 1 x x x x x 0 x x x x x 1 x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x 1 x 1 1 x x x x x 0 x x x x x 0 x 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x 1 x 1 1 x x x x x 1 x x x x 0 x x 0 1 0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 1 x x x x x x 1 x 1 0 x x x 1 x x x x x x 1 x x 0 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 x x x x x x 1 x 1 0 x x x 0 x x x x x x x 1 x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x 1 x 1 0 x x x 0 x x x x x x x 0 x 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x 1 x 1 0 x x x 1 x x x x x x 0 x x 0 1 0 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 x x x x x x 1 x 0 1 x x 1 x x x x x x x 1 x x 0 0 1 0 0 0 0 0 0 0 1 1 0 0 1 0 1 1 x x x x x x 1 x 0 1 x x 0 x x x x x x x x 1 x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x 1 x 0 1 x x 0 x x x x x x x x 0 x 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x 1 x 0 1 x x 1 x x x x x x x 0 x x 0 1 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 1 x x x x x x 1 x 0 0 x 1 x x x x x x x x 1 x x 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 x x x x x x 1 x 0 0 x 0 x x x x x x x x x 1 x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 CVAX CPU CHIP DESIGN SPECIFICATION Page 36 INSTRUCTION (I) BOX x x x x x x 1 x 0 0 x 0 x x x x x x x x x 0 x 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x 1 x 0 0 x 1 x x x x x x x x 0 x x 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 x x x x x x x x x x x x x x x x x x x x x x 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 -->use_exe output 0 0 x x 1 1 x 0 1 1 x x x x x x 0 x x x x 1 x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 1 x 0 1 1 x x x x x x 1 0 0 0 x x x 0 1 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 x x 1 1 x 0 1 0 x x x x 0 x x x x x x 1 x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 1 x 0 1 0 x x x x 1 x x 0 0 0 x x x 0 1 0 0 0 0 0 1 0 0 1 1 1 1 1 1 0 1 0 0 x x 1 1 x 0 0 1 x x x 0 x x x x x x x 1 x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 1 x 0 0 1 x x x 1 x x x 0 0 0 x x x 0 1 0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 1 0 0 x x 1 1 x 0 0 0 x x 0 x x x x x x x x 1 x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 1 x 0 0 0 x x 1 x x x x 0 0 0 x x x 0 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 x 1 x 0 x x 0 x x x x x x 0 0 0 x x x 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 x 1 1 1 x 0 x x x x x 0 x x x x x x x 1 x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 x 1 x 1 x 0 x x x x x 1 x x x 0 0 0 x x x 1 0 0 0 0 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 x 1 1 x 0 x x x x 0 x x x x x x x x 1 x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 x x 1 x 0 x x x x 1 x x x x 0 0 0 x x x 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 x x x x 1 x 1 x x 0 x x x x x x 0 0 0 x x x 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 --> use_fpd output 1 x x x x 1 x x x x 0 x x x x x x 0 0 0 x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --> use_illeg_opc output x x x x 1 1 x x x x 1 x x x x x x x x x x 1 x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x 0 1 x x x x x x x x x x x 1 0 0 x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --> use_tbit output 0 x x x x 1 x x x x 0 x x x x x x 0 0 0 x x x 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 x x x x 0 1 x x x x x x x x x x x x 1 0 x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --> use_int output x x x x 0 1 x x x x x x x x x x x x x 1 x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --> use_vtr output end 2.10.6 I_FPA_BUFFERS (IFB) - The fpa buffer logic sends opcode class information to the FPA logic. The FPA present bit also lives here, as does the logic used to generate the G_S%BRDCST_OK_H signal. 2.10.7 I_IID_LOGIC (IIL) - The IID logic examines the next two bytes of instruction data. Part of this logic generates an execution address offset for opcodes with no specifiers. Another part of the logic generates a specifier dispatch address offset for specifier parsing. The IID logic examines the opcode to see if it is illegal. Furthermore, it determines if the opcode is a simple branch or jump, the number of bytes needed for the next specifier dispatch, and whether or not the opcode is FD, the first part of a 2-byte opcode. 2.10.8 I_IPLA (IPL) - This logic forms the instruction PLA in the I Box. It examines the opcode to determine access types, data lengths, number of specifiers, floating point flags, and partial execution addresses for the current instruction. The programming of the IPLA is contained in the following four schematics: CVAX CPU CHIP DESIGN SPECIFICATION Page 37 INSTRUCTION (I) BOX o I_IPLA_BANK_0 IB0 o I_IPLA_BANK_1 IB1 o I_IPLA_BANK_2 IB2 o I_IPLA_BANK_3 IB3 2.10.9 I_MIB_DECODE (IMD) - The MIB Decoder decodes part of the microinstruction, specifically the BCS field and MISC field. In addition, the logic which controls I Box stalls is contained in this schematic. The global IID signal is generated here, as is the I Box WRITE clock, IC%LOADSTATEH. 2.10.10 I_MISC_STATE (IMS) - The misc state logic contains the I Box PSL bits, the XFD bit, and some additional miscellaneous logic. 2.10.11 I_OP_MUX (IOM) - The operation multiplexor generates control signals for modifying some I Box state based on the occurence of either DEC.NEXT or CASE.LD.ID BCS functions. The delta_pc value for ID register loading is generated here, as are the status bits used on the microtest bus during a CASE.LD.ID . 2.10.12 I_OTHER_MIB_DECODER (IM2) - This mib decoder decodes the SPECIAL functions and the MXPS functions for the I Box. 2.10.13 I_PFQ_CONTROL (IQC) - The prefetch queue controller uses calculated delta_pc values as well as MIB decoder outputs to determine the correct way to update the prefetch queue registers. It also generates the global delta_pc value and the state bits which indicate the validity of longwords in the prefetch queue. Another part of this logic creates a code which informs the dispatch PLA of the number of bytes available for the next operation, while yet another part controls the generation of IB fill requests. CVAX CPU CHIP DESIGN SPECIFICATION Page 38 INSTRUCTION (I) BOX 2.10.14 I_SECOND_IPLA (I2P) - This PLA augments the IPLA (see I_IPLA) for determining access types and data lengths for some specifiers. In particular, this PLA contains the codes for access types and data lengths for the forth through sixth specifiers of an opcode. 2.10.15 I_SPEC_COUNTER (ISC) - The specifier counter logic keeps track of the number of specifiers already parsed during instruction decode. The two primary registers in this schematic contain the current spec counter and the number of specifiers for the instruction. This schematic also generates two I Box state bits for use in INDEX specifier decoding. Other logic on this schematic generates a difference code from the spec counter and the number of specifiers. This difference code is used to generate an index for selecting the correct AT and DL code in the I_AT_DL_REG schematic. The code produced is also used to generate the global SN register index for the E Box. 2.10.16 I_SPEC_RN_REG (ISR) - The spec.rn register holds the current specifier. The OLD.RN register is here, as is the RMODE detection logic. Another part of this schematic holds the second.iid bit. 2.10.17 I_SPUR_UTEST_DRIVE (ISU) - This logic drives the WSPUR and microtest bus when the spirit moves it. CVAX CPU CHIP DESIGN SPECIFICATION Page 39 INSTRUCTION (I) BOX 2.11 Tables 2.11.1 Dispatch Types, STALL And UTrap Behavior - The following table shows, for all I Box requests, the behavior of the Microaddress Generator: REQUEST(SPEC.CTR.VAL) PFQ Status DISPATCH -----------------------+---------------+---------------+ DEC.NEXT (0) OK NORMAL DRY IE.IID.STALL DEC.NEXT (<>0) OK NORMAL DRY, NOT HLT DEC.NEXT.STALL DRY, HALTED DEC.NEXT.HALTED LOAD IDR OK CASE ON ID LOAD STATUS DRY, NOT HLT CASE ON ID LOAD STATUS DRY, HALTED CASE ON ID LOAD STATUS 2.11.2 NOTE ON UPDATING I BOX STATE - There are two conditions under which the I Box must freeze most dispatch and state change operations. These conditions arise as a result of events that interrupt the normal flow of microcode, namely microtraps and STALLs. The I Box must retire instruction data used by an I Box dispatch before the microinstruction containing the dispatch can be stalled or completed. In the event of a STALL or microtrap, however, the microinstruction may be retried. In the event of a retry, the I Box must ignore the reissued microinstruction, since the intended data for the microinstruction has already been discarded from the instruction stream. The INOP mechanism in the I Box is used to insure that reissued microinstructions are ignored correctly. There are two cases in which a reissued microinstruction must be ignored by the I Box. The first case occurs when a microtrap is signalled in the same cycle that a DEC.NEXT microinstruction is executed. In this case, the I Box must ignore all DEC.NEXT operations until after a DEC.NEXT is received and STALL is not asserted. In this way, the I Box will resume operation at the correct point in the microcode flow. The second case occurs when STALL is asserted. In this case, almost all I Box operations must be suspended until STALL is deasserted. Both cases are handled by the INOP logic in the I Box. The INOP signal inhibits: o all actions associated with DEC.NEXT or CASE.LD.ID operations (except drive of case status for the CASE.LD.ID) CVAX CPU CHIP DESIGN SPECIFICATION Page 40 INSTRUCTION (I) BOX o all I Box MISC field operations except DISABLE.PFQ o update of the delta PC value sent to the E Box o update of: SPEC.RN, OPCODE, VAX.TRAP.REQ, DL, AT, PSL BITS, IMAB, FD BIT, 2ND IID FLAG, INDEX MODE FLAG, SPEC COUNTER, WSN, AT_EQ_MOD, IID_LD, COPY_TRACE. The INOP signal does NOT inhibit: o MISC operations DISABLE.PFQ,DL.BYTE,DL.WORD,DL.LONG,DL.QUAD, and LOAD.OLD.RN o CASE operations (excluding CASE.LD.ID) o FLUSH of the I Box by LOAD.V&PC o FLUSH of the I Box by RESET In summary, o INOP is set by a microtrap occuring in the same cycle as a DEC.NEXT . In this case, it is cleared by RESET, LOAD.V&PC, or a DEC.NEXT while STALL is not asserted. o INOP is set by assertion of STALL. In this case, it is cleared by deassertion of STALL, assertion of RESET, or LOAD.V&PC. CVAX CPU CHIP DESIGN SPECIFICATION Page 41 INSTRUCTION (I) BOX 2.11.3 CVAX IPLA Assignments - KEY: OPCODE is listed in the first two to four characters AN "O" between the opcode and mnemonic indicates an opcode which is optimized with the help of CFPA AN "F" between the opcode and mnemonic indicates an opcode that can only be executed with the CFPA coprocessor MNEMONIC is next AT / DL fields for all operands follow the mnemonic NOTE: Access Types of "w" are treated as "v". START AUTOMATIC PARSING HERE 1 94 CLRB wb wb CLRX 588 1 D4 CLRL wl wl CLRX 588 1 7C CLRQ wq wq CLRX 588 1 B4 CLRW ww ww CLRX 588 1 97 DECB mb mb DECX 584 1 D7 DECL ml ml DECX 584 1 B7 DECW mw mw DECX 584 1 96 INCB mb mb INCX 580 1 D6 INCL ml ml INCX 580 1 B6 INCW mw mw INCX 580 1 DD PUSHL rl rl PUSHX 444 1 95 TSTB rb rb TSTX 400 1 D5 TSTL rl rl TSTX 400 1 B5 TSTW rw rw TSTX 400 1 9F PUSHAB ab ab PUSHX 444 1 DF PUSHAL al al PUSHX 444 1 7F PUSHAQ aq aq PUSHX 444 1 3F PUSHAW aw aw PUSHX 444 1 E9 BLBC rl rl BLBX 500 1 E8 BLBS rl rl BLBX 500 1 17 JMP ab ab JMP 480 1 16 JSB ab ab JSB 484 1 F4 SOBGEQ ml ml SOBX 504 1 F5 SOBGTR ml ml SOBX 504 1 B9 BICPSW rw rw BISPSW 520 1 B8 BISPSW rw rw BISPSW 520 1 DC MOVPSL wl wl MOVPSL 58C 1 BA POPR rw rw POPR 4A0 1 BB PUSHR rw rw PUSHR 4A4 1 BD CHME rw rw CHME 4BC 1 BC CHMK rw rw CHMK 4B8 1 BE CHMS rw rw CHMS 4C0 1 BF CHMU rw rw CHMU 4C4 1 73 F TSTD rd rd TSTDG 518 1 53 F TSTF rf rf TSTF 528 1 53FD F TSTG rg rg TSTDG 518 2 58 ADAWI rw aw ADAWI 448 ;2 ADAWI.RMODE 44A 2 80 ADDB2 rb mb ADDX2 40C ;2 ADDX2.RMODE 40E 2 C0 ADDL2 rl ml ADDX2 40C CVAX CPU CHIP DESIGN SPECIFICATION Page 42 INSTRUCTION (I) BOX ;2 ADDX2.RMODE 40E 2 A0 ADDW2 rw mw ADDX2 40C ;2 ADDX2.RMODE 40E 2 D8 ADWC rl ml ADWC 420 ;2 ADWC.RMODE 422 2 8A BICB2 rb mb BICX2 418 ;2 BICX2.RMODE 41A 2 CA BICL2 rl ml BICX2 418 ;2 BICX2.RMODE 41A 2 AA BICW2 rw mw BICX2 418 ;2 BICX2.RMODE 41A 2 88 BISB2 rb mb BISX2 414 ;2 BISX2.RMODE 416 2 C8 BISL2 rl ml BISX2 414 ;2 BISX2.RMODE 416 2 A8 BISW2 rw mw BISX2 414 ;2 BISX2.RMODE 416 2 93 BITB rb rb BITX 408 ;2 BITX.RMODE 40A 2 D3 BITL rl rl BITX 408 ;2 BITX.RMODE 40A 2 B3 BITW rw rw BITX 408 ;2 BITX.RMODE 40A 2 91 CMPB rb rb CMPX 404 ;2 CMPX.RMODE 406 2 D1 CMPL rl rl CMPX 404 ;2 CMPX.RMODE 406 2 B1 CMPW rw rw CMPX 404 ;2 CMPX.RMODE 406 2 98 CVTBL rb wl CVTBX 44C ;2 CVTBX.RMODE 44E 2 99 CVTBW rb ww CVTBX 44C ;2 CVTBX.RMODE 44E 2 F6 CVTLB rl wb CVTXY 598 ;2 CVTXY.RMODE 59A 2 F7 CVTLW rl ww CVTXY 598 ;2 CVTXY.RMODE 59A 2 33 CVTWB rw wb CVTXY 598 ;2 CVTXY.RMODE 59A 2 32 CVTWL rw wl CVTWL 450 ;2 CVTWL.RMODE 452 2 86 DIVB2 rb mb DIVX2 468 ;2 DIVX2.RMODE 46A 2 C6 O DIVL2 rl ml DIVX2 468 ;2 DIVX2.RMODE 46A 2 A6 DIVW2 rw mw DIVX2 468 ;2 DIVX2.RMODE 46A 2 92 MCOMB rb wb MCOMX 428 ;2 MCOMX.RMODE 42A 2 D2 MCOML rl wl MCOMX 428 ;2 MCOMX.RMODE 42A 2 B2 MCOMW rw ww MCOMX 428 ;2 MCOMX.RMODE 42A 2 8E MNEGB rb wb MNEGX 42C CVAX CPU CHIP DESIGN SPECIFICATION Page 43 INSTRUCTION (I) BOX ;2 MNEGX.RMODE 42E 2 CE MNEGL rl wl MNEGX 42C ;2 MNEGX.RMODE 42E 2 AE MNEGW rw ww MNEGX 42C ;2 MNEGX.RMODE 42E 2 90 MOVB rb wb MOVX 59C ;2 MOVX.RMODE 59E 2 D0 MOVL rl wl MOVX 59C ;2 MOVX.RMODE 59E 2 7D MOVQ rq wq MOVX 59C ;2 MOVX.RMODE 59E 2 B0 MOVW rw ww MOVX 59C ;2 MOVX.RMODE 59E 2 9B MOVZBW rb ww MOVX 59C ;2 MOVX.RMODE 59E 2 9A MOVZBL rb wl MOVX 59C ;2 MOVX.RMODE 59E 2 3C MOVZWL rw wl MOVX 59C ;2 MOVX.RMODE 59E 2 84 MULB2 rb mb MULX2 510 ;2 MULX2.RMODE 512 2 C4 O MULL2 rl ml MULX2 510 ;2 MULX2.RMODE 512 2 A4 MULW2 rw mw MULX2 510 ;2 MULX2.RMODE 512 2 D9 SBWC rl ml SBWC 424 ;2 SBWC.RMODE 426 2 82 SUBB2 rb mb SUBX2 410 ;2 SUBX2.RMODE 412 2 C2 SUBL2 rl ml SUBX2 410 ;2 SUBX2.RMODE 412 2 A2 SUBW2 rw mw SUBX2 410 ;2 SUBX2.RMODE 412 2 8C XORB2 rb mb XORX2 41C ;2 XORX2.RMODE 41E 2 CC XORL2 rl ml XORX2 41C ;2 XORX2.RMODE 41E 2 AC XORW2 rw mw XORX2 41C ;2 XORX2.RMODE 41E 2 9E MOVAB ab wl MOVX 59C ;2 MOVX.RMODE 59E 2 DE MOVAL al wl MOVX 59C ;2 MOVX.RMODE 59E 2 7E MOVAQ aq wl MOVX 59C ;2 MOVX.RMODE 59E 2 3E MOVAW aw wl MOVX 59C ;2 MOVX.RMODE 59E 2 F3 AOBLEQ rl ml AOBX 488 ;2 AOBX.RMODE 48A 2 F2 AOBLSS rl ml AOBX 488 ;2 AOBX.RMODE 48A 2 E1 BBC rl vb BBX 490 ;2 BBX.RMODE 492 2 E0 BBS rl vb BBX 490 CVAX CPU CHIP DESIGN SPECIFICATION Page 44 INSTRUCTION (I) BOX ;2 BBX.RMODE 492 2 E5 BBCC rl vb BBX 490 ;2 BBX.RMODE 492 2 E3 BBCS rl vb BBX 490 ;2 BBX.RMODE 492 2 E4 BBSC rl vb BBX 490 ;2 BBX.RMODE 492 2 E2 BBSS rl vb BBX 490 ;2 BBX.RMODE 492 2 E7 BBCCI rl vb BBX 490 ;2 BBX.RMODE 492 2 E6 BBSSI rl vb BBX 490 ;2 BBX.RMODE 492 2 FA CALLG ab ab CALLX 498 ;2 CALLX.RMODE 49A 2 FB CALLS rl ab CALLX 498 ;2 CALLX.RMODE 49A 2 5C INSQHI ab aq INSQXI 4CC ;2 INSQXI.RMODE 4CE 2 5D INSQTI ab aq INSQXI 4CC ;2 INSQXI.RMODE 4CE 2 0E INSQUE ab ab INSQUE 4A8 ;2 INSQUE.RMODE 4AA 2 5E REMQHI aq wl REMQXI 4F8 ;2 REMQXI.RMODE 4FA 2 5F REMQTI aq wl REMQXI 4F8 ;2 REMQXI.RMODE 4FA 2 0F REMQUE ab wl REMQUE 4AC ;2 REMQUE.RMODE 4AE 2 DB MFPR rl wl MFPR 4B4 ;2 MFPR.RMODE 4B6 2 DA MTPR rl rl MTPR 4B0 ;2 MTPR.RMODE 4B2 2 60 F ADDD2 rd md ADDDG2 4D4 ;2 ADDDG2.RMODE 4D6 2 40 F ADDF2 rf mf ADDF2 4D0 ;2 ADDF2.RMODE 4D2 2 40FD F ADDG2 rg mg ADDDG2 4D4 ;2 ADDDG2.RMODE 4D6 2 71 F CMPD rd rd CMPDG 4DC ;2 CMPDG.RMODE 4DE 2 51 F CMPF rf rf CMPF 4D8 ;2 CMPF.RMODE 4DA 2 51FD F CMPG rg rg CMPDG 4DC ;2 CMPDG.RMODE 4DE 2 6C F CVTBD rb wd ADDDG3 464 ;2 ADDDG3.RMODE 466 2 4C F CVTBF rb wf ADDF3 460 ;2 ADDF3.RMODE 462 2 4CFD F CVTBG rb wg ADDDG3 464 ;2 ADDDG3.RMODE 466 2 68 F CVTDB rd wb ADDF3 460 ;2 ADDF3.RMODE 462 2 76 F CVTDF rd wf ADDF3 460 CVAX CPU CHIP DESIGN SPECIFICATION Page 45 INSTRUCTION (I) BOX ;2 ADDF3.RMODE 462 2 6A