CMOS 2 CVAX CPU CHIP ENGINEERING SPECIFICATION DC580 21-24674-16 (80nsec) 21-24674-15 (60nsec) Document Rev. 1.0 Chip Rev 2.0 Mask Rev B Contact for SEG: Mike Phipps (RICKS::PHIPPS) C O M P A N Y C O N F I D E N T I A L Copyright (C) 1984, 1985, 1986, 1987, 1988, 1989 by Digital Equipment Corporation The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may occur in this document. This specification does not describe any program or product which is currently available from Digital Equipment Corporation. Nor does Digital Equipment Corporation commit to implement this specification in any product or program. Digital Equipment Corporation makes no commitment that this document accurately describes any product it might ever make. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential)Page 2 TABLE OF CONTENTS CONTENTS 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . 3 1.1 Scope . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Applicable Documents . . . . . . . . . . . . . . . 3 1.3 CVAX CPU Chip Features . . . . . . . . . . . . . . 3 1.4 Summary Of Differences . . . . . . . . . . . . . . 4 1.5 Part Number Variation Descriptions . . . . . . . . 5 2 ARCHITECTURE SUMMARY . . . . . . . . . . . . . . . . 6 2.1 Visible State . . . . . . . . . . . . . . . . . . 6 2.1.1 Virtual Address Space . . . . . . . . . . . . . 6 2.1.2 Physical Address Space . . . . . . . . . . . . . 7 2.1.3 Registers . . . . . . . . . . . . . . . . . . . 8 2.2 Data Types . . . . . . . . . . . . . . . . . . . . 9 2.3 Instruction Formats And Addressing Modes . . . . 11 2.3.1 Opcode Formats . . . . . . . . . . . . . . . . 11 2.3.2 General Register Operand Specifiers . . . . . 11 2.3.3 Branch Operand Specifiers . . . . . . . . . . 12 2.4 Instruction Set . . . . . . . . . . . . . . . . 13 2.4.1 Integer Arithmetic And Logical Instructions . 14 2.4.2 Address Instructions . . . . . . . . . . . . . 16 2.4.3 Variable Length Bit Field Instructions . . . . 16 2.4.4 Control Instructions . . . . . . . . . . . . . 17 2.4.5 Procedure Call Instructions . . . . . . . . . 18 2.4.6 Miscellaneous Instructions . . . . . . . . . . 18 2.4.7 Queue Instructions . . . . . . . . . . . . . . 19 2.4.8 Character String Instructions . . . . . . . . 19 2.4.9 Operating System Support Instructions . . . . 19 2.4.10 Floating Point Instructions . . . . . . . . . 20 2.4.11 Microcode-Assisted Emulated Instructions . . . 22 2.5 Memory Management . . . . . . . . . . . . . . . 23 2.5.1 Memory Management Control Registers . . . . . 23 2.5.2 System Space Address Translation . . . . . . . 24 2.5.3 Process Space Address Translation . . . . . . 26 2.5.3.1 P0 Region Address Translation . . . . . . . 26 2.5.3.2 P1 Region Address Translation . . . . . . . 28 2.5.4 Page Table Entry . . . . . . . . . . . . . . . 30 2.5.5 Translation Buffer . . . . . . . . . . . . . . 31 2.6 Exceptions And Interrupts . . . . . . . . . . . 32 2.6.1 Interrupts . . . . . . . . . . . . . . . . . . 32 2.6.2 Exceptions . . . . . . . . . . . . . . . . . . 33 2.6.3 System Control Block (SCB) . . . . . . . . . . 34 2.6.4 Machine Check Parameters . . . . . . . . . . . 37 2.6.4.1 Types Of Errors . . . . . . . . . . . . . . 37 2.6.4.2 Machine Check Processing . . . . . . . . . . 40 2.6.4.3 Processor Restart . . . . . . . . . . . . . 41 2.7 Process Structure . . . . . . . . . . . . . . . 43 2.7.1 Process Control Block (PCB) . . . . . . . . . 44 2.8 Processor Registers . . . . . . . . . . . . . . 46 2.8.1 Interval Clock Control And Status Register (ICCS) . . . . . . . . . . . . . . . . . . . . 47 2.8.2 Cache Disable Register (CADR) . . . . . . . . 48 2.8.3 Memory System Error Register (MSER) . . . . . 50 2.8.4 Console Saved Registers (SAVPC, SAVPSL) . . . 50 2.8.5 System Identification Register (SID) . . . . . 51 3 INTERNAL CACHE . . . . . . . . . . . . . . . . . . 52 CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential)Page 3 TABLE OF CONTENTS 3.1 Cache Allocation . . . . . . . . . . . . . . . . 53 3.2 Read Cycle Classification . . . . . . . . . . . 54 3.3 Cache Parity . . . . . . . . . . . . . . . . . 56 3.4 DAL H Parity . . . . . . . . . . . . . . . . . 56 4 INTERFACE . . . . . . . . . . . . . . . . . . . . 57 4.1 Pinouts . . . . . . . . . . . . . . . . . . . . 57 4.1.1 Summary . . . . . . . . . . . . . . . . . . . 57 4.1.2 Data And Address Bus . . . . . . . . . . . . . 58 4.1.2.1 Data And Address Lines (DAL<31:00> H) . . . 58 4.1.2.2 Cycle Status/Data Parity (CS/DP<3:0> L) . . 59 4.1.2.3 Data Parity Enable (DPE L) . . . . . . . . . 60 4.1.3 Bus Control . . . . . . . . . . . . . . . . . 61 4.1.3.1 Address Strobe (AS L) . . . . . . . . . . . 61 4.1.3.2 Data Strobe (DS L) . . . . . . . . . . . . . 61 4.1.3.3 Byte Mask (BM<3:0> L) . . . . . . . . . . . 61 4.1.3.4 Write (WR L) . . . . . . . . . . . . . . . . 62 4.1.3.5 Data Buffer Enable (DBE L) . . . . . . . . . 62 4.1.3.6 Ready (RDY L) . . . . . . . . . . . . . . . 63 4.1.3.7 Error (ERR L) . . . . . . . . . . . . . . . 63 4.1.4 System Control . . . . . . . . . . . . . . . . 64 4.1.4.1 Reset (RESET L) . . . . . . . . . . . . . . 65 4.1.4.2 Halt (HALT L) . . . . . . . . . . . . . . . 65 4.1.5 Interrupt Control . . . . . . . . . . . . . . 65 4.1.5.1 Interrupt Request (IRQ<3:0> L) . . . . . . . 65 4.1.5.2 Power Fail (PWRFL L) . . . . . . . . . . . . 65 4.1.5.3 Corrected Read Data (CRD L) . . . . . . . . 66 4.1.5.4 Interval Timer (INTTIM L) . . . . . . . . . 66 4.1.5.5 Memory Error (MEMERR L) . . . . . . . . . . 66 4.1.6 DMA Control . . . . . . . . . . . . . . . . . 66 4.1.6.1 DMA Request (DMR L) . . . . . . . . . . . . 67 4.1.6.2 DMA Grant (DMG L) . . . . . . . . . . . . . 67 4.1.7 Cache Control (CCTL L) . . . . . . . . . . . . 67 4.1.7.1 Conditional Cache Invalidate . . . . . . . . 67 4.1.7.2 Prevent Data Caching . . . . . . . . . . . . 68 4.1.8 Floating Point Unit Control . . . . . . . . . 68 4.1.8.1 CFPA Data Lines (CPDAT<5:0> H) . . . . . . . 68 4.1.8.2 CFPA Status Lines (CPSTA<1:0> H) . . . . . . 69 4.1.9 Miscellaneous . . . . . . . . . . . . . . . . 72 4.1.9.1 Power . . . . . . . . . . . . . . . . . . . 72 4.1.9.2 Ground . . . . . . . . . . . . . . . . . . . 72 4.1.9.3 Clock In (CLKA,CLKB) . . . . . . . . . . . . 72 4.1.9.4 Clear Write Buffer (CWB L) . . . . . . . . . 72 4.1.9.5 Test (TEST H) . . . . . . . . . . . . . . . 73 4.2 Bus Cycle Descriptions . . . . . . . . . . . . . 73 4.2.1 Idle Cycle . . . . . . . . . . . . . . . . . . 74 4.2.2 Single Transfer CPU Read Cycle . . . . . . . . 74 4.2.3 Multiple Transfer CPU Read Cycle . . . . . . . 75 4.2.4 CPU Write Cycle . . . . . . . . . . . . . . . 77 4.2.5 External Processor Register Read Cycle . . . . 78 4.2.6 External Processor Register Write Cycle . . . 79 4.2.7 Interrupt Acknowledge Cycle . . . . . . . . . 80 4.2.8 DMA Grant Cycle . . . . . . . . . . . . . . . 80 4.2.9 Cache Invalidate Cycles . . . . . . . . . . . 81 4.3 Memory Access Protocol . . . . . . . . . . . . . 81 4.3.1 I-stream Prefetching . . . . . . . . . . . . . 83 4.4 CFPA Protocols . . . . . . . . . . . . . . . . . 83 CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential)Page 4 TABLE OF CONTENTS 4.4.1 Passing Opcode Information To The CFPA . . . . 83 4.4.2 Passing Operands To The CFPA . . . . . . . . . 84 4.4.3 Passing Results Back From The CFPA . . . . . . 84 4.4.4 CFPA Present Indication . . . . . . . . . . . 86 4.4.5 CFPA Forced Termination . . . . . . . . . . . 86 4.4.6 CFPA Interface Overhead . . . . . . . . . . . 87 4.4.6.1 Opcode Transfer . . . . . . . . . . . . . . 87 4.4.6.2 Passing Operands To CFPA . . . . . . . . . . 88 4.4.6.3 Passing Results Back From CFPA . . . . . . . 89 4.5 Test Logic . . . . . . . . . . . . . . . . . . . 90 4.5.1 Observability Logic . . . . . . . . . . . . . 90 4.5.2 Control Logic . . . . . . . . . . . . . . . . 91 4.5.3 Normal State . . . . . . . . . . . . . . . . . 91 4.5.4 Test State . . . . . . . . . . . . . . . . . . 91 4.5.4.1 Internal MAB . . . . . . . . . . . . . . . . 91 4.5.4.2 External MAB . . . . . . . . . . . . . . . . 92 4.5.4.3 Force Broadcast . . . . . . . . . . . . . . 92 4.5.5 Test Registers . . . . . . . . . . . . . . . . 92 4.5.6 Main Reducer . . . . . . . . . . . . . . . . . 92 4.5.7 Test Control Pins Allocation . . . . . . . . . 93 5 DC CHARACTERISTICS . . . . . . . . . . . . . . . . 94 5.1 Electrostatic Discharge . . . . . . . . . . . . 94 5.2 Absolute Maximum Ratings . . . . . . . . . . . . 94 5.3 Electrical Characteristics . . . . . . . . . . . 94 5.4 Signal Summary . . . . . . . . . . . . . . . . . 96 6 AC CHARACTERISTICS . . . . . . . . . . . . . . . . 99 6.1 80nS Input Requirements (21-24674-16) . . . . . 99 6.2 80nS Output Responses (21-24674-16) . . . . . . 101 6.3 60nS Input Requirements (21-24674-15) . . . . . 103 6.4 60nS Output Responses (21-24674-15) . . . . . . 105 7 TIMING DIAGRAMS . . . . . . . . . . . . . . . . . 107 7.1 Clock Timing Requirements . . . . . . . . . . . 107 7.2 Initialization . . . . . . . . . . . . . . . . . 108 7.3 CWB L And TEST L Timing . . . . . . . . . . . . 109 7.4 External Interrupt Timing . . . . . . . . . . . 110 7.5 External DMA Timing . . . . . . . . . . . . . . 111 7.6 Quadword Cache Invalidate Cycle . . . . . . . . 112 7.7 Octaword Cache Invalidate Cycle . . . . . . . . 113 7.8 Single Transfer CPU Read Cycle, Interrupt Acknowledge Cycle . . . . . . . . . . . . . . . 114 7.9 Multiple Transfer CPU Read Cycle . . . . . . . . 117 7.10 CPU Write Cycle . . . . . . . . . . . . . . . . 120 7.11 CFPA Interface Timing . . . . . . . . . . . . . 123 7.11.1 Opcode Transfers . . . . . . . . . . . . . . . 123 7.11.2 Single Precision CVAX CPU To CFPA Transfer . . 124 7.11.3 Double Precision CVAX CPU To CFPA Transfer . . 125 7.11.4 Single Precision CFPA To CVAX CPU Transfers . 126 7.11.5 Double Precision CFPA To CVAX CPU Transfers . 128 8 CHIP INTERCONNECT DIAGRAM . . . . . . . . . . . . 130 9 DIFFERENCES BETWEEN CVAX DC341/DC580 AND MICROVAX DC333 . . . . . . . . . . . . . . . . . . . . . . 131 9.1 SOFTWARE DIFFERENCES . . . . . . . . . . . . . . 131 9.2 HARDWARE DIFFERENCES . . . . . . . . . . . . . . 132 10 PACKAGE PINOUT . . . . . . . . . . . . . . . . . . 135 11 BONDING PINOUT . . . . . . . . . . . . . . . . . . 136 12 CVAX INSTRUCTION TIMING . . . . . . . . . . . . . 137 CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential)Page 5 TABLE OF CONTENTS 12.1 Specifier Timing . . . . . . . . . . . . . . . . 138 12.1.1 Specifier Timing (Not The Last Specifier) . . 138 12.1.2 Specifier Timing (Last Specifier) . . . . . . 139 12.2 Execute, Fetch Timing . . . . . . . . . . . . . 141 12.2.1 Integer Arithmetic And Logical Instructions . 141 12.2.2 Address Instructions . . . . . . . . . . . . . 144 12.2.3 Variable Length Bit Field Instructions . . . . 145 12.2.4 Control Instructions . . . . . . . . . . . . . 145 12.2.5 Procedure Call Instructions . . . . . . . . . 147 12.2.6 Miscellaneous Instructions . . . . . . . . . . 147 12.2.7 Queue Instructions . . . . . . . . . . . . . . 148 12.2.8 Character String Instructions . . . . . . . . 148 12.2.9 Operating System Support Instructions . . . . 149 12.2.10 Floating Point Instructions . . . . . . . . . 149 12.2.11 Microcode-Assisted Emulated Instructions . . . 151 12.3 Other Timings . . . . . . . . . . . . . . . . . 153 12.4 Examples . . . . . . . . . . . . . . . . . . . . 154 CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 6 REVISION HISTORY REVISION HISTORY ---------------- REV DATE REASON --- ---- ------ 1.0 13-Jan-88 Creation of the DC580 Engineering Specification. This Specification reflects the functionality implemented in the 2nd pass CMOS-2 part. SPECIFIC CHANGES ------------------ Section 1.5 reflects the last known restriction (Reboot on ERR & cache miss and the last microcode change (MFPR bug). NOTE The following milestones are included for continuity purposes. For complete data refer to the "CVAX CPU Chip Engineering Specification - DC341" REV DATE REASON --- ---- ------ 4.0 9-Jun-88 This specification reflects the functionality implemented on the 4th pass part. 3.0 27-May-87 This specification reflects the functionality implemented on the 3rd pass part. 2.0 8-Dec-86 This specification reflects the functionality implemented on the 2nd pass part. 1.00 11-Nov-84 Preliminary version. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 7 INTRODUCTION 1 INTRODUCTION 1.1 Scope This document describes the CVAX CPU chip, a CMOS/VLSI chip that implements a VAX central processor. This specification describes the external interface and behavior of the chip. It does not describe the internal organization or operation of the chip. For further information, the applicable documents should be consulted. 1.2 Applicable Documents VAX Architecture Standard (DEC Standard 032) CVAX CPU Chip Design Specification CVAX CPU Chip Engineering Specification - DC341 CVAX Clock Chip Engineering Specification CMOS 2 CFPA Chip (DC581) Engineering Specification 1.3 CVAX CPU Chip Features The CVAX DC580 CPU chip is a 32-bit, virtual memory microprocessor. Implemented in CMOS-2 (`1.5 micron' double metal CMOS), the 180K transistor CVAX CPU chip is a high performance, low cost CPU for single board computers, single user workstations, low end systems, and multiple microprocessor systems. The DC580 is functionally equivalent to and pin-compatible with the DC341 CMOS I CVAX CPU. The DC580 has a higher performance figure than the DC341. Key features of the CVAX CPUs are: 1. Subset VAX data types. The CVAX CPU chip supports the following subset of the VAX data types: byte, word, longword, quadword, character string, and variable length bit field. Support for f_floating, d_floating, and g_floating data types is provided by an external Floating Point Coprocessor. Support for the remaining VAX data types can be provided by macrocode emulation. 2. Full base instruction group. The CVAX CPU chip implements the full base instruction group which consists of the following VAX instruction: integer and logical, address, variable length bit field, control, procedure call, miscellaneous, queue, CMPC3/CMPC5, LOCC, MOVC3/MOVC5, SCANC, SKPC, SPANC and operating system support. f_floating point, d_floating point, and g_floating point instructions are implemented in an external floating point unit (including the floating point instructions that are part of the CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 8 INTRODUCTION emulate-only instruction group: POLYf, EMULf, and ACBf). The remaining VAX instructions can be implemented via macrocode emulation (the CVAX CPU chip provides microcode assists for the emulation of character string instructions not included in the full base instruction group, decimal string, EDITPC, and CRC instructions). 3. Full VAX memory management. The CVAX CPU chip includes a demand paged memory management unit which is fully compatible with VAX memory management. System space addresses are virtually mapped through single level page tables, process space addresses through double level page tables. 4. On chip cache. The CVAX CPU chip includes 1k bytes of on chip cache to optimize the performance of the memory subsystem. The cache can be configured to store I-stream only references, or both I-stream and D-stream references. 5. The external interface is based on industry Standards. The CVAX CPU chip's external interface is a 32-bit custom implementation of the industry standard microprocessor interface. The CVAX CPU chip functionally replaces the MicroVAX CPU chip in existing designs although the exact timing, pin assignments, and external protocol have slightly changed. Chapter 9 highlights the interface differences between MicroVAX and CVAX. 6. Large virtual and physical address space. The CVAX CPU chip supports four gigabytes (2**32) of virtual memory, and one gigabyte (2**30) of physical memory. 7. High performance. The 21-24674-15 CVAX CPU chip achieves a 60 nsec microcycle and a 120 nsec I/O cycle. 8. Single package. The CVAX CPU chip is packaged in a standard 84-pin surface mounted chip carrier. 1.4 Summary Of Differences The principal differences between the CVAX CPU chip and the full VAX architecture are these: 1. The CVAX CPU chip omits these data types: decimal string, octaword, h_floating. [These data types can be supported via macrocode emulation.] 2. The CVAX CPU chip omits these instruction classes: character string instructions (MATCHC, MOVTC, MOVTUC), decimal string, EDITPC, CRC, compatibility mode, octaword, h_floating. [The chip provides microcode assists for the macrocode emulation of the character string, decimal string, CRC, and EDITPC instructions.] CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 9 INTRODUCTION 3. The CVAX CPU chip omits some of the VAX internal processor registers. Specifically, NICR, ICR, TODR, RXCS, RXDB, TXCS, TXDB and PMR are not built in CVAX. MFPR or MTPR references to these registers generate an external processor register read or write cycle, respectively. Therefore, these registers can be externally supported. 4. The CVAX CPU chip does not have a built-in console function. 1.5 Part Number Variation Descriptions Digital Part # Mask Letter/Rev Speed Restriction 21-24674-16 B / PASS 2.0 80nS Yes 21-24674-15 B / PASS 2.0 60nS Yes Restrictions: When operating correctly, if external logic asserts ERR L in response to any memory cycle other than an instruction prefetch or interrupt acknowledge, a machine check occurs. If a write error occurs that does not satisfy the problem conditions, a machine check is followed by execution of system error (macro)code. The error code will determine if a system reboot is needed. If the problem conditions are met, a immediate reboot with no machine check is the result. The restart code will be 3, initial power on. When a specific sequence of events combines with a write cycle and the write cycle ends with an error response, the CVAX will be forced to branch to the restart microcode (an error response is ERRL asserted and RDYL not asserted for two sample points). The problem can only occur when writing to memory or IO space. It does not occur when writing to an IPR and does not occur if the MEMERRL or CRDL interrupt inputs are asserted. The probability of the problem occurring are extremely small and occurs under the following specific circumstances: 1. Write is queued up in Bus Interface Unit (BIU) 2. The second sample point of an ERRL response to the write operation is seen at the same time as the start of a non-prefetch data read. 3. The above data read will result in a cache miss. If the read operation starts one cycle earlier or later, no problem occurs. If the read is an instruction prefetch, no problem occurs. If the read does not cause a cache miss, no problem occurs. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 10 ARCHITECTURE SUMMARY 2 ARCHITECTURE SUMMARY This section provides summary information about the architecture of the CVAX CPU chip. It is not intended as a complete reference but rather to give an overview of the user-visible features. For a complete description of the architecture, consult the "VAX Architecture Standard". 2.1 Visible State The visible state of the processor consists of memory, both virtual and physical, the general registers, and the processor status longword (PSL). 2.1.1 Virtual Address Space - The virtual address space is four gigabytes (2**32), as follows: +-------------------------+ 00000000 | | length of P0 Region in pages (P0LR) | | | P0 ----------------| | Region | | 3FFFFFFF | V | P0 Region growth direction +-------------------------+ 40000000 | ^ | P1 Region growth direction | | | | P1 ----------------| | Region | 7FFFFFFF | | length of P1 Region in pages (2**21-P1LR) +-------------------------+ 80000000 | | length of System Region in pages (SLR) | | | System ---------------| | Region | | BFFFFFFF | V | System Region growth direction +-------------------------+ C0000000 | | | | | Reserved | | Region | FFFFFFFF | | +-------------------------+ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 11 ARCHITECTURE SUMMARY 2.1.2 Physical Address Space - The physical address space is one gigabyte (2**30), as follows: +-------------------------+ 00000000 | | | | | Memory | | Space | | | 1FFFFFFF | | +-------------------------+ 20000000 | | | | | I/O | | Space | | | 3FFFFFFF | | +-------------------------+ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 12 ARCHITECTURE SUMMARY 2.1.3 Registers - 3 1 0 +---------------------------------------------------------------+ 16 general registers | | :Rn [R0 - R11, general purpose +---------------------------------------------------------------+ R12 = AP, argument pointer R13 = FP, frame pointer R14 = SP, stack pointer R15 = PC, program counter] 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 6 5 8 7 6 5 4 3 2 1 0 +-+-+---+-+-+---+---+-+---------+---------------+-+-+-+-+-+-+-+-+ | | | |F| | | |M| | | | | | | | | | | Processor Status Longword |C|T| |P|I|CUR|PRV|B| | |D|F|I| | | | | | :PSL [CM = compatibility mode |M|P|MBZ|D|S|MOD|MOD|Z| IPL | MBZ |V|U|V|T|N|Z|V|C| TP = trace pending +-+-+---+-+-+---+---+-+---------+---------------+-+-+-+-+-+-+-+-+ FPD = first part done IS = interrupt stack CUR = current mode PRV = previous mode IPL = interrupt priority level DV = decimal overflow trap enable FU = floating underflow fault enable IV = integer overflow trap enable T = trace trap enable N = negative condition code Z = zero condition code V = overflow condition code C = carry condition code] CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 13 ARCHITECTURE SUMMARY 2.2 Data Types The CVAX CPU chip supports nine data types: byte, word, longword, quadword, character string, variable length bit field, and, through an optional external processor, f_floating, d_floating, and g_floating. These are summarized below: Type Length Use Graphic Representation ---- ------ --- ------------------------ 7 0 +---------------+ Byte 8 bits signed or | | :A unsigned integer +---------------+ 1 5 0 +-------------------------------+ Word 16 bits signed or | | :A unsigned integer +-------------------------------+ 3 1 0 +---------------------------------------------------------------+ Longword 32 bits signed or | | :A unsigned integer +---------------------------------------------------------------+ 3 1 0 +---------------------------------------------------------------+ Quadword 64 bits signed integer | | :A +---------------------------------------------------------------+ | | :A+4 +---------------------------------------------------------------+ 6 3 3 2 7 0 +---------------+ Character 0-65k bytes byte string | | :A String +---------------+ | | :A+1 +---------------+ . . . +---------------+ | | :A+L-1 +---------------+ 7 0 CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 14 ARCHITECTURE SUMMARY P+S P+S-1 P P-1 0 +---------------------+------------------+----------------------+ Variable Length 0-32 bits bit string | |//////////////////| | :A Bit Field +---------------------+------------------+----------------------+ S-1 0 1 1 5 4 7 6 0 +-+---------------+-------------+ F_floating 32 bits floating point |S| exponent | fraction | :A +-+---------------+-------------+ | fraction | :A+2 +-------------------------------+ 3 1 1 6 1 1 5 4 7 6 0 +-+---------------+-------------+ D_floating 64 bits floating point |S| exponent | fraction | :A +-+---------------+-------------+ | fraction | :A+2 +-------------------------------+ | fraction | :A+4 +-------------------------------+ | fraction | :A+6 +-------------------------------+ 6 4 3 8 1 1 5 4 4 3 0 +-+---------------------+-------+ G_floating 64 bits floating point |S| exponent | frac | :A +-+---------------------+-------+ | fraction | :A+2 +-------------------------------+ | fraction | :A+4 +-------------------------------+ | fraction | :A+6 +-------------------------------+ 6 4 3 8 CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 15 ARCHITECTURE SUMMARY 2.3 Instruction Formats And Addressing Modes VAX instructions consist of a one- or two-byte opcode, followed by zero to six operand specifiers. 2.3.1 Opcode Formats - 7 0 +---------------+ One byte opcode: | opcode | :A +---------------+ 1 5 8 7 0 +---------------+---------------+ Two byte opcode: | opcode | FD | :A +---------------+---------------+ 2.3.2 General Register Operand Specifiers - The general register address modes are: 7 4 3 0 +-------+-------+ | mode | reg | +-------+-------+ Access Mode Name Assembler r m w a v PC SP Indexable? ---- ---- --------- --------- -- -- ---------- 0-3 literal S^#literal y f f f f - - f 4 index i[Rx] y y y y y f y f 5 register Rn y y y f y u uq f 6 register deferred (Rn) y y y y y u y y 7 autodecrement -(Rn) y y y y y u y ux 8 autoincrement (Rn)+ y y y y y p y ux 9 autoincrement @(Rn)+ y y y y y p y ux deferred A byte displacement B^d(Rn) y y y y y p y y B byte displacement @B^d(Rn) y y y y y p y y deferred C word displacement W^d(Rn) y y y y y p y y D word displacement @W^d(Rn) y y y y y p y y deferred E longword displacement L^d(Rn) y y y y y p y y F longword displacement @L^d(Rn) y y y y y p y y deferred CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 16 ARCHITECTURE SUMMARY If the register is the PC, the address modes are: 7 4 3 0 +-------+-------+ | mode |1 1 1 1| +-------+-------+ Access Mode Name Assembler r m w a v Indexable? ---- ---- --------- --------- ---------- 8 Immediate I^#constant y u u y y u 9 absolute @#address y y y y y y A byte relative B^address y y y y y y B byte relative @B^address y y y y y y deferred C word relative W^address y y y y y y D word relative W^address y y y y y y deferred E longword relative L^address y y y y y y F longword relative L^address y y y y y y deferred Addressing Legend Access: Syntax: Results: r = read i = any Indexable address mode y = yes, always valid address mode m = modify d = displacement f = reserved address mode fault w = write Rn = general register, n = to 15 - = logically impossible a = address Rx = general register, x = to 14 p = program counter addressing v = field u = unpredictable uq = unpredictable for quad, d/g_floating, and field if pos + size > 32 ux = unpredictable if index reg = base reg 2.3.3 Branch Operand Specifiers - 7 0 +---------------+ Signed byte displacement: | displ | +---------------+ 1 5 0 +-------------------------------+ Signed word displacement: | displ | +-------------------------------+ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 17 ARCHITECTURE SUMMARY 2.4 Instruction Set The standard notation for operand specifiers is: . where: 1. Name is a suggestive name for the operand in the context of the instruction. It is the capitalized name of a register or block for implied operands. 2. Access type is a letter denoting the operand specifier access type. a = address operand b = branch displacement m = modified operand (both read and written) r = read only operand v = if not "Rn", same as a, otherwise R[n+1]'R[n] w = write only operand 3. Data type is a letter denoting the data type of the operand. b = byte d = d_floating f = f_floating g = g_floating l = longword q = quadword v = field (used only in implied operands) w = word * = multiple longwords (used only in implied operands) 4. Implied operands, that is, locations that are accessed by the instruction, but not specified in an operand, are denoted by curly braces {}. The abbreviations for condition codes are: * = conditionally set/cleared - = not affected 0 = cleared 1 = set The abbreviations for exceptions are: rsv = reserved operand fault iov = integer overflow trap idvz = integer divide by zero trap fov = floating overflow fault fuv = floating underflow fault fdvz = floating divide by zero fault dov = decimal overflow trap ddvz = decimal divide by zero trap sub = subscript range trap CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 18 ARCHITECTURE SUMMARY prv = privileged instruction fault 2.4.1 Integer Arithmetic And Logical Instructions - Opcode Instruction N Z V C Exceptions ------ ----------- ------- ---------- 58 ADAWI add.rw, sum.mw * * * * iov 80 ADDB2 add.rb, sum.mb * * * * iov C0 ADDL2 add.rl, sum.ml * * * * iov A0 ADDW2 add.rw, sum.mw * * * * iov 81 ADDB3 add1.rb, add2.rb, sum.wb * * * * iov C1 ADDL3 add1.rl, add2.rl, sum.wl * * * * iov A1 ADDW3 add1.rw, add2.rw, sum.ww * * * * iov D8 ADWC add.rl, sum.ml * * * * iov 78 ASHL cnt.rb, src.rl, dst.wl * * * 0 iov 79 ASHQ cnt.rb, src.rq, dst.wq * * * 0 iov 8A BICB2 mask.rb, dst.mb * * 0 - CA BICL2 mask.rl, dst.ml * * 0 - AA BICW2 mask.rw, dst.mw * * 0 - 8B BICB3 mask.rb, src.rb, dst.wb * * 0 - CB BICL3 mask.rl, src.rl, dst.wl * * 0 - AB BICW3 mask.rw, src.rw, dst.ww * * 0 - 88 BICB2 mask.rb, dst.mb * * 0 - C8 BISL2 mask.rl, dst.ml * * 0 - A8 BISW2 mask.rw, dst.mw * * 0 - 89 BISB3 mask.rb, src.rb, dst.wb * * 0 - C9 BISL3 mask.rl, src.rl, dst.wl * * 0 - A9 BISW3 mask.rw, src.rw, dst.ww * * 0 - 93 BITB mask.rb, src.rb * * 0 - D3 BITL mask.rl, src.rl * * 0 - B3 BITW mask.rw, src.rw * * 0 - 94 CLRB dst.wb 0 1 0 - D4 CLRL{=F} dst.wl 0 1 0 - 7C CLRQ{=D=G} dst.wq 0 1 0 - B4 CLRW dst.ww 0 1 0 - 91 CMPB src1.rb, src2.rb * * 0 * D1 CMPL src1.rl, src2.rl * * 0 * B1 CMPW src1.rw, src2.rw * * 0 * 98 CVTBL src.rb, dst.wl * * 0 0 99 CVTBW src.rb, dst.wl * * 0 0 CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 19 ARCHITECTURE SUMMARY F6 CVTLB src.rl, dst.wb * * * 0 iov F7 CVTLW src.rl, dst.ww * * * 0 iov 33 CVTWB src.rw, dst.wb * * * 0 iov 32 CVTWL src.rw, dst.wl * * 0 0 97 DECB dif.mb * * * * iov D7 DECL dif.ml * * * * iov B7 DECW dif.mw * * * * iov 86 DIVB2 divr.rb, quo.mb * * * 0 iov, idvz C6 DIVL2 divr.rl, quo.ml * * * 0 iov, idvz A6 DIVW2 divr.rw, quo.mw * * * 0 iov, idvz 87 DIVB3 divr.rb, divd.rb, quo.wb * * * 0 iov, idvz C7 DIVL3 divr.rl, divd.rl, quo.wl * * * 0 iov, idvz A7 DIVW3 divr.rw, divd.rw, quo.ww * * * 0 iov, idvz 7B EDIV divr.rl, divd.rq, quo.wl, rem.wl * * * 0 iov, idvz 7A EMUL mulr.rl, muld.rl, add.rl, prod.wq * * 0 0 96 INCB sum.mb * * * * iov D6 INCL sum.ml * * * * iov B6 INCW sum.mw * * * * iov 92 MCOMB src.rb, dst.wb * * 0 - D2 MCOML src.rl, dst.wl * * 0 - B2 MCOMW src.rw, dst.ww * * 0 - 8E MNEGB src.rb, dst.wb * * * * iov CE MNEGL src.rl, dst.wl * * * * iov AE MNEGW src.rw, dst.ww * * * * iov 90 MOVB src.rb, dst.wb * * 0 - D0 MOVL src.rl, dst.wl * * 0 - 7D MOVQ src.rq, dst.wq * * 0 - B0 MOVW src.rw, dst.ww * * 0 - 9A MOVZBW src.rb, dst.wb 0 * 0 - 9B MOVZBL src.rb, dst.wl 0 * 0 - 3C MOVZWL src.rw, dst.ww 0 * 0 - 84 MULB2 mulr.rb, prod.mb * * * 0 iov C4 MULL2 mulr.rl, prod.ml * * * 0 iov A4 MULW2 mulr.rw, prod.mw * * * 0 iov 85 MULB3 mulr.rb, muld.rb, prod.wb * * * 0 iov C5 MULL3 mulr.rl, muld.rl, prod.wl * * * 0 iov A5 MULW3 mulr.rw, muld.rw, prod.ww * * * 0 iov DD PUSHL src.rl, {-(SP).wl} * * 0 - 9C ROTL cnt.rb, src.rl, dst.wl * * 0 - D9 SBWC sub.rl, dif.ml * * * * iov CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 20 ARCHITECTURE SUMMARY 82 SUBB2 sub.rb, dif.mb * * * * iov C2 SUBL2 sub.rl, dif.ml * * * * iov A2 SUBW2 sub.rw, dif.mw * * * * iov 83 SUBB3 sub.rb, min.rb, dif.wb * * * * iov C3 SUBL3 sub.rl, min.rl, dif.wl * * * * iov A3 SUBW3 sub.rw, min.rw, dif.ww * * * * iov 95 TSTB src.rb * * 0 0 D5 TSTL src.rl * * 0 0 B5 TSTW src.rw * * 0 0 8C XORB2 mask.rb, dst.mb * * 0 - CC XORL2 mask.rl, dst.ml * * 0 - AC XORB2 mask.rw, dst.mw * * 0 - 8D XORB3 mask.rb, src.rb, dst.wb * * 0 - CD XORL3 mask.rl, src.rl, dst.wl * * 0 - AD XORW3 mask.rw, src.rw, dst.ww * * 0 - 2.4.2 Address Instructions - Opcode Instruction N Z V C Exceptions ------ ----------- ------- ---------- 9E MOVAB src.ab, dst.wl * * 0 - DE MOVAL{=F} src.al, dst.wl * * 0 - 7E MOVAQ{=D=G} src.aq, dst.wl * * 0 - 3E MOVAW src.aw, dst.wl * * 0 - 9F PUSHAB src.ab, {-(SP).wl} * * 0 - DF PUSHAL{=F} src.al, {-(SP).wl} * * 0 - 7F PUSHAQ{=D=G} src.aq, {-(SP).wl} * * 0 - 3F PUSHAW src.aw, {-(SP).wl} * * 0 - 2.4.3 Variable Length Bit Field Instructions - Opcode Instruction N Z V C Exceptions ------ ----------- ------- ---------- EC CMPV pos.rl, size.rb, base.vb, {field.rv}, src.rl * * 0 * rsv ED CMPZV pos.rl, size.rb, base.vb, {field.rv}, src.rl * * 0 * rsv EE EXTV pos.rl, size.rb, base.vb, {field.rv}, dst.wl * * 0 - rsv EF EXTZV pos.rl, size.rb, base.vb, {field.rv}, dst.wl * * 0 - rsv F0 INSV src.rl, pos.rl, size.rb, base.vb, {field.wv} - - - - rsv CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 21 ARCHITECTURE SUMMARY EB FFC startpos.rl, size.rb, base.vb, {field.rv}, findpos.wl 0 * 0 0 rsv EA FFS startpos.rl, size.rb, base.vb, {field.rv}, findpos.wl 0 * 0 0 rsv 2.4.4 Control Instructions - Opcode Instruction N Z V C Exceptions ------ ----------- ------- ---------- 9D ACBB limit.rb, add.rb, index.mb, displ.bw * * * - iov F1 ACBL limit.rl, add.rl, index.ml, displ.bw * * * - iov 3D ACBW limit.rw, add.rw, index.mw, displ.bw * * * - iov F3 AOBLEQ limit.rl, index.ml, displ.bb * * * - iov F2 AOBLSS limit.rl, index.ml, displ.bb * * * - iov 1E BCC{=BGEQU} displ.bb - - - - 1F BCS{=BLSSU} displ.bb - - - - 13 BEQL{=BEQLU} displ.bb - - - - 18 BGEQ displ.bb - - - - 14 BGTR displ.bb - - - - 1A BGTRU displ.bb - - - - 15 BLEQ displ.bb - - - - 1B BLEQU displ.bb - - - - 19 BLSS displ.bb - - - - 12 BNEQ{=BNEQU} displ.bb - - - - 1C BVC displ.bb - - - - 1D BVS displ.bb - - - - E1 BBC pos.rl, base.vb, displ.bb, {field.rv} - - - - rsv E0 BBS pos.rl, base.vb, displ.bb, {field.rv} - - - - rsv E5 BBCC pos.rl, base.vb, displ.bb, {field.mv} - - - - rsv E3 BBCS pos.rl, base.vb, displ.bb, {field.mv} - - - - rsv E4 BBSC pos.rl, base.vb, displ.bb, {field.mv} - - - - rsv E2 BBSS pos.rl, base.vb, displ.bb, {field.mv} - - - - rsv E7 BBCCI pos.rl, base.vb, displ.bb, {field.mv} - - - - rsv E6 BBSSI pos.rl, base.vb, displ.bb, {field.mv} - - - - rsv E9 BLBC src.rl, displ.bb - - - - E8 BLBS src.rl, displ.bb - - - - 11 BRB displ.bb - - - - 31 BRW displ.bw - - - - 10 BSBB displ.bb, {-(SP).wl} - - - - 30 BSBW displ.bw, {-(SP).wl} - - - - 8F CASEB selector.rb, base.rb, limit.rb, displ.bw-list * * 0 * CF CASEL selector.rl, base.rl, limit.rl, displ.bw-list * * 0 * AF CASEW selector.rw, base.rw, limit.rw, displ.bw-list * * 0 * CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 22 ARCHITECTURE SUMMARY 17 JMP dst.ab - - - - 16 JSB dst.ab, {-(SP).wl} - - - - 05 RSB {(SP)+.rl} - - - - F4 SOBGEQ index.ml, displ.bb * * * - iov F5 SOBGTR index.ml, displ.bb * * * - iov 2.4.5 Procedure Call Instructions - Opcode Instruction N Z V C Exceptions ------ ----------- ------- ---------- FA CALLG arglist.ab, dst.ab, {-(SP).w*} 0 0 0 0 rsv FB CALLS numarg.rl, dst.ab, {-(SP).w*} 0 0 0 0 rsv 04 RET {(SP)+.r*} * * * * rsv 2.4.6 Miscellaneous Instructions - Opcode Instruction N Z V C Exceptions ------ ----------- ------- ---------- B9 BICPSW mask.rw * * * * rsv B8 BISPSW mask.rw * * * * rsv 03 BPT {-(KSP).w*} 0 0 0 0 00 HALT {-(KSP).w*} - - - - prv 0A INDEX subscript.rl, low.rl, high.rl, size.rl, indexin.rl, * * 0 0 sub indexout.wl DC MOVPSL dst.wl - - - - 01 NOP - - - - BA POPR mask.rw, {(SP)+.r*} - - - - BB PUSHR mask.rw, {-(SP).w*} - - - - FC XFC {unspecified operands} 0 0 0 0 CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 23 ARCHITECTURE SUMMARY 2.4.7 Queue Instructions - Opcode Instruction N Z V C Exceptions ------ ----------- ------- ---------- 5C INSQHI entry.ab, header.aq 0 * 0 * rsv 5D INSQTI entry.ab, header.aq 0 * 0 * rsv 0E INSQUE entry.ab, pred.ab * * 0 * 5E REMQHI header.aq, addr.wl 0 * * * rsv 5F REMQTI header.aq, addr.wl 0 * * * rsv 0F REMQUE entry.ab, addr.wl * * * * 2.4.8 Character String Instructions - Opcode Instruction N Z V C Exceptions ------ ----------- ------- ---------- 29 CMPC3 len.rw, src1addr.ab, src2addr.ab * * 0 * 2D CMPC5 src1len.rw, src1addr.ab, fill.rb, * * 0 * src2len.rw, src2addr.ab 3A LOCC char.rb, len.rw, addr.ab 0 * 0 0 28 MOVC3 len.rw, srcaddr.ab, dstaddr.ab, {R0-5.wl} 0 1 0 0 2C MOVC5 srclen.rw, srcaddr.ab, fill.rb, dstlen.rw, dstaddr.ab, * * 0 * {R0-5.wl} 2A SCANC len.rw, addr.ab, tbladdr.ab, mask.rb 0 * 0 0 3B SKPC char.rb, len.rw, addr.ab 0 * 0 0 2B SPANC len.rw, addr.ab, tbladdr.ab, mask.rb 0 * 0 0 2.4.9 Operating System Support Instructions - Opcode Instruction N Z V C Exceptions ------ ----------- ------- ---------- BD CHME param.rw, {-(ySP).w*} 0 0 0 0 BC CHMK param.rw, {-(ySP).w*} 0 0 0 0 BE CHMS param.rw, {-(ySP).w*} 0 0 0 0 CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 24 ARCHITECTURE SUMMARY BF CHMU param.rw, {-(ySP).w*} 0 0 0 0 Where y=MINU(x, PSL) 06 LDPCTX {PCB.r*, -(KSP).w*} - - - - rsv, prv DB MFPR procreg.rl, dst.wl * * 0 - rsv, prv DA MTPR src.rl, procreg.rl * * 0 - rsv, prv 0C PROBER mode.rb, len.rw, base.ab 0 * 0 - 0D PROBEW mode.rb, len.rw, base.ab 0 * 0 - 02 REI {(SP)+.r*} * * * * rsv 07 SVPCTX {(SP)+.r*, PCB.w*} - - - - prv 2.4.10 Floating Point Instructions - These instructions are implemented in hardware only if an external floating point unit is present in the system. Opcode Instruction N Z V C Exceptions ------ ----------- ------- ---------- 6F ACBD limit.rd, add.rd, index.md,displ.bw * * 0 - rsv, fov, fuv 4F ACBF limit.rf, add.rf, index.mf,displ.bw * * 0 - rsv, fov, fuv 4FFD ACBG limit.rg, add.rg, index.mg,displ.bw * * 0 - rsv, fov, fuv 60 ADDD2 add.rd, sum.md * * 0 0 rsv, fov, fuv 40 ADDF2 add.rf, sum.mf * * 0 0 rsv, fov, fuv 40FD ADDG2 add.rg, sum.mg * * 0 0 rsv, fov, fuv 61 ADDD3 add1.rd, add2.rd, sum.wd * * 0 0 rsv, fov, fuv 41 ADDF3 add1.rf, add2.rf, sum.wf * * 0 0 rsv, fov, fuv 41FD ADDG3 add1.rg, add2.rg, sum.wg * * 0 0 rsv, fov, fuv 71 CMPD src1.rd, src2.rd * * 0 0 rsv 51 CMPF src1.rf, src2.rf * * 0 0 rsv 51FD CMPG src1.rg, src2.rg * * 0 0 rsv 6C CVTBD src.rb, dst.wd * * 0 0 4C CVTBF src.rb, dst.wf * * 0 0 4CFD CVTBG src.rb, dst.wg * * 0 0 68 CVTDB src.rd, dst.wb * * * 0 rsv, iov 76 CVTDF src.rd, dst.wf * * 0 0 rsv, fov 6A CVTDL src.rd, dst.wl * * * 0 rsv, iov 69 CVTDW src.rd, dst.ww * * * 0 rsv, iov 48 CVTFB src.rf, dst.wb * * * 0 rsv, iov 56 CVTFD src.rf, dst.wd * * 0 0 rsv 99FD CVTFG src.rf, dst.wg * * 0 0 rsv 4A CVTFL src.rf, dst.wl * * * 0 rsv, iov 49 CVTFW src.rf, dst.ww * * * 0 rsv, iov 48FD CVTGB src.rg, dst.wb * * * 0 rsv, iov 33FD CVTGF src.rg, dst.wf * * 0 0 rsv, fov, fuv CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 25 ARCHITECTURE SUMMARY 4AFD CVTGL src.rg, dst.wl * * * 0 rsv, iov 49FD CVTGW src.rg, dst.ww * * * 0 rsv, iov 6E CVTLD src.rl, dst.wd * * 0 0 4E CVTLF src.rl, dst.wf * * 0 0 4EFD CVTLG src.rl, dst.wg * * 0 0 6D CVTWD src.rw, dst.wd * * 0 0 4D CVTWF src.rw, dst.wf * * 0 0 4DFD CVTWG src.rw, dst.wg * * 0 0 6B CVTRDL src.rd, dst.wl * * * 0 rsv, iov 4B CVTRFL src.rf, dst.wl * * * 0 rsv, iov 4BFD CVTRGL src.rg, dst.wl * * * 0 rsv, iov 66 DIVD2 divr.rd, quo.md * * 0 0 rsv, fov, fuv, fdvz 46 DIVF2 divr.rf, quo.mf * * 0 0 rsv, fov, fuv, fdvz 46FD DIVG2 divr.rg, quo.mg * * 0 0 rsv, fov, fuv, fdvz 67 DIVD3 divr.rd, divd.rd, quo.wd * * 0 0 rsv, fov, fuv, fdvz 47 DIVF3 divr.rf, divd.rf, quo.wf * * 0 0 rsv, fov, fuv, fdvz 47FD DIVG3 divr.rg, divd.rg, quo.wg * * 0 0 rsv, fov, fuv, fdvz 74 EMODD mulr.rd, mulrx.rb, muld.rd, int.wl, fract.wd * * * 0 rsv, fov, fuv, iov 54 EMODF mulr.rf, mulrx.rb, muld.rf, int.wl, fract.wf * * * 0 rsv, fov, fuv, iov 54FD EMODG mulr.rg, mulrx.rw, muld.rg, int.wl, fract.wg * * * 0 rsv, fov, fuv, iov 72 MNEGD src.rd, dst.wd * * 0 0 rsv 52 MNEGF src.rf, dst.wf * * 0 0 rsv 52FD MNEGG src.rg, dst.wg * * 0 0 rsv 70 MOVD src.rd, dst.wd * * 0 - rsv 50 MOVF src.rf, dst.wf * * 0 - rsv 50FD MOVG src.rg, dst.wg * * 0 - rsv 64 MULD2 mulr.rd, prod.md * * 0 0 rsv, fov, fuv 44 MULF2 mulr.rf, prod.mf * * 0 0 rsv, fov, fuv 44FD MULG2 mulr.rg, prod.mg * * 0 0 rsv, fov, fuv 65 MULD3 mulr.rd, muld.rd, prod.wd * * 0 0 rsv, fov, fuv 45 MULF3 mulr.rf, muld.rf, prod.wf * * 0 0 rsv, fov, fuv 45FD MULG3 mulr.rg, muld.rg, prod.wg * * 0 0 rsv, fov, fuv 75 POLYD arg.rd, degree.rw, table.ab * * 0 0 rsv, fov, fuv 55 POLYF arg.rf, degree.rw, table.ab * * 0 0 rsv, fov, fuv 55FD POLYG arg.rf, degree.rw, table.ab * * 0 0 rsv, fov, fuv 62 SUBD2 sub.rd, dif.md * * 0 0 rsv, fov, fuv 42 SUBF2 sub.rf, dif.mf * * 0 0 rsv, fov, fuv 42FD SUBG2 sub.rg, dif.mg * * 0 0 rsv, fov, fuv 63 SUBD3 sub.rd, min.rd, dif.wd * * 0 0 rsv, fov, fuv 43 SUBF3 sub.rf, min.rf, dif.wf * * 0 0 rsv, fov, fuv 43FD SUBG3 sub.rg, min.rg, dif.wg * * 0 0 rsv, fov, fuv 73 TSTD src.rd * * 0 0 rsv 53 TSTF src.rf * * 0 0 rsv 53FD TSTG src.rg * * 0 0 rsv CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 26 ARCHITECTURE SUMMARY 2.4.11 Microcode-Assisted Emulated Instructions - The chip provides microcode assistance for the macrocode emulation of these instructions. The chip processes each operand specifier, creates a standard argument list, and invokes an emulation routine to perform emulation. Opcode Instruction N Z V C Exceptions ------ ----------- ------- ---------- 20 ADDP4 addlen.rw, addaddr.ab, sumlen.rw, sumaddr.ab * * * 0 rsv, dov 21 ADDP6 add1len.rw, add1addr.ab, add2len.rw, add2addr.ab, * * * 0 rsv, dov sumlen.rw, sumaddr.ab F8 ASHP cnt.rb, srclen.rw, srcaddr.ab, round.rb, * * * 0 rsv, dov dstlen.rw, dstaddr.ab 35 CMPP3 len.rw, src1addr.ab, src2addr.ab * * 0 0 37 CMPP4 src1len.rw, src1addr.ab, src2len.rw, src2addr.ab * * 0 0 0B CRC tbl.ab, inicrc.rl, strlen.rw, stream.ab * * 0 0 F9 CVTLP src.rl, dstlen.rw, dstaddr.ab * * * 0 rsv, dov 36 CVTPL srclen.rw, srcaddr.ab, dst.wl * * * 0 rsv, iov 08 CVTPS srclen.rw, srcaddr.ab, dstlen.rw, dstaddr.ab * * * 0 rsv, dov 09 CVTSP srclen.rw, srcaddr.ab, dstlen.rw, dstaddr.ab * * * 0 rsv, dov 24 CVTPT srclen.rw, srcaddr.ab, tbladdr.ab, * * * 0 rsv, dov dstlen.rw, dstaddr.ab 26 CVTTP srclen.rw, srcaddr.ab, tbladdr.ab, * * * 0 rsv, dov dstlen.rw, dstaddr.ab 27 DIVP divrlen.rw, divraddr.ab, divdlen.rw, divdaddr.ab, * * * 0 rsv, dov, ddvz quolen.rw, quoaddr.ab 38 EDITPC srclen.rw, srcaddr.ab, pattern.ab, dstaddr.ab * * * * rsv, dov 39 MATCHC objlen.rw, objaddr.ab, srclen.rw, srcaddr.ab 0 * 0 0 34 MOVP len.rw, srcaddr.ab, dstaddr.ab * * 0 0 2E MOVTC srclen.rw, srcaddr.ab, fill.rb, tbladdr.ab, * * 0 * dstlen.rw, dstaddr.ab 2F MOVTUC srclen.rw, srcaddr.ab, esc.rb, tbladdr.ab, * * * * dstlen.rw, dstaddr.ab 25 MULP mulrlen.rw, mulraddr.ab, muldlen.rw, muldaddr.ab, * * * 0 rsv, dov prodlen.rw, prodaddr.ab 22 SUBP4 sublen.rw, subaddr.ab, diflen.rw, difaddr.ab * * * 0 rsv, dov 23 SUBP6 sublen.rw, subaddr.ab, minlen.rw, minaddr.ab, * * * 0 rsv, dov diflen.rw, difaddr.ab CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 27 ARCHITECTURE SUMMARY 2.5 Memory Management The VAX architecture provides a four gigabyte (2**32) virtual address space, divided into two sections, system space and process space. Process space is further subdivided into the P0 region and the P1 region. 2.5.1 Memory Management Control Registers - Memory management is controlled by three processor registers: Memory Management Enable (MAPEN), Translation Buffer Invalidate Single (TBIS), and Translation Buffer Invalidate All (TBIA). MAPEN contains one bit: MAPEN<0> = MME enables memory management. 3 1 1 0 +-------------------------------------------------------------+-+ | |M| | MBZ |M| :MAPEN | |E| +-------------------------------------------------------------+-+ TBIS controls translation buffer invalidation. Writing a virtual address into TBIS invalidates any entry which maps that virtual address. 3 1 0 +---------------------------------------------------------------+ | Virtual Address | :TBIS +---------------------------------------------------------------+ TBIA also controls translation buffer invalidation. Writing a zero into TBIA invalidates the entire translation buffer. 3 1 0 +---------------------------------------------------------------+ | MBZ | :TBIA +---------------------------------------------------------------+ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 28 ARCHITECTURE SUMMARY 2.5.2 System Space Address Translation - A virtual address with bits <31:30> = 2 is an address in the system virtual address space. System virtual address space is mapped by the System Page Table (SPT), which is defined by the System Base Register (SBR) and the System Length Register (SLR). The SBR contains the physical address of the the System Page Table. The SLR contains the size of the SPT in longwords, that is, the number of Page Table Entries. The Page Table Entry addressed by the System Base Register maps the first page of system virtual address space, that is, virtual byte address 80000000 (hex). 3 3 2 1 0 9 2 1 0 +---+-------------------------------------------------------+---+ |MBZ| physical longword address of SPT |MBZ| :SBR +---+-------------------------------------------------------+---+ 3 2 2 1 2 1 0 +-------------------+-------------------------------------------+ | MBZ | length of SPT in longwords | :SLR +-------------------+-------------------------------------------+ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 29 ARCHITECTURE SUMMARY 3 3 2 1 0 9 9 8 0 +---+--------------------+--------+ SVA: | 2 | | byte | (System Virtual +---+--------------------+--------+ Address) | extract and | | 3 2|2 check length | | 1 3|2 2|10 | +--------+--------------------+--+ | | 0 | | 0| | +--------+--------------------+--+ | | | add | | +-----------------------------+--+ | SBR: | Physical Base Adr of SPT | 0| | +-----------------------------+--+ | | yields | | +-----------------------------+--+ | | Physical Adr of PTE | 0| | +-----------------------------+--+ | | fetch | | 3 3 2 2 | 1 0 1 0 0 | +-+--------+--------------------+ | PTE: |1| | PFN | | +-+--------+--------------------+ | check access | this access check | | | in current mode | | | | | |2 | | |9 9|8 V 0 +--------------------+--------+ Physical Adr of Data: | | | +--------------------+--------+ System Virtual to Physical Translation CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 30 ARCHITECTURE SUMMARY 2.5.3 Process Space Address Translation - A virtual address with bit <31> = 0 is an address in the process virtual address space. Process space is divided into two equal sized, separately mapped regions. If virtual address bit <30> = 0, the address is in region P0. If virtual address bit <30> = 1, the address is in region P1. 2.5.3.1 P0 Region Address Translation - The P0 region of the address space is mapped by the P0 Page Table (P0PT), which is defined by the P0 Base Register (P0BR) and the P0 Length Register (P0LR). The P0BR contains the system virtual address of the P0 Page Table. The P0LR contains the size of the P0PT in longwords, that is, the number of Page Table Entries. The Page Table Entry addressed by the P0 Base Register maps the first page of the P0 region of the virtual address space, that is, virtual byte address 0. 3 3 2 1 0 9 2 1 0 +---+-------------------------------------------------------+---+ | 2 | system virtual longword address of P0PT |MBZ| :P0BR +---+-------------------------------------------------------+---+ 3 2 2 1 2 1 0 +-------------------+-------------------------------------------+ | MBZ | length of P0PT in longwords | :P0LR +-------------------+-------------------------------------------+ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 31 ARCHITECTURE SUMMARY 3 3 2 1 0 9 9 8 0 +---+--------------------+--------+ PVA: | 0 | | byte | (Process Virtual +---+--------------------+--------+ Address) | extract and | | 3 2|2 check length | | 1 3|2 2|10 | +--------+--------------------+--+ | | 0 | | 0| | +--------+--------------------+--+ | | | add | | +-----------------------------+--+ | P0BR: | Sys Virt Base Adr of P0PT | 0| | +-----------------------------+--+ | | yields | | +-----------------------------+--+ | | Virtual Adr of PTE | 0| | +-----------------------------+--+ | | fetch by system space | translation algorithm, | including length check | | 3 3 2 2 | 1 0 1 0 0 | +-+--------+--------------------+ | PTE: |1| | PFN | | +-+--------+--------------------+ | check access | this access check | | | in current mode | | | | | |2 | | |9 9|8 V 0 +--------------------+--------+ Physical Adr of Data: | | | +--------------------+--------+ P0 Virtual to Physical Translation CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 32 ARCHITECTURE SUMMARY 2.5.3.2 P1 Region Address Translation - The P1 region of the address space is mapped by the P1 Page Table (P1PT), which is defined by the P1 Base Register (P1BR) and the P1 Length Register (P1LR). Because P1 space grows towards smaller addresses, and because a consistent hardware interpretation of the base and length registers is desirable, P1BR and P1LR describe the portion of P1 space that is NOT accessible. Note that P1LR contains the number of nonexistent PTEs. P1BR contains the virtual address of what would be the PTE for the first page of P1, that is, virtual byte address 40000000 (hex). The address in P1BR is not necessarily a valid virtual address, but all the addresses of PTEs must be valid virtual addresses. 3 1 2 1 0 +-----------------------------------------------------------+---+ | virtual longword address of P1PT |MBZ| :P1BR +-----------------------------------------------------------+---+ 3 2 2 1 2 1 0 +-------------------+-------------------------------------------+ | MBZ | length of P1PT in longwords | :P1LR +-------------------+-------------------------------------------+ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 33 ARCHITECTURE SUMMARY 3 3 2 1 0 9 9 8 0 +---+--------------------+--------+ PVA: | 1 | | byte | (Process Virtual +---+--------------------+--------+ Address) | extract and | | 3 2|2 check length | | 1 3|2 2|10 | +--------+--------------------+--+ | | 0 | | 0| | +--------+--------------------+--+ | | add | | +-----------------------------+--+ | P1BR: | Virt Base Adr of P1PT | 0| | +-----------------------------+--+ | | yields | | +-----------------------------+--+ | | Virtual Adr of PTE | 0| | +-----------------------------+--+ | | fetch by system space | translation algorithm, | including length check | | 3 3 2 2 | 1 0 1 0 0 | +-+--------+--------------------+ | PTE: |1| | PFN | | +-+--------+--------------------+ | check access | this access check | | | in current mode | | | | | |2 | | |9 9|8 V 0 +--------------------+--------+ Physical Adr of Data: | | | +--------------------+--------+ P1 Virtual to Physical Translation CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 34 ARCHITECTURE SUMMARY 2.5.4 Page Table Entry - The format of a page table entry is: 3 3 2 2 2 2 2 2 2 2 1 0 7 6 5 4 3 2 1 0 0 +-+-------+-+-+---+---+-----------------------------------------+ |V| PROT |M|0|OWN| 0 | PFN | :PTE +-+-------+-+-+---+---+-----------------------------------------+ The protection code access matrix is: code current mode decimal binary mnemonic K E S U comment ------- ------ -------- - - - - ------- 0 0000 NA - - - - no access 1 0001 unpredictable reserved 2 0010 KW RW - - - 3 0011 KR R - - - 4 0100 UW RW RW RW RW all access 5 0101 EW RW RW - - 6 0110 ERKW RW R - - 7 0111 ER R R - - 8 1000 SW RW RW RW - 9 1001 SREW RW RW R - 10 1010 SRKW RW R R - 11 1011 SR R R R - 12 1100 URSW RW RW RW R 13 1101 UREW RW RW R R 14 1110 URKW RW R R R 15 1111 UR R R R R K = kernel R = read E = executive W = write S = supervisor - = no access U = user CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 35 ARCHITECTURE SUMMARY 2.5.5 Translation Buffer - In order to save actual memory references when repeatedly referencing pages, The CVAX CPU chip uses a translation buffer to remember successful virtual address translations and page status. The translation buffer contains 28 fully associative entries. Both system and process references share these entries. Translation buffer entries are replaced using a not last used (NLU) algorithm. NLU guarantees that the replacement pointer is not pointing at the last translation buffer entry to be used. This is accomplished by rotating the replacement pointer to the next sequential translation buffer entry if it is pointing to an entry that has just been accessed. Both D-stream and I-stream references can cause the NLU to cycle. When the translation buffer does not contain a reference's virtual address and page status, the machine updates the translation buffer by replacing the entry that is selected by the replacement pointer. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 36 ARCHITECTURE SUMMARY 2.6 Exceptions And Interrupts Both exceptions and interrupts divert execution from the normal flow of control. An exception is caused by the execution of the current instruction, while an interrupt is caused by some activity outside the central processor. 2.6.1 Interrupts - The VAX architecture has 31 interrupt priority levels (IPL), used as follows: IPL levels interrupt condition ---------- ------------------- 1F unused 1E PWRFL L asserted 1D MEMERR L asserted 1B - 1C unused 1A CRD L asserted 18 - 19 unused 17 IRQ<3> L asserted 16 IRQ<2> L asserted 16 INTTIM L asserted 15 IRQ<1> L asserted 14 IRQ<0> L asserted 10 - 13 unused 01 - 0F software interrupt request The interrupt system is controlled by the Interrupt Priority Level Register (IPL, corresponds to PSL<20:16>), the Software Interrupt Request Register (SIRR), and the Software Interrupt Summary Register (SISR). 3 1 5 4 0 +----------------------------------------------------+----------+ | ignored, returns 0 |PSL<20:16>| :IPL +----------------------------------------------------+----------+ 3 1 4 3 0 +-------------------------------------------------------+-------+ | ignored |request| :SIRR +-------------------------------------------------------+-------+ 3 1 1 1 6 5 0 +-------------------------------+-----------------------------+-+ | | Pending Software Interrupts |M| | | |B| :SISR | |F E D C B A 9 8 7 6 5 4 3 2 1|Z| +-------------------------------+-----------------------------+-+ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 37 ARCHITECTURE SUMMARY 2.6.2 Exceptions - The VAX architecture recognizes six classes of exceptions. exception class instances --------------- --------- arithmetic traps/faults integer overflow trap integer divide by zero trap subscript range trap floating overflow fault floating divide by zero fault floating underflow fault memory management exceptions access control violation fault translation not valid fault operand reference exceptions reserved addressing mode fault reserved operand fault or abort instruction execution exceptions reserved/privileged instruction fault emulated instruction fault customer reserved instruction fault breakpoint fault ---------------------------------------------------------------- tracing exception trace fault system failure exceptions machine check abort (including read/write bus and parity errors, cache parity errors, and CFPA protocol errors) kernel stack not valid abort interrupt stack not valid abort CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 38 ARCHITECTURE SUMMARY 2.6.3 System Control Block (SCB) - The System Control Block (SCB) is a page aligned table containing the vectors for servicing interrupts and exceptions. The SCB is pointed to by the System Control Block Base Register (SCBB). 3 3 2 1 0 9 9 8 0 +---+-----------------------------------------+-----------------+ |MBZ| physical longword address of SCB | MBZ | :SCBB +---+-----------------------------------------------------------+ The System Control Block format: vector name type #param notes ------ ---- ---- ------ ----- 00 passive release interrupt 0 not generated by the CVAX CPU chip 04 machine check abort 4 parameters depend upon error type 08 kernel stack not valid abort 0 must be serviced on interrupt stack 0C power fail interrupt 0 IPL is raised to 1E 10 reserved/privileged fault 0 instruction 14 customer reserved instruction fault 0 XFC instruction 18 reserved operand fault/ 0 not always recoverable abort 1C reserved addressing mode fault 0 20 access control violation fault 2 parameters are virtual address, status code 24 translation not valid fault 2 parameters are virtual address, status code 28 trace pending (TP) fault 0 2C breakpoint instruction fault 0 30 unused - - compatibility mode in VAX 34 arithmetic trap/ 1 parameter is type code fault 38-3C unused - - - 40 CHMK trap 1 parameter is sign-extended operand word 44 CHME trap 1 parameter is sign-extended operand word CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 39 ARCHITECTURE SUMMARY 48 CHMS trap 1 parameter is sign-extended operand word 4C CHMU trap 1 parameter is sign-extended operand word 50 unused - - - 54 corrected read data interrupt 0 IPL is 1A (CRD L) 58-5C unused - - - 60 memory error interrupt 0 IPL is 1D (MEMERR L) 64-80 unused - - - 84 software level 1 interrupt 0 88 software level 2 interrupt 0 ordinarily used for AST delivery 8C software level 3 interrupt 0 ordinarily used for process scheduling 90-BC software levels 4-15 interrupt 0 C0 interval timer interrupt 0 IPL is 16 (INTTIM L) C4 unused - - - C8 emulation start fault 10 same mode exception, FPD = 0: parameters are opcode, PC, specifiers CC emulation continue fault 0 same mode exception, FPD = 1: no parameters D0-FC unused - - - 100-1FC adapter vectors interrupt 0 200-FFFC device vectors interrupt 0 Vectors in the range of 100-FFFC are used to directly vector interrupts from the external bus. The SCBB vector index is determined from bits <15:2> of the value supplied by external hardware. The new PSL priority level is determined by either the external interrupt request level that caused the interrupt or by bit <0> of the value supplied by external hardware. If bit<0> is 0, the new IPL level is determined by the interrupt request level being serviced. IRQ<3> sets the IPL to 17 (hex); IRQ<2>, 16 (hex); IRQ<1>, 15 (hex); and IRQ<0>, 14 (hex). If bit<0> of the value supplied by external hardware is 1, then the new IPL is forced to 17 (hex). The ability to force the IPL to 17 (hex) supports an external bus, such as the Q-Bus, that can not guarantee that the device generating the SCBB vector index is the device that originally requested the interrupt. For example, the Q-Bus has four separate interrupt request signals that correspond to IRQ<3:0> but only one signal to daisy chain the interrupt grant. Furthermore, devices on the Q-Bus are ordered so that higher priority devices are electrically closer CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 40 ARCHITECTURE SUMMARY to the bus master. If an IRQ<1> is being serviced, there is no guarantee that a higher priority device will not intercept the grant. Software must determine the level of the device that was serviced and set the IPL to the correct value. Only device vectors in the range of 100 to FFFC (hex) should be used, except by devices emulating console storage and terminal hardware. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 41 ARCHITECTURE SUMMARY 2.6.4 Machine Check Parameters - A machine check occurs as a result of a serious microcode and hardware error conditions including memory subsystem errors. These conditions are: - CFPA protocol error - Impossible situations in memory management - Unused IPL requests - Impossible situations in the microcode - Bus (memory) errors - Multiple errors 2.6.4.1 Types Of Errors - 2.6.4.1.1 CFPA Protocol Error - The CFPA checks for proper ordering of requests from the CPU. If the CFPA detects a protocol violation, a machine check occurs. param meaning ----- ------- 1 CFPA protocol error 2 CFPA reserved instruction 3 CFPA unknown error 4 CFPA unknown error All CFPA protocol error machine checks are NON-RECOVERABLE. The error should be logged, and the currently running process (or the operating system) terminated. 2.6.4.1.2 Impossible Situations In Memory Management - The CVAX CPU does some checking for impossible conditions in the memory management microflows. If an impossible situation is detected, a machine check occurs. param meaning ----- ------- 5 The calculated virtual address for a Process PTE is in P0 space (TB miss flows) 6 The calculated virtual address for a Process PTE is in P1 space (TB miss flows) CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 42 ARCHITECTURE SUMMARY 7 The calculated virtual address for a Process PTE is in P0 space (M = 0 flows) 8 The calculated virtual address for a Process PTE is in P1 space (M = 0 flows) All impossible memory management machine checks are NON-RECOVERABLE. The error should be logged, and the currently running process (or the operating system) terminated. The current memory management registers (P0BR, P1BR, SBR, P0LR, P1LR, SLR) should also be logged. 2.6.4.1.3 Unused IPL Request - The CVAX CPU uses 13 of the 16 hardware interrupt priority levels (IPLs) defined in the VAX architecture. If the interrupt controller requests an interrupt at an unused hardware IPL, a machine check occurs. param meaning ----- ------- 9 The interrupt controller returned an interrupting IPL of 18, 19, or 1B The unused IPL machine check is NON-RECOVERABLE. The error should be logged. A non-vectored interrupt representing a serious error (corrected read data, memory error, power fail, or processor halt) has probably been lost. The operating system should be terminated. 2.6.4.1.4 Impossible Situations In The Microcode - Due to size constraints, erroneous branches in the microcode will usually result in the execution of random microinstruction. However, a few cases are trapped out. If the microcode detects an impossible situation, a machine check occurs. param meaning ----- ------- A MOVC3 or MOVC5 in impossible state (not move forward, move backward, or fill) The impossible microcode machine check is NON-RECOVERABLE. The error should be logged, and the currently running process (or the operating system) terminated. 2.6.4.1.5 Bus (Memory) Errors - If external logic asserts ERR L in response to any memory cycle other than an instruction prefetch or interrupt acknowledge, a CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 43 ARCHITECTURE SUMMARY machine check occurs. param meaning ----- ------- 80 read bus error, normal read 81 read bus error, SPTE, PCB, or SCB read 82 write bus error, normal write 83 write bus error, SPTE or PCB write The bus (memory) error machine checks MAY be recoverable, depending on the error code, the VAX CANT RESTART, and FPD flags in the machine check stack frame, as shown in the following table: error VAX CANT RESTART FPD action --------+-------------------------------+-------------- 80,81 | 0 X | restartable | 1 0 | non-recoverable | 1 1 | restartable | | 82,83 | X X | non-recoverable In addition, bus (memory) error machine checks that are restartable from the chip's point of view may be non-recoverable for system reasons (eg, a read lock may be outstanding). CONSULT THE VARIOUS SYSTEM SPECIFICATIONS FOR FURTHER DETAILS. On a non-recoverable error, the error should be logged, and the currently running process (or the operating system) should be terminated. 2.6.4.1.6 Multiple Errors - If the CVAX CPU encounters nested serious errors (e.g., kernel stack not valid inside a machine check), or other conditions which cannot be processed by macrocode (e.g., HALT instruction in kernel mode), the microcode places the current PC in IPR[SAVEPC], the current PSL, MAPEN, and a restart code in IPR[SAVEPSL], and executes a processor restart. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 44 ARCHITECTURE SUMMARY 2.6.4.2 Machine Check Processing - The microcode process for machine check is the same for all cases. If any exception is in progress, a processor restart occurs. Otherwise, the current instruction is packed up (MOVC3, MOVC5, POLYf) or unwound. The microcode sets the serious error flag and performs machine check exception processing through SCB vector 4. Note that the exception is always processed on the interrupt stack. The following parameters are pushed on the stack: +-------------------------------------------------------+ | byte count (00000010 hex) | :SP +-------------------------------------------------------+ | machine check code | +-------------------------------------------------------+ | most recent memory address | +-------------------------------------------------------+ | internal state information 1 | +-------------------------------------------------------+ | internal state information 2 | +-------------------------------------------------------+ | PC | +-------------------------------------------------------+ | PSL | +-------------------------------------------------------+ The parameters are: machine check code (hex): 1 = CFPA protocol error 2 = CFPA reserved instruction 3 = CFPA unknown error 4 = CFPA unknown error 5 = process PTE in P0 space (TB miss) 6 = process PTE in P1 space (TB miss) 7 = process PTE in P0 space (M = 0) 8 = process PTE in P1 space (M = 0) 9 = undefined interrupt ID code A = impossible microcode state (MOVCx) 80 = read bus error, normal read 81 = read bus error, SPTE, PCB, or SCB read 82 = write bus error, normal write 83 = write bus error, SPTE or PCB write most recent memory address: <31:0> = current contents of VAP register internal state information 1: <31:24> = current contents of OPCODE<7:0> <23:20> = 1110 <19:16> = current contents of HSIR<3:0> <15:8> = current contents of CADR<7:0> CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 45 ARCHITECTURE SUMMARY <7:0> = current contents of MSER<7:0> internal state information 2: <31:24> = current contents of SC<7:0> <23:22> = 11 <21:16> = current contents of STATE<5:0> <15> = current contents of VAX CANT RESTART bit <14:12> = 111 <11:8> = current ALU condition codes <7:0> = delta PC at time of exception PC: <31:0> = PC of start of current instruction PSL: <31:0> = current contents of PSL When exception processing is complete, the serious error flag is cleared, and the next instruction is decoded. 2.6.4.3 Processor Restart - If the hardware or kernel software environment becomes severely corrupted, the chip may be unable to continue normal processing. In these instances, the chip executes a processor restart and passes control to recovery code beginning at physical address 20040000 (hex). IPR[SAVEPC] contains the previous PC, IPR[SAVEPSL] contains the previous PSL with MAPEN in bit<15>, a valid stack flag in bit<14>, and a restart code in bits <13:8>. The restart codes are as follows: code condition ---- --------- 2 HALT L asserted 3 initial power on 4 interrupt stack not valid during exception 5 machine check during normal exception 6 HALT instruction executed in kernel mode 7 SCB vector bits<1:0> = 11 8 SCB vector bits<1:0> = 10 A CHMx executed while on interrupt stack 10 ACV or TNV during machine check exception 11 ACV or TNV during kernel stack not valid exception 12 machine check during machine check exception 13 machine check during kernel stack not valid exception 19 PSL<26:24> = 101 during interrupt or exception 1A PSL<26:24> = 110 during interrupt or exception 1B PSL<26:24> = 111 during interrupt or exception 1D PSL<26:24> = 101 during REI 1E PSL<26:24> = 110 during REI 1F PSL<26:24> = 111 during REI A processor restart sets the state of the chip as follows: IPR[SAVEPC] = saved PC CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 46 ARCHITECTURE SUMMARY IPR[SAVEPSL] = saved PSL<31:16,7:0> in <31:16,7:0> saved MAPEN<0> in <15> valid stack flag in <14> saved restart code in <13:8> SP = interrupt stack pointer PSL = 041F0000 (hex) PC = 20040000 (hex) MAPEN = 0 SISR = 0 (powerup only) ASTLVL = 4 (powerup only) ICCS = 0 (powerup only) MSER = 0 (powerup only) CADR = 0 (powerup only) all else = undefined CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 47 ARCHITECTURE SUMMARY 2.7 Process Structure A process is a single thread of execution. The context of the current process is contained in the Process Control Block (PCB). The PCB is pointed to by the Process Control Block Base register (PCBB). 3 3 2 1 0 9 2 1 0 +---+-------------------------------------------------------+---+ |MBZ| physical longword address of PCB |MBZ| :PCBB +---+-------------------------------------------------------+---+ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 48 ARCHITECTURE SUMMARY 2.7.1 Process Control Block (PCB) - 3 1 0 +---------------------------------------------------------------+ | KSP | :PCB +---------------------------------------------------------------+ | ESP | +4 +---------------------------------------------------------------+ | SSP | +8 +---------------------------------------------------------------+ | USP | +12 +---------------------------------------------------------------+ | R0 | +16 +---------------------------------------------------------------+ | R1 | +20 +---------------------------------------------------------------+ | R2 | +24 +---------------------------------------------------------------+ | R3 | +28 +---------------------------------------------------------------+ | R4 | +32 +---------------------------------------------------------------+ | R5 | +36 +---------------------------------------------------------------+ | R6 | +40 +---------------------------------------------------------------+ | R7 | +44 +---------------------------------------------------------------+ | R8 | +48 +---------------------------------------------------------------+ | R9 | +52 +---------------------------------------------------------------+ | R10 | +56 +---------------------------------------------------------------+ | R11 | +60 +---------------------------------------------------------------+ | AP(R12) | +64 +---------------------------------------------------------------+ | FP(R13) | +68 +---------------------------------------------------------------+ | PC | +72 +---------------------------------------------------------------+ | PSL | +76 +---------------------------------------------------------------+ | P0BR | +80 +---------+-----+---+-------------------------------------------+ | | AST | | | +84 | MBZ | LVL |MBZ| P0LR | +---------+-----+---+-------------------------------------------+ | P1BR | +88 +-+-----------------+-------------------------------------------+ |P| | | +92 |M| MBZ | P1LR | |E| | | +-+-------------------------------------------------------------+ CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 49 ARCHITECTURE SUMMARY Note: The PME field is unused. CMOS-2 CVAX CPU ENGINEERING SPECIFICATION (Company Confidential) Page 50 ARCHITECTURE SUMMARY 2.8 Processor Registers Each of the processor registers listed in the table below falls into one of the following categories: 1 = implemented by the CVAX CPU Chip as specified in the VAX Architecture Standard (DEC Standard 032) 2 = implemented by the CVAX CPU Chip uniquely 3 = passed to external logic via an external processor register cycle; if not implemented externally, read as zero, nopped on write 4 = access not allowed (reserved operand fault) The column labeled "INIT?" means is this register initialized in the CVAX on chip power-up microcode. YES = it is initialized by power-up code NO = it is NOT initialized by power-up code but IS valid --- = register contents are undefined after power-up Number Register Name Mnemonic Type Scope Init? Category ------ ------------- -------- ---- ----- ----- -------- 0 Kernel Stack Pointer KSP rw proc -- 1 1 Executive Stack Pointer ESP rw proc -- 1 2 Supervisor Stack Pointer SSP rw proc -- 1 3 User Stack Pointer USP rw proc -- 1 4 Interrupt Stack Pointer ISP rw cpu -- 1 5 not implemented -- -- -- -- 3 6 not implemented -- -- -- -- 3 7 not implemented -- -- -- -- 3 8 P0 Base Register P0BR rw proc -- 1 9 P0 Length Register P0LR rw proc -- 1 10 P1 Base Register P1BR rw proc -- 1 11 P1 Length Register P1LR rw proc -- 1 12 System Base Register SBR rw cpu -- 1 13 System Length Register SLR rw cpu -- 1 14 not implemented -- -- -- -- 3 15 not implemented -- -- -- -- 3 16 Process Control Block Base PCBB rw proc -- 1 17 System Control Block Base SCBB rw cpu -- 1 18 Interrupt Priority Level