MicroVAX CPU CHIP DESIGN SPECIFICATION DC 333 (21-20887-01) Rev. 3.02 (WORKING DRAFT) C O M P A N Y C O N F I D E N T I A L Copyright (C) 1982, 1983, 1984, 1985 by Digital Equipment Corporation The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may occur in this document. This specification does not describe any program or product which is currently available from Digital Equipment Corporation. Nor does Digital Equipment Corporation commit to implement this specification in any product or program. Digital Equipment Corporation makes no commitment that this document accurately describes any product it might ever make. MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 2 TABLE OF CONTENTS 09 Jan 85 1.0 INTRODUCTION . . . . . . . . . . . . . . . . . . . 10 1.1 Scope . . . . . . . . . . . . . . . . . . . . . 10 1.2 Applicable Documents . . . . . . . . . . . . . . 10 1.3 MicroVAX CPU Chip Features . . . . . . . . . . . 10 1.4 MicroVAX CPU Chip Sections . . . . . . . . . . . 11 1.4.1 Instruction (I) Box . . . . . . . . . . . . . 11 1.4.2 Execution (E) Box . . . . . . . . . . . . . . 11 1.4.3 Memory (M) Box . . . . . . . . . . . . . . . . 11 1.4.4 DAL Interface . . . . . . . . . . . . . . . . 12 1.4.5 Microsequencer . . . . . . . . . . . . . . . . 12 1.4.6 Interrupts . . . . . . . . . . . . . . . . . . 12 1.4.7 Control Store . . . . . . . . . . . . . . . . 12 1.4.8 Clock Logic . . . . . . . . . . . . . . . . . 12 1.5 Block Diagram . . . . . . . . . . . . . . . . . 13 2.0 INSTRUCTION (I) BOX . . . . . . . . . . . . . . . 15 2.1 Prefetcher . . . . . . . . . . . . . . . . . . . 15 2.1.1 Prefetcher Data Path . . . . . . . . . . . . . 15 2.1.1.1 Instruction Prefetch Stack . . . . . . . . . 16 2.1.1.2 Instruction Byte Rotator . . . . . . . . . . 16 2.1.1.3 Instruction Data (ID) Register . . . . . . . 16 2.1.2 Prefetch Controller . . . . . . . . . . . . . 17 2.2 The Instruction PLA (IPLA) . . . . . . . . . . . 18 2.2.1 IPLA Reducer . . . . . . . . . . . . . . . . . 19 2.3 Microaddress Generator . . . . . . . . . . . . . 20 2.3.1 Initial Instruction Decode (IID) Branch . . . 20 2.3.1.1 IID Exception Dispatch . . . . . . . . . . . 21 2.3.1.2 IID Opcode Dispatch . . . . . . . . . . . . 21 2.3.1.3 Specifier Dispatches . . . . . . . . . . . . 22 2.3.2 Next Specifier Decode . . . . . . . . . . . . 23 2.3.3 Specifer Decode . . . . . . . . . . . . . . . 24 2.3.4 Delta PC Logic . . . . . . . . . . . . . . . . 24 2.4 Miscellaneous Functions . . . . . . . . . . . . 25 2.4.1 Opcode And FD Bit Register . . . . . . . . . . 25 2.4.2 Register Number Latch (RN) . . . . . . . . . . 25 2.4.3 RMODE . . . . . . . . . . . . . . . . . . . . 26 2.4.4 FPU Present . . . . . . . . . . . . . . . . . 26 2.4.5 VAX Trap Request . . . . . . . . . . . . . . . 27 2.4.6 Specifier Counter . . . . . . . . . . . . . . 27 2.4.7 Data Length And Access Type . . . . . . . . . 27 2.4.8 PSL Bits . . . . . . . . . . . . . . . . . . . 28 2.4.9 Execution_Started . . . . . . . . . . . . . . 28 2.5 I Box Related Microinstructions . . . . . . . . 28 2.6 Tables . . . . . . . . . . . . . . . . . . . . . 31 2.6.1 Fork Type Decode . . . . . . . . . . . . . . . 31 2.6.2 Execution Dispatch Masks . . . . . . . . . . . 31 2.6.3 Karnaugh Maps Of Opcodes . . . . . . . . . . . 32 2.7 Block Diagram . . . . . . . . . . . . . . . . . 38 3.0 EXECUTION (E) BOX . . . . . . . . . . . . . . . . 41 3.1 Register File . . . . . . . . . . . . . . . . . 41 3.1.1 General Purpose Registers (GPR[0:E]) . . . . . 41 3.1.2 Temporary Registers (T[0:B]) . . . . . . . . . 42 3.1.3 Working Registers (WR[0:6]) . . . . . . . . . 42 3.1.4 Functional Summary . . . . . . . . . . . . . . 42 MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 3 TABLE OF CONTENTS 09 Jan 85 3.1.4.1 BASIC Source And Destination Control Field, CS<32:28> . . . . . . . . . . . . . . . . . 43 3.1.4.2 CONSTANT Source And Destination Control Field, CS<31:29> . . . . . . . . . . . . . . 44 3.1.4.3 SHIFT Source And Destination Control Field, CS<30:27> . . . . . . . . . . . . . . . . . 44 3.1.4.4 MXPR Source And Destination Control Field, CS<25:23> . . . . . . . . . . . . . . . . . 44 3.1.4.5 MEM REQ Source And Destination Control Field, CS<25:23> . . . . . . . . . . . . . . . . . 45 3.1.4.6 FBOX XFER Source And Destination Control Field, CS<24:23> . . . . . . . . . . . . . . 45 3.1.4.7 SPECIAL MISC2 Control Field, CS<27:23> . . . 45 3.1.4.8 SPARE Function Control Field, CS<32:28> . . 45 3.1.4.9 MISC Control Field, CS<22:18> . . . . . . . 46 3.1.5 Microcode Restrictions . . . . . . . . . . . . 46 3.2 PC Logic . . . . . . . . . . . . . . . . . . . . 47 3.2.1 PC Register . . . . . . . . . . . . . . . . . 47 3.2.2 PC Adder . . . . . . . . . . . . . . . . . . . 47 3.2.3 BPC Register . . . . . . . . . . . . . . . . . 47 3.2.4 Microcode Restrictions . . . . . . . . . . . . 48 3.3 K Mux . . . . . . . . . . . . . . . . . . . . . 49 3.3.1 K(DL) . . . . . . . . . . . . . . . . . . . . 49 3.3.2 Constant Generator . . . . . . . . . . . . . . 49 3.3.3 Zero Extension . . . . . . . . . . . . . . . . 49 3.3.4 Addressing/Other Constants . . . . . . . . . . 50 3.3.5 Microcode Restrictions . . . . . . . . . . . . 50 3.4 SC (Shift Counter) . . . . . . . . . . . . . . . 51 3.4.1 Functional Summary . . . . . . . . . . . . . . 51 3.4.2 Microcode Restrictions . . . . . . . . . . . . 52 3.5 ALU . . . . . . . . . . . . . . . . . . . . . . 53 3.5.1 Functional Summary . . . . . . . . . . . . . . 53 3.5.1.1 Operation Control . . . . . . . . . . . . . 53 3.5.1.1.1 BASIC ALU Control . . . . . . . . . . . . 53 3.5.1.1.2 CONSTANT ALU Control . . . . . . . . . . . 54 3.5.1.1.3 SPARE ALU Control . . . . . . . . . . . . 55 3.5.1.1.4 SHIFT ALU Control . . . . . . . . . . . . 55 3.5.1.1.5 MEM REQ, SPECIAL, FBOX XFER, MXPR ALU Control . . . . . . . . . . . . . . . . . 55 3.5.1.2 Immediate ALU Condition Codes . . . . . . . 55 3.5.2 Microcode Restrictions . . . . . . . . . . . . 56 3.6 Shifter . . . . . . . . . . . . . . . . . . . . 57 3.6.1 Functional Summary . . . . . . . . . . . . . . 57 3.6.2 Microcode Restrictions . . . . . . . . . . . . 58 3.7 Condition Code Logic . . . . . . . . . . . . . . 59 3.7.1 ALU CC Register . . . . . . . . . . . . . . . 59 3.7.2 PSL CC Logic . . . . . . . . . . . . . . . . . 60 3.7.3 CC Map . . . . . . . . . . . . . . . . . . . . 60 3.7.4 Branch Test Logic . . . . . . . . . . . . . . 61 3.7.5 Microcode Restrictions . . . . . . . . . . . . 62 3.8 RLOG . . . . . . . . . . . . . . . . . . . . . . 64 3.8.1 Microcode Restrictions . . . . . . . . . . . . 64 3.9 STATE . . . . . . . . . . . . . . . . . . . . . 65 3.9.1 Microcode Restrictions . . . . . . . . . . . . 66 MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 4 TABLE OF CONTENTS 09 Jan 85 3.10 Summary Of E Box Microcode Restrictions . . . . 67 3.10.1 Register File . . . . . . . . . . . . . . . . 67 3.10.2 PC Logic . . . . . . . . . . . . . . . . . . . 67 3.10.3 K Mux . . . . . . . . . . . . . . . . . . . . 67 3.10.4 SC Logic . . . . . . . . . . . . . . . . . . . 67 3.10.5 ALU . . . . . . . . . . . . . . . . . . . . . 68 3.10.6 Shifter . . . . . . . . . . . . . . . . . . . 68 3.10.7 CC Logic . . . . . . . . . . . . . . . . . . . 68 3.10.8 RLOG . . . . . . . . . . . . . . . . . . . . . 69 3.10.9 State . . . . . . . . . . . . . . . . . . . . 69 3.11 Block Diagrams . . . . . . . . . . . . . . . . . 70 4.0 MEMORY (M) BOX . . . . . . . . . . . . . . . . . . 75 4.1 M Box Overview . . . . . . . . . . . . . . . . . 75 4.1.1 Introduction . . . . . . . . . . . . . . . . . 75 4.1.2 Microinstruction Control Of The M Box . . . . 75 4.1.2.1 Memory Requests . . . . . . . . . . . . . . 76 4.1.2.1.1 Microcode Restrictions . . . . . . . . . . 77 4.1.2.1.2 Virtual References . . . . . . . . . . . . 78 4.1.2.1.2.1 Read Virtual . . . . . . . . . . . . . 78 4.1.2.1.2.2 Read Virtual (AT) Check . . . . . . . . 78 4.1.2.1.2.3 Read Virtual Write Check . . . . . . . 78 4.1.2.1.2.4 Read Virtual Write Check Lock . . . . . 78 4.1.2.1.2.5 Read (VA') . . . . . . . . . . . . . . 79 4.1.2.1.2.6 Write Virtual . . . . . . . . . . . . . 79 4.1.2.1.2.7 Write Virtual Unlock . . . . . . . . . 79 4.1.2.1.2.8 Write (VA') . . . . . . . . . . . . . . 79 4.1.2.1.3 Physical References . . . . . . . . . . . 79 4.1.2.1.3.1 Read Physical . . . . . . . . . . . . . 79 4.1.2.1.3.2 Write Physical . . . . . . . . . . . . 79 4.1.2.1.3.3 Read Physical (VA') . . . . . . . . . . 80 4.1.2.1.3.4 Write Physical (VA') . . . . . . . . . . 80 4.1.2.1.4 Kernel References . . . . . . . . . . . . 80 4.1.2.1.5 Probe References . . . . . . . . . . . . . 80 4.1.2.1.6 Read PTE References . . . . . . . . . . . 80 4.1.2.1.7 Read Interrupt Vector . . . . . . . . . . 81 4.1.2.2 Non Memory Request Microinstructions . . . . 81 4.1.3 Translation Buffer Description . . . . . . . . 81 4.1.4 Microcode Flows . . . . . . . . . . . . . . . 82 4.1.4.1 Longword References . . . . . . . . . . . . 83 4.1.4.2 Memory References That Use DL . . . . . . . 84 4.1.5 Registers . . . . . . . . . . . . . . . . . . 85 4.2 Function Descriptions . . . . . . . . . . . . . 87 4.2.1 Memory Address Logic . . . . . . . . . . . . 87 4.2.1.1 VA (Virtual Address) Register . . . . . . . 87 4.2.1.2 VA' (VA Prime) Register . . . . . . . . . . 87 4.2.1.3 VIBA (Virtual Instruction Buffer Address) Register . . . . . . . . . . . . . . . . . . 88 4.2.1.4 VA Adder . . . . . . . . . . . . . . . . . . 88 4.2.2 TB . . . . . . . . . . . . . . . . . . . . . . 88 4.2.2.1 PTEs . . . . . . . . . . . . . . . . . . . . 89 4.2.2.2 LRU . . . . . . . . . . . . . . . . . . . . 91 4.2.2.3 TB Data Path . . . . . . . . . . . . . . . . 91 4.2.2.3.1 I Stream Access . . . . . . . . . . . . . 91 4.2.2.3.1.1 I Stream TB Hit . . . . . . . . . . . . 92 MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 5 TABLE OF CONTENTS 09 Jan 85 4.2.2.3.1.2 I Stream TB Miss . . . . . . . . . . . . 92 4.2.2.3.2 D Stream Access . . . . . . . . . . . . . 92 4.2.2.3.2.1 D Stream TB Hit . . . . . . . . . . . . 92 4.2.2.3.2.2 TB Miss . . . . . . . . . . . . . . . . 92 4.2.2.3.3 TB Data Formatting . . . . . . . . . . . . 93 4.2.2.3.3.1 TB Bypasses . . . . . . . . . . . . . . 93 4.2.2.3.3.2 TB Accesses . . . . . . . . . . . . . . 93 4.2.2.4 TB Fills From Memory . . . . . . . . . . . . 93 4.2.2.5 TB Invalidate Logic . . . . . . . . . . . . 93 4.2.2.6 TB Miss Logic . . . . . . . . . . . . . . . 94 4.2.2.7 TB Summary . . . . . . . . . . . . . . . . . 94 4.2.3 Access Logic . . . . . . . . . . . . . . . . . 96 4.2.3.1 Privilege Check Logic . . . . . . . . . . . 96 4.2.3.2 Length Check Logic . . . . . . . . . . . . . 96 4.2.3.3 Inhibit IB Fill Logic . . . . . . . . . . . 97 4.2.3.4 Memory Management Case Status Register Logic 97 4.2.3.5 MBOX Case Status Register . . . . . . . . . 98 4.2.3.6 Bus Error Case Status Register . . . . . . . 98 4.2.4 Memory Management Microtrap Logic . . . . . . 98 4.2.4.1 Partial PSL Logic . . . . . . . . . . . . . 99 4.2.4.2 Cross Page Detection Logic . . . . . . . . . 99 4.2.4.3 Microtrap And Abort Determination Logic . . 99 4.2.5 Memory Management Controller . . . . . . . . . 101 4.2.5.1 Trap Disable Logic . . . . . . . . . . . . . 101 4.2.5.2 Reexecute Reference Logic . . . . . . . . . 101 4.2.5.3 REPROBE Flag . . . . . . . . . . . . . . . . 102 4.2.5.4 Memory Management Enable Logic . . . . . . . 102 4.2.6 Second DAL Cycle Detection Logic . . . . . . . 102 4.2.6.1 REQ_2ND_REF Logic . . . . . . . . . . . . . 103 4.2.7 Memory Data Size Control Logic . . . . . . . . 103 4.3 Block Diagram . . . . . . . . . . . . . . . . . 104 5.0 DAL INTERFACE . . . . . . . . . . . . . . . . . . 106 5.1 DAL State Sequencer . . . . . . . . . . . . . . 106 5.1.1 States Of The State Sequencer . . . . . . . . 107 5.1.2 DAL State Sequencer Outputs . . . . . . . . . 107 5.1.2.1 CS_UPDATE And PHW_EN . . . . . . . . . . . . 107 5.1.2.2 I Stream . . . . . . . . . . . . . . . . . 108 5.1.2.3 Unaligned References . . . . . . . . . . . . 108 5.2 BUSARB Circuitry . . . . . . . . . . . . . . . . 109 5.3 Off-Chip Control . . . . . . . . . . . . . . . . 110 5.3.1 Byte Mask Logic . . . . . . . . . . . . . . . 111 5.3.2 Control Status Signals . . . . . . . . . . . . 111 5.3.3 Asynchronous Inputs . . . . . . . . . . . . . 112 5.3.4 Timing Of Internal Signals . . . . . . . . . . 113 5.3.4.1 CPU Read And Write Cycles . . . . . . . . . 113 5.3.4.1.1 Aligned Read . . . . . . . . . . . . . . . 114 5.3.4.1.2 Aligned Write . . . . . . . . . . . . . . 114 5.3.4.1.3 Unaligned Read . . . . . . . . . . . . . . 115 5.3.4.1.3.1 First Bus Cycle . . . . . . . . . . . . 115 5.3.4.1.3.2 Second Bus Cycle . . . . . . . . . . . . 115 5.3.4.1.4 Unaligned Write . . . . . . . . . . . . . 116 5.3.4.1.4.1 First Bus Cycle . . . . . . . . . . . . 116 5.3.4.1.4.2 Second Bus Cycle . . . . . . . . . . . . 116 5.3.4.2 FPU XFER Chip Signals . . . . . . . . . . . 117 MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 6 TABLE OF CONTENTS 09 Jan 85 5.3.4.2.1 FPU XFER Read . . . . . . . . . . . . . . 117 5.3.4.2.2 FPU XFER Write . . . . . . . . . . . . . . 117 5.3.4.3 MXPR Chip Signals . . . . . . . . . . . . . 118 5.3.4.4 MicroVAX Response To FPU Assertion Of CS<2> L . . . . . . . . . . . . . . . . . . . . . 118 5.4 On-Chip Control . . . . . . . . . . . . . . . . 119 5.4.1 IDAL And DAL Pad Control . . . . . . . . . . . 119 5.4.2 Data Latches Control . . . . . . . . . . . . . 120 5.4.3 Rotators And Data Multiplexer Control . . . . 120 5.4.4 Zero Extender Control . . . . . . . . . . . . 121 5.5 Test Control . . . . . . . . . . . . . . . . . . 121 5.6 Block Diagram . . . . . . . . . . . . . . . . . 124 6.0 MICROSEQUENCER . . . . . . . . . . . . . . . . . . 126 6.1 Overview . . . . . . . . . . . . . . . . . . . . 126 6.1.1 Busses . . . . . . . . . . . . . . . . . . . . 126 6.1.1.1 Microaddress Bus (MAB) <10:0> . . . . . . . 126 6.1.1.2 Internal Microaddress Bus (IMAB) <10:0> . . 127 6.1.1.3 Next Address Bus (NAB) <10:1> . . . . . . . 127 6.1.1.4 Jump Next Address Bus (JMPNA) <10:0> . . . . 127 6.1.1.5 Microtest Bus (uTest) <3:0> . . . . . . . . 127 6.1.1.6 Internal Microinstruction Bus (IMIB) <38:0> 127 6.1.2 Logic Components . . . . . . . . . . . . . . . 128 6.1.2.1 Microsubroutine Stack (uStack) [0:7] <10:0> 128 6.1.2.2 Adder . . . . . . . . . . . . . . . . . . . 128 6.1.2.3 Microprogram Counter (uPC) <10:0> . . . . . 128 6.1.2.4 Jump Control . . . . . . . . . . . . . . . . 129 6.1.2.5 OR Box . . . . . . . . . . . . . . . . . . . 129 6.1.2.6 MAB Mux . . . . . . . . . . . . . . . . . . 129 6.1.2.7 MAB Latch . . . . . . . . . . . . . . . . . 129 6.1.2.8 MAB Reducer . . . . . . . . . . . . . . . . 129 6.1.2.9 Control Logic . . . . . . . . . . . . . . . 129 6.1.3 Timing Summary . . . . . . . . . . . . . . . . 130 6.2 Functional Description . . . . . . . . . . . . . 131 6.2.1 Microsequencer Control Interpretation . . . . 131 6.2.1.1 Branch Format . . . . . . . . . . . . . . . 131 6.2.1.1.1 Branch Offset (BO) <6:0> . . . . . . . . . 131 6.2.1.1.2 Branch Condition Select (BCS) <12:7> . . . 131 6.2.1.1.2.1 Relative Branch . . . . . . . . . . . . 132 6.2.1.1.2.2 Microtrap . . . . . . . . . . . . . . . 132 6.2.1.1.2.3 Case . . . . . . . . . . . . . . . . . . 132 6.2.1.1.2.4 Stack Branch . . . . . . . . . . . . . . 132 6.2.1.1.3 Branch Condition Chart Summary . . . . . . 133 6.2.1.2 Jump Format . . . . . . . . . . . . . . . . 135 6.2.1.2.1 Subroutine Control Bit (SB) <12> . . . . 135 6.2.1.2.2 Jump Address Field <10:0> . . . . . . . . 136 6.2.1.3 Miscellaneous Field (MISC) <22:18> . . . . . 136 6.2.2 Microtrap Mechanism . . . . . . . . . . . . . 136 6.2.3 Test Mode . . . . . . . . . . . . . . . . . . 137 6.3 Block Diagram . . . . . . . . . . . . . . . . . 138 7.0 INTERRUPT LOGIC . . . . . . . . . . . . . . . . . 140 7.1 Interrupt Latches . . . . . . . . . . . . . . . 140 7.2 Interrupt Priority Encoder . . . . . . . . . . 141 7.3 Interrupt IPL And Comparator . . . . . . . . . . 141 7.4 Microcode Notes . . . . . . . . . . . . . . . . 142 MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 7 TABLE OF CONTENTS 09 Jan 85 7.5 Block Diagram . . . . . . . . . . . . . . . . . 143 8.0 CONTROL STORE . . . . . . . . . . . . . . . . . . 144 8.1 Functional Summary . . . . . . . . . . . . . . . 144 8.2 Block Diagram . . . . . . . . . . . . . . . . . 145 9.0 CLOCK LOGIC . . . . . . . . . . . . . . . . . . . 146 9.1 Clock Input Buffer . . . . . . . . . . . . . . . 146 9.2 RESET L Input Buffer . . . . . . . . . . . . . . 146 9.3 Reset Synchronizer . . . . . . . . . . . . . . . 146 9.4 Divide-By-Two Logic . . . . . . . . . . . . . . 147 9.5 20MHz Clock Drivers . . . . . . . . . . . . . . 147 9.6 Phase Generators . . . . . . . . . . . . . . . . 147 9.7 Reset Logic . . . . . . . . . . . . . . . . . . 147 9.8 20 MHz Clock Out Circuitry . . . . . . . . . . . 147 9.9 Block Diagram . . . . . . . . . . . . . . . . . 148 10.0 CONTROL FIELDS SUMMARY . . . . . . . . . . . . . . 149 10.1 Data Path Control Formats . . . . . . . . . . . 149 10.2 Microsequencer Control Formats . . . . . . . . . 150 10.3 Data Path Register Addressing . . . . . . . . . 151 10.4 BASIC Microinstruction . . . . . . . . . . . . . 153 10.4.1 BASIC Function Field CS<37:33> . . . . . . . . 153 10.4.2 BASIC Source And Destination Control Field CS<32:28> . . . . . . . . . . . . . . . . . . 154 10.5 General Fields . . . . . . . . . . . . . . . . . 155 10.5.1 CC Field CS<27:26> . . . . . . . . . . . . . . 155 10.5.2 B Field (B_Bus Address) CS<25:23> . . . . . . 155 10.5.3 Miscellaneous Field CS<22:18> . . . . . . . . 155 10.5.4 A Field (A_Bus Address) CS<17:14> . . . . . . 156 10.6 CONSTANT Microinstruction . . . . . . . . . . . 157 10.6.1 ALU Control Field CS<36:34> . . . . . . . . . 157 10.6.2 KFMT, KPOS, And KBYTE Fields CS<33:32,28:27,25:18> . . . . . . . . . . . . 157 10.6.3 CONSTANT Source And Destination Field CS<31:29> . . . . . . . . . . . . . . . . . . 158 10.6.4 CC (Condition Code Control) Field CS<26> . . . 158 10.7 SHIFT Microinstruction . . . . . . . . . . . . . 159 10.7.1 SHF VAL (Shift Value) CS<35:31> . . . . . . . 159 10.7.2 SHIFT Source And Destination CS<31:29> . . . . 159 10.7.3 CC (Condition Code Control) Field CS<26> . . . 160 10.8 MXPR (Move To/From Processor Register) Microinstruction . . . . . . . . . . . . . . . 161 10.8.1 REG ADDR (Register Address) CS<34:29> . . . . 161 10.8.2 RD (Read/Write Control) CS<28> . . . . . . . . 161 10.8.3 MXPR Source And Destination CS<25:23> . . . . 162 10.8.4 MXPR CC Field CS<26> . . . . . . . . . . . . . 162 10.9 MEM REQ (Memory Request) Microinstruction . . . 163 10.9.1 MEM FUNC (Memory/Bus Function) CS<32:28> . . . 163 10.9.2 FF (F Box Flag) Field CS<27> . . . . . . . . . 164 10.9.3 CC (PSL Condition Code Control) Field CS<26> . 164 10.9.4 MEM REQ Source And Destination CS<25:23> . . . 165 10.10 FBOX XFER Microinstruction . . . . . . . . . . . 166 10.10.1 FBOX OP (FPU Operation) Field CS<31:28> . . . 166 10.10.2 RD Field CS<25> . . . . . . . . . . . . . . . 166 10.10.3 FBOX XFER Source And Destination Control Field CS<24:23> . . . . . . . . . . . . . . . . . . 166 MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 8 TABLE OF CONTENTS 09 Jan 85 10.11 FBOX EXEC Microinstruction . . . . . . . . . . . 167 10.12 SPECIAL Microinstruction . . . . . . . . . . . . 168 10.13 SPARE Microinstruction . . . . . . . . . . . . . 169 10.13.1 SPARE Function Field CS<32:28> . . . . . . . . 169 10.14 BRANCH Microinstruction . . . . . . . . . . . . 170 10.14.1 BCS (Branch Condition Select) Field CS<12:7> . 170 10.14.2 BO (Branch Offset) Field CS<6:0> . . . . . . . 171 10.15 JUMP Microinstruction . . . . . . . . . . . . . 172 10.15.1 SB (SUBROUTINE) Control Bit CS<12> . . . . . . 172 10.15.2 JUMP ADDRESS Field CS<11:0> . . . . . . . . . 172 MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 9 REVISION HISTORY 09 Jan 85 REVISION HISTORY ---------------- REV DATE REASON --- ---- ------ 3.02 WORKING DRAFT Pass 3 PG/LR updates. 3.01 Jul, 1984 Pass 2 PG updates. 3.00 Jan, 1984 Pass 1 PG updates. 2.00 May, 1983 New memory management. 1.02 Jan, 1983 Updates. 1.01 Dec, 1982 Updates. 1.00 Oct, 1982 Initial release. MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 10 INTRODUCTION 09 Jan 85 1.0 INTRODUCTION 1.1 Scope This document describes the MicroVAX CPU chip, a MOS/VLSI chip that implements a subset VAX compatible central processor. This specification describes the internal organization and operation of the chip. It does not describe the external interface and behavior of the chip. For further information, the applicable documents should be consulted. 1.2 Applicable Documents VAX Architecture Standard (DEC Standard 032) MicroVAX CPU Chip Engineering Specification MicroVAX FPU Chip Engineering Specification MicroVAX FPU Chip Design Specification 1.3 MicroVAX CPU Chip Features The MicroVAX CPU chip is a 32-bit, virtual memory microprocessor. Implemented in ZMOS (double metal NMOS), the MicroVAX CPU chip is a high performance, low cost CPU for single board computers, single user workstations, low end systems, and other applications that do not need the flexibility of, or cannot afford the complexity of, the full VAX architecture. Its key features are: 1. Subset VAX data types. The MicroVAX CPU chip supports the following subset of the VAX data types: byte, word, longword, quadword, character string, and variable length bit field. Support for f_floating, d_floating, and g_floating is available via an external floating point unit. Support for the remaining VAX data types can be provided by macrocode emulation. 2. Subset VAX instruction set. The MicroVAX CPU chip implements the following subset of the VAX instruction set: integer and logical, address, variable length bit field, control, procedure call, miscellaneous, queue, MOVC3/MOVC5, and operating system support. Floating point is implemented via an external floating point unit. The remaining VAX instructions can be implemented via macrocode emulation (the MicroVAX CPU chip provides microcode assists for the emulation of the character string, decimal string, EDITPC, and CRC instructions). 3. Full VAX memory management. The MicroVAX CPU chip includes a demand paged memory management unit which is fully compatible with VAX memory management. System space addresses are virtually mapped through single level page tables, process space addresses through double level page tables. MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 11 INTRODUCTION 09 Jan 85 4. Industry standard external interface. The MicroVAX CPU chip's external interface is a 32-bit extension of the industry standard microprocessor interface. The MicroVAX CPU chip can be easily interfaced to industry peripheral chips from Motorola, National, and other vendors. 5. Large virtual and physical address space. The MicroVAX CPU chip supports four gigabytes (2**32) of virtual memory, and one gigabyte (2**30) of physical memory. 6. High performance. At its maximum frequency, the MicroVAX CPU chip achieves a 200 nsec microcycle and a 400 nsec I/O cycle. 7. Single package. The MicroVAX CPU chip is packaged in a standard 68-pin surface mounted chip carrier and requires no special clock generator or support chips. 1.4 MicroVAX CPU Chip Sections The MicroVAX CPU chip is composed of the following sections. 1.4.1 Instruction (I) Box - The Instruction (I) Box contains the instruction buffer, initial decode PLA, and associated logic. It prefetches the instruction stream, generates microprogram addresses, and provides instruction data to the E Box. 1.4.2 Execution (E) Box - The Execution (E) Box contains the VAX general registers, microcode working registers, ALU, shifter, and other facilities for the efficient emulation of the MicroVAX instruction set. 1.4.3 Memory (M) Box - The Memory (M) Box contains the translation buffer, length check registers, and associated logic. It converts program generated virtual addresses to physical addresses, when necessary, and handles translation exceptions. MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 12 INTRODUCTION 09 Jan 85 1.4.4 DAL Interface - The DAL Interface connects the active chip logic to the external environment. It includes the incoming and outgoing data latches, rotators, and swappers, the pin signal generation logic, and the external operation control sequencer. 1.4.5 Microsequencer - The Microsequencer determines the address of the next microword to be fetched and executed from the Control Store. It also oversees the generation and execution of microtraps. 1.4.6 Interrupts - The Interrupt logic mediates hardware interrupt requests against the current IPL and generates an interrupt request to the I Box, if necessary. 1.4.7 Control Store - The Control Store contains 1600 x 39 words of microcode which direct all operations in the chip. 1.4.8 Clock Logic - The clock logic converts an external, double frequency clock reference into the internal phase clocks required by the chip logic. MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 13 INTRODUCTION 09 Jan 85 1.5 Block Diagram MicroVAX CPU Chip Block Diagram HALT PWRFL INTTIM IRQ<3:0> | | | | | | | | .---V-------V-------V-------V---. | | .---------------------IID_IRQ------------------+ | | | Interrupts | | .-----------------FPD_IRQ------------------+ | | | | | | | `-----------^-------^-----------' | | | | | | .------AW_BUS<20:16>--------' | | | | | .----IDAL<31:0>----. | | | .-------IMIB<38:14>---------' | | | | | | | .--------------V-------V---V--. | | .-------------------------------. | | +--IMAB<10:0>-----------|-------|-------> | | | | | | | | | | <--IMIB<38:7>-----------|-------+-------> | | | | | | | | | | <--UTEST_BUS<3:0>-------|---+---|-------> | | | I Box | | | | | Microsequencer | | | <--AW_BUS<4:0>----------+ | | | | | | | | | | | | | | +--AT<1:0>----------. | | | | | | | | | | | | | | | | +--DL<2:0>--. | | | | | | | `--+---+---+---+---+---+---^--' | | | | | `----------------+--------------' | | | | | | | | | | | | | | | | | | | | | | | | | | | | I M B R D I O P | | A U I M D A N E I P C | | W T M A A P B ^ L D C ^ | | E I B L U 3 T ^ O 1 | | B S B ^ ^ C S : A 0 D : | | U T ^ 1 3 O ^ 0 V E 0 | | S 3 0 1 D 3 V P | ^ V | | ^ B 8 : : E 1 | C | 8 | | | 3 U : 0 0 ^ : | ^ | : | | | 1 S 0 V V 2 0 | 2 | 0 | | | : ^ V | | : V | : | V | | | 0 3 | | | 0 | | 0 | | | | | V : | | | V | | V | | | | | | 0 | | | | | | | | | | | | | V | | | | | | | | | | | | | | | | | .--V---V---V---V---V---V---+--. | | | | | .---------------V---------------. | | <--DL<2:0>--+ | | | | | | | | | | | | | | | | | | <--FORCE_LONG---+ | | | | | | | | | | | | | | | | | MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 14 INTRODUCTION 09 Jan 85 | | E Box <--AW_BUS<31:0>-|---|---+ | |<-------+ Control Store | | | | | | | | | | | | | | <--UTEST_BUS<3:0>---|---|---+ | | | | | | | | | | | | | | | | <--IMIB<38:7>---|---|---|---|---+ | | | `--------------+--------------' | | | | | | `-------------------------------' | | | | | | | | | | | | | | | | | STATE<1:0> | | | | | | PHASE CLOCKS, IRESET* | | | | | | | | ^ ^ ^ ^ ^ ^ ^ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | .--------------V--------------. | | | | | | .---+---+---+---+---+---+---+---. | | <--DL<2:0>--' | | | | | | | | | | | | | | | | | | | +--FORCE_LONG---' | | | | | <--- CLKI | | | | | | | | | | | <--AT<1:0>----------' | | | | <--- RESET | | M Box | | | | | Clock Generator | | | <--AW_BUS<31:0>---------' | | | <--- TEST | | | | | | | | | <--UTEST_BUS<3:0>-----------' | | +--> CLKO | | | | | | | | <--IMIB<38:7>-------------------' | | | `------+---------------+------' `-------------------------------' | | | | IDAL<31:0> DAL_CTL | | | PHW_EN* * = global signal, routed to most sections `----------+ | ^ | | | | | | .------V---------------V---------------+---------------------------------------------------------------. | | | | | DAL Interface | | | | | `-+--------+--------+--------+--------+--------+--------+--------+--------^--------+--------^--------^-' | | | | | | | | | | | | | | | | | | | | | | | | V V V V V V V V | V | | DAL<31:0> AS DS WR DBE CS<2:0> BM<3:0> EPS DMR DMG RDY ERR MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 15 INSTRUCTION (I) BOX 09 Jan 85 2.0 INSTRUCTION (I) BOX The I Box handles instruction prefetching and the sequencing of instruction execution. The sequencing begins when the Initial Instruction Decode (IID) signal is given in the microinstruction (specifically, by the IID codes in the Branch Condition Select (BCS) field). This signal causes the I Box to examine the opcode and first specifier of the new macroinstruction and drive the Next Address Bus (NAB) with a microaddress to start the microprogram for the instruction. If the instruction has specifiers, the microaddress is based on the mode of the first specifier, and will take the microcode directly to the First Specifier Decode (FSD) routines. If there are no specifiers, execution flows for the instruction are entered immediately. The FSD flows end with a microinstruction that issues a Next Specifier Decode (NSD) command, again with codes in the BCS field. The I Box again forces an address that starts up microprograms for decoding the second specifier or for executing the instruction. Following Second Specifier Decode (SSD), the I Box provides the microaddress for the instruction's execution flows. If there are further specifiers to be decoded after the execution flows for an instruction have been entered, a SPEC DECODE command is issued in the MISC field of a microinstruction. In response to this, the I Box drives NAB<4:1> with a value based on the mode of the next specifier, and the rest of the microaddress is provided by the same microinstruction's JUMP address field. The microcode thus addressed decodes the next specifier and ends with a RETURN (in the BCS field) to the execution flows from which it was called. When the execution of an instruction is completed, its final microinstruction issues an IID to start the next instruction. While the chip is executing one instruction, the I Box tries to fetch the next ones using free cycles on the DAL. If there are branches in the program flow, the prefetched instructions are thrown away. If for any reason the data has not come in by the time the I Box needs it, the I Box forces a branch in the microprogram flow. The microcode then loops until the data comes in, or goes off to memory management flows. The I Box has four main parts: the Prefetcher, the IPLA, the Microaddress Generator, and miscellaneous registers and control. 2.1 Prefetcher The Prefetcher has two sections, the Data Path and the Controller. 2.1.1 Prefetcher Data Path - The I Box Prefetcher Data Path handles the actual macroinstructions. It buffers the prefetched longwords from memory, rotates the instructions to bring the opcode to the front, and stores literals and displacements for the E Box. It is controlled by the Prefetch Controller and consists of MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 16 INSTRUCTION (I) BOX 09 Jan 85 the following blocks. 2.1.1.1 Instruction Prefetch Stack - The Instruction Prefetch Stack consists of two longword registers, each corresponding to an aligned longword in memory. The registers comprise a two-entry FIFO stack or queue. Data is loaded into the end of the queue from the the IDAL and stored in whichever empty register is closest to the head of the queue. If the entire queue is empty the data is loaded into the first register; if the first register contains valid data, the data on the IDAL goes into the second register. When a full longword has been removed from the head of the queue, the contents of the second register move into the first. 2.1.1.2 Instruction Byte Rotator - The Instruction Byte Rotator can select up to four contiguous bytes in the Prefetch Stack (for example, an opcode, a specifier, and two bytes of data) starting at any byte in the lowest longword. The position of the starting byte is specified by the IB Pointer. 2.1.1.3 Instruction Data (ID) Register - This four-byte register is the mechanism by which the E Box data path is passed data from the instruction stream (displacements, literals, etc.). Data is loaded from the Byte Rotator, either automatically by the I Box or explicitly by the microinstruction MISC field, and sign extended to longword in the same cycle it is loaded. The ID register is automatically loaded by the I Box when: o The I Box Microaddress Generator detects that the opcode is a branch instruction. The ID register is loaded with the byte or word branch displacement. o The Microaddress Generator detects that the specifier is a short literal (i.e. the specifier mode nibble is 0-3). The specifier itself, containing the operand, is loaded. o The Microaddress Generator detects that the specifier mode is byte or word displacement (specifier mode A, B, C, or D). The following bytes, containing the byte or word displacement, are loaded. Explicit loads of the ID register are accomplished by the microinstruction MISC field commands LOAD ID (with the data length based on the Data Length register) and LOAD ID LONG (with the data length forced to LONG). Longword displacements (for specifier modes E and F) are always loaded using an explicit MISC field command, because the Byte Rotator cannot provide the specifier byte and four bytes of data in the same cycle. MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 17 INSTRUCTION (I) BOX 09 Jan 85 The I Box drives two bits on the Next Address Bus (NAB) to indicate whether an ID register load was successful. NAB<2> NAB<1> ------ ------ 0 0 load was successful 1 0 not enough bytes in stack, prefetching not halted 1 1 not enough bytes in stack, prefetching halted The other bits of the microaddress are unaffected. Jumps and branches can be done by the same microinstruction as a LOAD ID, but the final addresses must be allocated allowing for the I Box to drive NAB<2:1>. The ID register is read by the E Box as Miscellaneous Register MR[3]. 2.1.2 Prefetch Controller - The DAL Interface must decide, based on information from the I Box, whether to fetch I Stream data for the Prefetch Stack when there is no D Stream access in progress. If prefetching has not been halted and at least one longword is invalid or expected to become invalid during the current microcycle, the Prefetch Controller will signal the DAL Interface that it wants I Stream data by asserting the IB_REQ line. If the I Stream read results in a TB miss or there is some other problem with the PTE, the Hardware Prefetch Halt Bit is set and no more prefetching is done. This is done to prevent prefetching from interfering with memory management operations. When the Prefetch Stack eventually runs out of valid data, a special microaddress is forced onto the NAB; a microcode routine then handles the problem. The I Box does not react immediately to a prefetching error because the prefetched data may not be used. The Hardware Prefetch Halt Bit is cleared by the RESTART PREFETCH MISC field, and as a side effect of the BCS fields that load VIBA and PC. The microcode can also explicitly stop prefetching by setting the Microcode Prefetch Halt Bit in the I Box. This is a different bit from the Hardware Prefetch Halt Bit. This microcode-controllable bit can be set and cleared by the MISC field commands DISABLE PREFETCH and ENABLE PREFETCH. It is also cleared by the RESTART PREFETCH MISC field, and as a side effect of the BCS fields that load VIBA and PC. A microinstruction with DISABLE PREFETCH in the MISC field and LOAD VIBA AND PC in the BCS field results in the microcode halt bit being set and the hardware halt bit being cleared. A two bit register called the IB Pointer is kept to point to the next valid byte in the lowest longword of the Prefetch Stack. As data is drawn out of the stack by the Microaddress Generator, this pointer is incremented by Delta PC. When the macroinstruction stream branches, nothing in the stack is usable. It is flushed as a side effect of the BCS branches that load VIBA and PC. Prefetching is started up again, and the IB Pointer is set pointing to the start of the new instruction (i.e. bits <1:0> of the PC). MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 18 INSTRUCTION (I) BOX 09 Jan 85 2.2 The Instruction PLA (IPLA) The IPLA parses the opcode. It has as inputs the eight-bit opcode and a ninth bit called XFD, set by hardware if the previous opcode was FD (meaning that this is a two byte opcode). From this information, the IPLA generates the following 23 bits of data: 18 17 16 15 14 13 12 11 10 9 8 7 +-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ |F Box| PSL Map Code |Data Length|Data Length|Access Type|Access Type| |Instr| | spec 1 | spec 2 | spec 1 | spec 2 | +-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 6 5 4 3 2 1 0 +-----+-----+-----+-----+-----+-----+-----+ | Fork Code | Execution | Dis | FPD | | |Dispatch Control |VTrap|Illeg| +-----+-----+-----+-----+-----+-----+-----+ <18> The F Box Instruction bit is true if the opcode is for an F, D, or G floating point instruction. If this bit is true and there is no FPU present, an illegal opcode trap is taken. The microcode also tests this bit during the decode of short literal mode specifiers and, if set, rearranges the literal into floating point format. <17:15> The PSL Map Code bits tell the E Box how to set the PSL condition code bits for the current opcode. <14:7> The IPLA has a multiplexor on some of its outputs. This mux selects one of the two Data Length fields and one of the two Access Type fields, depending upon which specifier is being evaluated. This data is loaded into the AT/DL Register during IID and NSD microcycles. <6:5> The Fork Code is an encoding of the Fork Types, which control the next microaddress sent out at NSD. (The codes are detailed in the Tables section.) If the Fork Type is S then the microcode will go to routines that decode the second specifier. If O then the hardware will detect if the second specifier is register mode and if so will go directly to execution flows (optimize), since no specifier decoding needs to be done. This saves a cycle in many instructions. If E then the microcode goes unconditionally to execution flows. The Fork Type I is used to denote an illegal opcode. Since many illegal opcodes do not have IPLA terms, the Fork Code bits default to the code for Fork Type I. <4:2> The Execution Dispatch Control outputs from the IPLA are sent to the Microaddress Generator where they are used to form a mask that is ANDed with the opcode to produce a microaddress for the instruction's execution flows. Through the use of these masks, different macroinstructions can share the same microcode. If the instructions need to be separated further down the flow, there is a microbranch provided that cases on MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 19 INSTRUCTION (I) BOX 09 Jan 85 the bottom four bits of the opcode. See the Tables section for the specific masks used. <1:0> The last two bits are for the two microtraps asserted by the I Box: optimized integer overflow microtrap and trap on illegal opcode. The traps are asserted at the start of a macroinstruction, in the cycle following a executed IID (ie, IID AND PHI_WRITE). The integer overflow trap exists so that the microcode does not have to waste two cycles checking to see if an arithmetic operation has overflowed. Instead a trap is taken the cycle after the end of the instruction if: o the V bit (overflow) in the PSL is set, and o the IV bit (overflow trap enable) in the PSL is set, and o the IPLA disable overflow trap bit is not asserted for this opcode. The disable overflow trap bit defaults to being set to prevent undecoded (i.e. illegal) opcodes from taking overflow traps. The end of an instruction execution is indicated by IID AND PHI_WRITE. If the IID takes an exceptional branch like an interrupt the integer overflow trap will still be asserted. However, if an exception like a page fault occurs during the instruction, then microcode can clear any pending overflow traps with the SPECIAL MISC3 instruction CLEAR VAX TRAP REQUEST. An illegal opcode trap occurs if the instruction is a floating point type and there is no FPU present in the system, if the Fork Code bits from the IPLA indicate an illegal opcode (Fork Type I), or if the FPD Illegal bit from the IPLA is asserted and the First Part Done bit in the PSL is also set. Unlike the overflow trap, the illegal opcode trap will not be asserted if IID takes an exceptional branch like an interrupt. The IPLA has 72 terms and an access time of 100 ns. 2.2.1 IPLA Reducer - For testability, there is a reducer at the outputs of the IPLA. The reducer uses an XOR and shift combination to checksum the IPLA during test mode. The shift out is routed to the M Box and conditionally driven on Control Status pin CS<2>. MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 20 INSTRUCTION (I) BOX 09 Jan 85 2.3 Microaddress Generator The Microaddress Generator produces microaddresses for entering the microcode flows at various stages of a macroinstruction. The microaddresses may be generated at four times: during IID, during NSD, during SPEC DECODE, and during LOAD ID operations. 2.3.1 Initial Instruction Decode (IID) Branch - The IID branch is described in three parts: exceptions/traps/interrupts pending, opcode dispatch, and specifier dispatch. An IID command is given at the end of an instruction routine. It causes a microcode dispatch based on the next opcode. It is encoded into several of the microbranch commands, and may be conditional. Its use spans two microcycles, the microinstruction fetch cycle and the execute cycle: T0 T50 T100 T150 T200 T400 fetch |-------+-------+-------+-------| | | | T250 T300 T350 | execute | |-------+-------+-------+-------| ccccccccccccccccc bbbbbbbbbbb aaaaaaaaaaaaaaaaa ^ ^ ^ ^ | | | | last last last E Box start, last E Box end, uAddr out uInst in first uAddr out first uInst in ccc - Control Store fetch, 100 ns, T50 to T150 of fetch cycle bbb - IID branch decision, 50 ns, T160 of fetch cycle to T25 of execute cycle aaa - E Box execution, 100 ns, T50 to T150 of execute cycle At time T50 the address for the last microinstruction of a macroinstruction execution sequence is sent to the Control Store. The microinstruction, which includes the code for the final E Box operation as well as the IID branch code, is driven by the Control Store beginning at T150 and is valid at the I Box Decoder at about T160. The IID branch decision is made at time bbb above, before the E Box operation is executed at time aaa. If the branch condition is true (that is, this actually is the last E Box operation required for the current macroinstruction), the I Box produces the microaddress for the first microinstruction of the routine for the next macroinstruction, which is sent to the Control Store at T250. From T250 to T350 the last E Box operation of the previous macroinstruction is being executed while the first microinstruction of the next macroinstruction is being fetched. In subsequent microcycles, other branches (NSD to SSD or Execute, or SPEC DECODE) can be made based on bits in the IPLA. The IPLA bits arrive at about T375, too late to control the IID branch calculation. Illegal opcodes are detected by having no IPLA row selected, or by the IPLA F Box Instruction output being true when the FPU Present bit is clear, or by the IPLA FPD output being true when PSL is set. Since these are not determined until T375 (after IID), illegal opcodes generate a microtrap during the execute cycle after IID. MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 21 INSTRUCTION (I) BOX 09 Jan 85 2.3.1.1 IID Exception Dispatch - These exceptional conditions are examined at IID. They force special microaddresses and cause the opcode to be ignored. VAX |INTERRUPT|PSL|Prefetch| IB || uADDR ARITH | PENDING | | Halted | DRY || (hex) TRAP REQ| | | | || (MISC3) | | | | || --------+---------+-------+--------+-------++-------- 1 | x | x | x | x || 114 arith trap 0 | 1 | x | x | x || 10E interrupt 0 | 0 | 1 | x | x || 10C trace trap pending 0 | 0 | 0 | 1 | x || 106 prefetch halted, not enough bytes in stack 0 | 0 | 0 | 0 | 1 || 104 prefetch not halted, not enough bytes in stack The arithmetic trap bit is set and cleared by SPECIAL microinstructions. MICROCODE NOTE An IID and SET VAX TRAP may not be done in the same microinstruction; nor may an IID and CLEAR VAX TRAP. Also, a SET VAX TRAP or CLEAR VAX TRAP microinstruction may not be followed immediately by an IID. Interrupts are signalled by the Interrupt Logic over the IID_IRQ line. Trace trap pending is a bit in the PSL indicating that a debugging trap is to be taken. Prefetching is halted by problems that prevent determining if an instruction read from a page is allowed, e.g., TB miss or TB hit with Access Violation or Translation Not Valid. Any of the exceptions will disable the illegal opcode microtrap. There are four IB.DRY locations reachable from IID: 104 and 106, and 144 and 146 within FSD. 104 and 106 are the only ones used at IID, while 144 and 146 are used when the FSD flows are called by SPEC DECODE. 2.3.1.2 IID Opcode Dispatch - If there are no exceptions pending at IID, an address based on the opcode is driven out: MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 22 INSTRUCTION (I) BOX 09 Jan 85 PSL | IB[PC] <7:0> || uADDR | || (hex) -------+-------+--------++-------- 0 | 0000 0xxx || 130..13E zero specifiers HALT..SVPCTX 0 | 00x1 0000 || 124 BSBB..BSBW 0 | 00x1 0001 || 120 BRB..BRW 0 | 0001 001x || 120 BNEQ..BEQL 0 | 0001 010x || 120 BGTR..BLEQ 0 | 0001 1xxx || 120 BGEQ..BCS 0 | 1111 1100 || 128 XFC x | 1111 1101 || 12A XFD 1 | not FD (hex) || 12C 0 | xxxx xxxx || 140..15E all others go to FSD, using SPEC MAP(IB[PC+1]) The SPEC MAP bits come from logic that operates on the specifier. The offsets are given in the section on Specifier Dispatches. If the opcode loaded at IID is FD (hex), the microcode performs a second IID, which picks up the second byte of the opcode and dispatches either to FSD or to one of the IB.DRY locations. The first IID (when IB[PC]=FD) sets the 9-bit opcode register to 0FD and adds 1 to the PC. The second IID sets the 9-bit opcode register to 1xx, where xx is the second opcode byte and increments PC by 1 to 4, if it does not go to IB.DRY. If the second IID does go to IB.DRY, it leaves the opcode at 0FD, and leaves the PC unchanged. The first IID sets the Backup PC (BPC) equal to the PC; the second one does not change it. If a page fault occurs after parsing the FD, but before picking up the second opcode byte and first specifier, the microcode backs out of the instruction in the normal way, backing up PC to be BPC, i.e. pointing at the FD again. Instructions without specifiers go immediately to execute flows, while those with specifiers go to First Specifier Decode (FSD). 2.3.1.3 Specifier Dispatches - Specifier dispatches cause 16-way cases in the microcode flow. Some of them also do a jump to fixed locations. FSD does its case starting at a base address of 140; Second Specifier Decode (an NSD with a fork type of S) cases at 180. The MISC field SPEC DECODE does its case at whatever base address the JUMP field specifies. The same mapping for microaddress bits <4:1> is used with all bases. MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 23 INSTRUCTION (I) BOX 09 Jan 85 SPEC MAP |NAB<4:1>|NAB<4:1>| Delta PC (add one Specifier<7:4> | (hex) | (hex) | for IID.FSD to skip (hex) | R=0..E | R=F | over opcode too) ----------------+--------+--------+------------------------------------------------ 0,1,2,3 | 0 | 0 | 1 S^# 4 | 1 | 7 | 1 * [R] [PC] illegal dry, not halted | 2 | 2 | 0 stack dry, prefetching not halted dry and halted | 3 | 3 | 0 stack dry, prefetching halted 5 | 5 | 7 | 1 R PC illegal 6 | 6 | 7 | 1 (R) (PC) illegal 7 | 8 | 7 | 1 -(R) -(PC) illegal 8 | 9 | 4 | 1 (R)+ (PC)+ 9 | A | B | 1 @(R)+ @(PC)+ A,C | C | C | 2,3 D(R) D(PC) E | D | D | 1 ** D(R) D(R) longword B,D | E | E | 2,3 @D(R) @D(PC) F | F | F | 1 ** @D(R) @D(R) longword * The index mode prefix is treated as a one-byte specifier. The embedded specifier is parsed (and PC incremented, etc.) by a microcode SPEC DECODE. ** The Byte Rotator cannot pull off a longword displacement and a specifier at the same time. The displacement for the E and F specifiers must be obtained with a subsequent LOAD ID command. 2.3.2 Next Specifier Decode - The NSD signal comes from a number of codes in the Branch Condition Select field of the microinstruction. In executing these forks, the Microaddress Generator examines the Fork Type information from the IPLA and the current specifier. ----------------+-----+--------------------------------+-----------+ Fork Type | FT | Next Address Bus | Address | |Label|10 9 8 7 6 5 4 3 2 1 0| Range | ----------------+-----+--+--+--+--+--+--+--+--+--+--+--+-----------+ SSD | S | 0| 0| 1| 1| 0| 0| SPEC MAP | 0| 180 - 19E | ----------------+-----+--+--+--+--+--+--+--+--+--+--+--+-----------+ Optimizations | O | 1| 0| EXECUTION ADDRESS | 0| 400 - 5FE | ----------------+-----+--+--+--+--+--+--+--+--+--+--+--+-----------+ Execute | E | 0| 1| EXECUTION ADDRESS | 0| 200 - 3FE | ----------------+-----+--+--+--+--+--+--+--+--+--+--+--+-----------+ The Execution Address is derived from the nine-bit opcode and the three-bit Execution Dispatch Control code from the IPLA. The Execution Dispatch Control code is decoded by a simple logic network to generate an eight-bit mask. Opcode<8> is OR'ed into Opcode<5> and the eight-bit result is AND'ed with the mask to form the eight execution dispatch address bits. The Optimizations are for instructions with register mode specifiers. Because these do not need to go through a specifier decode microroutine, MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 24 INSTRUCTION (I) BOX 09 Jan 85 they go directly to execution flows. 2.3.3 Specifer Decode - If the MISC field of a microinstruction contains the SPEC DECODE signal, the I Box drives bits <4:1> of the Next Address Bus with the same bit patterns as in the NSD SSD dispatch. (Bit <0> is always 0.) This gives the microcode a case branch on the specifier type. 2.3.4 Delta PC Logic - The Delta PC logic is integrated with the microaddress generation. It generates the three bit value to be added to the PC when the next piece of instruction data is used. Whenever data is not being requested from the Prefetch Stack, it must be zero. Delta PC is used by the PC function of the E Box data path, and by the Prefetch Controller. The controller uses it to increment the IB Pointer that specifies the next byte to be used in the Prefetch Stack. Condition Delta PC -------------------------------- IID forks: Exceptions 0 FPD 1 Opc = Branch byte disp. 2 Opc = Branch word disp. 3 Opc = FD (hex) 1 Zero operand opc. 1 FSD see note NSD forks: SSD see note Optimize 1 Execute 0 SPEC DECODE see note LOAD ID: DL=0 1 DL=1 2 DL=2 4 DL=other 4 LOAD ID LONG: 4 NOTE: In these cases the amount of data taken out of the Prefetch Stack depends on the specifier mode. MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 25 INSTRUCTION (I) BOX 09 Jan 85 Spec Mode Spec Code Delta PC ------------------------------------------- byte disp. A 2 byte disp. deferred B 2 word disp. C 3 word disp. deferred D 3 longword disp. E 1 longword disp. def. F 1 other 0-9 1 If this is an IID fork, delta PC is increased by 1 to account for the opcode. 2.4 Miscellaneous Functions 2.4.1 Opcode And FD Bit Register - The nine-bit Opcode Register holds the opcode for the duration of the macroinstruction execution. It consists of the eight-bit opcode and a ninth bit (called XFD) that indicates an extended opcode (first byte is FD). The Opcode Register is loaded on every IID, and is the opcode input to the IPLA. The XFD bit is loaded from the previous opcode byte on every IID, and cleared as a side effect of the BCS fields that load VIBA and PC. A case branch is provided on the bottom four bits of the opcode. The nine-bit Opcode Register may be read (but not written) when addressed as T[E] by a BASIC microinstruction with Source/Destination code equal to C or E, or by a MEM REQ or FPU XFER microinstruction with Source/Destination code equal to 1. MICROCODE NOTE A read T[E] and an IID may not be done in the same microinstruction. 2.4.2 Register Number Latch (RN) - The Register Number Latch holds the GPR address of the specifier last decoded. It can be operated upon under control of the MISC field or the SPECIAL MISC1 field. It is also used with the RLOG facility in the E Box data path section. When RLOG is pushed, RN supplies four bits of the data that is pushed. When RLOG is popped, RN is loaded from that facility. RN is also loaded during IID, non-execute NSD forks, and SPEC DECODE, with bits <3:0> of the specifier. MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 26 INSTRUCTION (I) BOX 09 Jan 85 MISC Operation ---- ---------------------- 1 RN is incremented by 1 2 RN is decremented by 1 3 RN is loaded from SC 1E RN <- SPEC<3:0> MISC1 Operation ----- ---------------------- 1 RN is loaded from RLOG BCS --- IID RN <- SPEC<3:0> NSD and (FT=SSD or FT=Optimize) RN <- SPEC<3:0> MICROCODE NOTE During execution, it is normal for conflicting commands to be sent from the I Box and microcode. When these cases occur, the I Box-requested operation is executed and the microcode-requested operation is ignored. If, for example, the MISC field says to increment RN, but the Branch Condition Select field says do a Second Specifer Dispatch, then RN will be loaded with the number of the second specifier. 2.4.3 RMODE - This bit indicates that the addressing mode of the specifier under decode is register. It is used at the end of instructions like INC to determine if the destination is a GPR. It is loaded during IID, during NSD if the fork type is not Execute, and during SPEC DECODE. 2.4.4 FPU Present - During power up initialization, the microcode must find out whether the system contains a Floating Point Unit. If so, it will set this bit, and floating point instructions will cause a normal FSD dispatch at IID. If this bit is clear and the IPLA entry for an instruction specifies F Box execution, an illegal opcode microtrap occurs. This bit is also tested by the microcode in CVT Integer to Floating instructions, because these are not identified by the IPLA as floating point instructions but still must trap if no FPU is present. MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 27 INSTRUCTION (I) BOX 09 Jan 85 2.4.5 VAX Trap Request - When the microcode detects an arithmetic exception like integer overflow it can set this bit with the SPECIAL MISC3 microinstruction SET VAX TRAP REQUEST. Then on the next IID a special branch will be forced by the I Box. The handler routine can clear the bit with the SPECIAL MISC3 microinstruction CLEAR VAX TRAP REQUEST. 2.4.6 Specifier Counter - This facility indicates which specifier is presently under decode. It is cleared by IID, and incremented by NSD and SPEC DECODE. It is only used to count the first two specifiers, since the IPLA contains the data lengths, access types, and fork codes for only two specifers. 2.4.7 Data Length And Access Type - The data length and access type of the specifier presently being worked on are kept in the AT/DL register. This register may be read as PR[B] with the access type in bits <4:3> and the data length in bits <2:0>. The access type portion of the AT/DL register may be written in the following ways: o Automatically with a value from the IPLA one cycle after IID or on NSD (for the first two specifiers only). o Explicitly from the AW_Bus, addressed as PR[B]<4:3>. The codes for the access type are: 0 Read Source 1 Modify Source 2 Address Source 3 Field Source The data length portion of the AT/DL register may be written in the following ways: o Automatically with a value from the IPLA one cycle after IID or on NSD (for the first two specifiers only). o Explicitly from the AW_Bus, addressed as PR[B]<2:0>. o Forced by the MISC field. The codes for the data lengths are (bit <2> is always 0): 0 BYTE 1 WORD 2 LONG 3 QUAD MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 28 INSTRUCTION (I) BOX 09 Jan 85 2.4.8 PSL Bits - The following PSL bits are stored in the I Box: < 4> T < 5> IV <27> FPD <30> TP All four bits are loaded by an MXPR write of PSL.HWRE. The T and TP bits may be read as part of PR[C]. MICROCODE NOTE An MXPR write of PSL.HWRE can not occur in the same microinstruction as an IID, nor, if or were changed, can it be immediately followed by an IID microinstruction. 2.4.9 Execution_Started - The Execution_Started flip-flop is set by the I Box when an NSD dispatch to execution flows is made. It is tested by several of the Branch Conditions to cause either a microsubroutine RETURN (if set) or NSD (if clear). This permits the same specifier flows (FSD flows) to be used in decoding an instruction's first specifier and in decoding specifiers encountered after execution flows are entered. The Execution_Started flip-flop is cleared at IID. 2.5 I Box Related Microinstructions In the Source/Destination fields: o The ID register can be read onto the B_Bus as MR[3]. o The AT/DL register can be read to or written from the AW_Bus as PR[B] with AT in bits <4:3> and DL in bits <2:0>. o The PSL TP and T bits can be read to the AW_Bus as PR[C] with TP in bit <30> and T in bit <4>. o The opcode register can be read onto the AW_Bus as T[E]. In the MISC field: MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 29 INSTRUCTION (I) BOX 09 Jan 85 Code Operation Comment -----+-----------------+-------------------------------------------------------- 1 RN <- RN+1 increment RN 2 RN <- RN-1 decrement RN 3 RN <- SC load RN with the bottom four bits of SC B ENABLE PREFETCH clear the microcode Prefetch Halt bit C DISABLE PREFETCH set the microcode Prefetch Halt bit E DL <-- BYTE force data length to BYTE F DL <-- WORD force data length to WORD 14 SPEC DECODE parse a new specifier 15 DL <-- LONG force data length to LONG 16 LOAD ID LONG CASE load the ID register with four bytes from the Prefetch Stack, case if not enough data 17 LOAD ID CASE load ID from the Prefetch Stack, data length based on the DL register, case if not enough data 1B RESTART PREFETCH clear both the hardware and microcode Prefetch Halt bits In the SPECIAL MISC1 field: Code Operation Comment ----+---------------------+-------------------------------------------- 1 POP RLOG pop the top of the RLOG stack into RN and STATE 4 SET FPNT set FPU Present 5 CLR FPNT clear FPU Present In the SPECIAL MISC3 field: Code Operation Comment ----+-----------------------+----------------------------------------- 6 SET VAX TRAP REQUEST set the trap bit for the IID branch 7 CLEAR VAX TRAP REQUEST clear the trap bit for the IID branch In the MXPR ADDR field: Code Operation Comment ----+-----------------------+------------------------------------------------------------------ 28 PSL.HWRE load the PSL bits stored in the I Box (FPD, IV, T, TP) from the AW_Bus MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 30 INSTRUCTION (I) BOX 09 Jan 85 In the Branch Condition Select (BCS) field: Code Operation Comment ----+---------------------------------+--------------------------------------------------------- 1 NO FPD INTERRUPTS PENDING branch if no FPD interrupts pending 5 IF AVMF GOTO IF BWL NSD/RET branch if AT is not read or if instruction is floating point, else if DL is byte, word, or long then if not Execution_Started NSD, else RET 9 NOT FPU branch if FPU Present is clear 1A RMODE branch if last specifier was register mode 24 IF A GOTO IF V OR BWL NSD/RET branch if AT is address, else if AT is variable or DL is byte, word, or long then if not Execution_Started NSD, else RET 25 IF AVM GOTO IF BWL NSD/RET branch if AT is not read, else if DL is byte, word, or long then if not Execution_Started NSD, else RET 26 IF BWL IID ELSE GOTO branch if DL is quad, else IID 29 IF R OR M GOTO branch if AT is read or modify 2A IF BCOND LOAD VIBA&PC ELSE IID branch if BCOND is true and invalidate the Prefetch Stack, else IID 2B SUCCESSIVE IID unconditional IID, ignore exceptions other than IB_DRY 2C NSD/RET NSD if not Execution_Started, else RET 2D IF AV NSD/RET ELSE GOTO branch if AT is read or modify, else if not Execution_Started NSD, else RET 2E IID unconditional IID 2F LOAD VIBA&PC unconditional branch, invalidate Prefetch Stack 36 OPCODE 3-0 case on bottom four bits of opcode 37 DL.MBOX STATUS case on DL and the M Box status bits, with DL in uTest<3:2> and the M Box status in uTest<1:0> 3D RETURN + BO unconditional return plus branch offset MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 31 INSTRUCTION (I) BOX 09 Jan 85 2.6 Tables 2.6.1 Fork Type Decode - This logic derives the Fork Type from the Fork Code and the Specifier Counter, according to the following table. Specifier # ----------- Fork Code 0 1 ------------------------- 0 S E S = Second Spec Decode 1 O E O = Optimize if RMODE, else SSD 2 E X E = Execute 3 I X I = Illegal Opcode Trap 2.6.2 Execution Dispatch Masks - Opcode<8> is OR'd into Opcode<5> and the result is ANDed with one of these masks to produce eight bits of the dispatch address for the NSD Execute fork. Code Mask Comment -----+---------------+---------------------------------------------------------------------------------------- 0 1111 1001 used to force BBCx to BBC, BBSx to BBS 1 1001 1111 used to force ADD{B,W,L}x to ADDBx, SUB{B,W,L}x to SUBBx, etc. 2 1101 1001 used to force ADD{F,D,G}x, SUB{F,D,G}x, MUL{F,D,G}x, DIV{F,D,G}x to ADDFx 3 0001 0000 used to force MOVx, MOVAx, MOVZxL to 10 (hex) 4 0001 0101 used to force PUSHAx, PUSHL to 15 (hex), CLRx to 14 (hex) 5 1111 1111 used for unmodified dispatch 6 1111 1100 used to force CVT{F,D,G}{B,W,L} to CVT{F,D}B, CVT{B,W,L}{F,D,G} to CVTB{F,D} 7 1111 1110 used to consolidate even-odd pairs MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 32 INSTRUCTION (I) BOX 09 Jan 85 2.6.3 Karnaugh Maps Of Opcodes - KARNAUGH MAP OF MicroVAX ONE-BYTE OPCODES 0 1 2 3 4 5 6 7 8 9 A B C D E F ----------------------------------------------------------------------------------------------------------------- 0 |HALT |NOP |REI |BPT |RET |RSB |LDPCTX|SVPCTX|CVTPS |CVTSP |INDEX |CRC |PROBER|PROBEW|INSQUE|REMQUE| ----------------------------------------------------------------------------------------------------------------- 1 |BSBB |BRB |BNEQ |BEQL |BGTR |BLEQ |JSB |JMP |BGEQ |BLSS |BGTRU |BLEQU |BVC |BVS |BCC |BCS | ----------------------------------------------------------------------------------------------------------------- 2 |ADDP4 |ADDP6 |SUBP4 |SUBP6 |CVTPT |MULP |CVTTP |DIVP |MOVC3 |CMPC3 |SCANC |SPANC |MOVC5 |CMPC5 |MOVTC |MOVTUC| ----------------------------------------------------------------------------------------------------------------- 3 |BSBW |BRW |CVTWL |CVTWB |MOVP |CMPP3 |CVTPL |CMPP4 |EDITPC|MATCHC|LOCC |SKPC |MOVZWL|ACBW |MOVAW |PUSHAW| ----------------------------------------------------------------------------------------------------------------- 4 |ADDF2 |ADDF3 |SUBF2 |SUBF3 |MULF2 |MULF3 |DIVF2 |DIVF3 |CVTFB |CVTFW |CVTFL |CVTRFL|CVTBF |CVTWF |CVTLF |ACBF | ----------------------------------------------------------------------------------------------------------------- 5 |MOVF |CMPF |MNEGF |TSTF |EMODF |POLYF |CVTFD | |ADAWI | | | |INSQHI|INSQTI|REMQHI|REMQTI| ----------------------------------------------------------------------------------------------------------------- 6 |ADDD2 |ADDD3 |SUBD2 |SUBD3 |MULD2 |MULD3 |DIVD2 |DIVD3 |CVTDB |CVTDW |CVTDL |CVTRDL|CVTBD |CVTWD |CVTLD |ACBD | ----------------------------------------------------------------------------------------------------------------- 7 |MOVD |CMPD |MNEGD |TSTD |EMODD |POLYD |CVTDF | |ASHL |ASHQ |EMUL |EDIV |CLRQ |MOVQ |MOVAQ |PUSHAQ| ----------------------------------------------------------------------------------------------------------------- 8 |ADDB2 |ADDB3 |SUBB2 |SUBB3 |MULB2 |MULB3 |DIVB2 |DIVB3 |BISB2 |BISB3 |BICB2 |BICB3 |XORB2 |XORB3 |MNEGB |CASEB | ----------------------------------------------------------------------------------------------------------------- 9 |MOVB |CMPB |MCOMB |BITB |CLRB |TSTB |INCB |DECB |CVTBL |CVTBW |MOVZBL|MOVZBW|ROTL |ACBB |MOVAB |PUSHAB| ----------------------------------------------------------------------------------------------------------------- A |ADDW2 |ADDW3 |SUBW2 |SUBW3 |MULW2 |MULW3 |DIVW2 |DIVW3 |BISW2 |BISW3 |BICW2 |BICW3 |XORW2 |XORW3 |MNEGW |CASEW | ----------------------------------------------------------------------------------------------------------------- B |MOVW |CMPW |MCOMW |BITW |CLRW |TSTW |INCW |DECW |BISPSW|BICPSW|POPR |PUSHR |CHMK |CHME |CHMS |CHMU | ----------------------------------------------------------------------------------------------------------------- C |ADDL2 |ADDL3 |SUBL2 |SUBL3 |MULL2 |MULL3 |DIVL2 |DIVL3 |BISL2 |BISL3 |BICL2 |BICL3 |XORL2 |XORL3 |MNEGL |CASEL | ----------------------------------------------------------------------------------------------------------------- D |MOVL |CMPL |MCOML |BITL |CLRL |TSTL |INCL |DECL |ADWC |SBWC |MTPR |MFPR |MOVPSL|PUSHL |MOVAL |PUSHAL| ----------------------------------------------------------------------------------------------------------------- E |BBS |BBC |BBSS |BBCS |BBSC |BBCC |BBSSI |BBCCI |BLBS |BLBC |FFS |FFC |CMPV |CMPZV |EXTV |EXTZV | ----------------------------------------------------------------------------------------------------------------- F |INSV |ACBL |AOBLSS|AOBLEQ|SOBGEQ|SOBGTR|CVTLB |CVTLW |ASHP |CVTLP |CALLG |CALLS |XFC | ** | | | ----------------------------------------------------------------------------------------------------------------- ** TWO-BYTE OPCODE PREFIX MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 33 INSTRUCTION (I) BOX 09 Jan 85 KARNAUGH MAP OF MicroVAX TWO-BYTE OPCODES 0 1 2 3 4 5 6 7 8 9 A B C D E F ----------------------------------------------------------------------------------------------------------------- 0 | | | | | | | | | | | | | | | | | ----------------------------------------------------------------------------------------------------------------- 1 | | | | | | | | | | | | | | | | | ----------------------------------------------------------------------------------------------------------------- 2 | | | | | | | | | | | | | | | | | ----------------------------------------------------------------------------------------------------------------- 3 | | | |CVTGF | | | | | | | | | | | | | ----------------------------------------------------------------------------------------------------------------- 4 |ADDG2 |ADDG3 |SUBG2 |SUBG3 |MULG2 |MULG3 |DIVG2 |DIVG3 |CVTGB |CVTGW |CVTGL |CVTRGL|CVTBG |CVTWG |CVTLG |ACBG | ----------------------------------------------------------------------------------------------------------------- 5 |MOVG |CMPG |MNEGG |TSTG |EMODG |POLYG | | | | | | | | | | | ----------------------------------------------------------------------------------------------------------------- 6 | | | | | | | | | | | | | | | | | ----------------------------------------------------------------------------------------------------------------- 7 | | | | | | | | | | | | | | | | | ----------------------------------------------------------------------------------------------------------------- 8 | | | | | | | | | | | | | | | | | ----------------------------------------------------------------------------------------------------------------- 9 | | | | | | | | | |CVTFG | | | | | | | ----------------------------------------------------------------------------------------------------------------- A | | | | | | | | | | | | | | | | | ----------------------------------------------------------------------------------------------------------------- B | | | | | | | | | | | | | | | | | ----------------------------------------------------------------------------------------------------------------- C | | | | | | | | | | | | | | | | | ----------------------------------------------------------------------------------------------------------------- D | | | | | | | | | | | | | | | | | ----------------------------------------------------------------------------------------------------------------- E | | | | | | | | | | | | | | | | | ----------------------------------------------------------------------------------------------------------------- F | | | | | | | | | | | | | | | | | ----------------------------------------------------------------------------------------------------------------- MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 34 INSTRUCTION (I) BOX 09 Jan 85 IID BRANCH, NO EXCEPTIONS PENDING, ONE-BYTE OPCODE: OPCODE<8> = 0, PSL=0 0 1 2 3 4 5 6 7 8 9 A B C D E F --------------------------------------------------------------------------------- 0 |exe |exe |exe |exe |exe |exe |exe |exe |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd | --------------------------------------------------------------------------------- 1 |bsub|br |br |br |br |br |fsd |fsd |br |br |br |br |br |br |br |br | --------------------------------------------------------------------------------- 2 |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd | --------------------------------------------------------------------------------- 3 |bsub|br |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd | --------------------------------------------------------------------------------- 4 |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd | --------------------------------------------------------------------------------- 5 |fsd |fsd |fsd |fsd |fsd |fsd |fsd | |fsd | | | |fsd |fsd |fsd |fsd | --------------------------------------------------------------------------------- 6 |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd | --------------------------------------------------------------------------------- 7 |fsd |fsd |fsd |fsd |fsd |fsd |fsd | |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd | --------------------------------------------------------------------------------- 8 |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd | --------------------------------------------------------------------------------- 9 |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd | --------------------------------------------------------------------------------- A |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd | --------------------------------------------------------------------------------- B |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd | --------------------------------------------------------------------------------- C |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd | --------------------------------------------------------------------------------- D |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd | --------------------------------------------------------------------------------- E |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd | --------------------------------------------------------------------------------- F |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |FC |FD | | | --------------------------------------------------------------------------------- exe = 130..13E, 8-way opcode branch based on opcode<2:0> br = 120 bsub = 124 FC = 128 FD = 12A fsd = 140..15E, 16-way specifier branch based on IB[PC+1] ___ = don't care. These illegal opcodes will microtrap on the cycle following IID. MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 35 INSTRUCTION (I) BOX 09 Jan 85 IID BRANCH, NO EXCEPTIONS PENDING, TWO-BYTE OPCODE: OPCODE<8> = 1, PSL=0 0 1 2 3 4 5 6 7 8 9 A B C D E F --------------------------------------------------------------------------------- 0 | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- 1 | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- 2 | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- 3 | | | |fsd | | | | | | | | | | | | | --------------------------------------------------------------------------------- 5 |fsd |fsd |fsd |fsd |fsd |fsd | | | | | | | | | | | --------------------------------------------------------------------------------- 4 |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd |fsd | --------------------------------------------------------------------------------- 6 | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- 7 | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- 8 | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- 9 | | | | | | | | | |fsd | | | | | | | --------------------------------------------------------------------------------- A | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- B | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- C | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- D | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- E | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- F | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- fsd = 140..15E, 16-way specifier branch based on IB[PC+1] ___ = don't care. These illegal opcodes will microtrap on the cycle following IID. MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 36 INSTRUCTION (I) BOX 09 Jan 85 IID BRANCH, NO EXCEPTIONS PENDING, ONE-BYTE OPCODE: OPCODE<8> = 0, PSL=1 0 1 2 3 4 5 6 7 8 9 A B C D E F --------------------------------------------------------------------------------- 0 | | | | | | | | |fpdx|fpdx| |fpdx| | | | | --------------------------------------------------------------------------------- 1 | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- 2 |fpdx|fpdx|fpdx|fpdx|fpdx|fpdx|fpdx|fpdx|fpdx|fpdx|fpdx|fpdx|fpdx|fpdx|fpdx|fpdx| --------------------------------------------------------------------------------- 3 | | | | |fpdx|fpdx|fpdx|fpdx|fpdx|fpdx|fpdx|fpdx| | | | | --------------------------------------------------------------------------------- 4 | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- 5 | | | | | |fpdx| | | | | | | | | | | --------------------------------------------------------------------------------- 6 | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- 7 | | | | | |fpdx| | | | | | | | | | | --------------------------------------------------------------------------------- 8 | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- 9 | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- A | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- B | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- C | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- D | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- E | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- F | | | | | | | | |fpdx|fpdx| | |fpdx|FD | | | --------------------------------------------------------------------------------- fpdx = 12C FD = 12A ___ = don't care. These illegal opcodes will microtrap on the cycle following IID. MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 37 INSTRUCTION (I) BOX 09 Jan 85 IID BRANCH, NO EXCEPTIONS PENDING, ONE-BYTE OPCODE: OPCODE<8> = 1, PSL=1 0 1 2 3 4 5 6 7 8 9 A B C D E F --------------------------------------------------------------------------------- 0 | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- 1 | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- 2 | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- 3 | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- 4 | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- 5 | | | | | |fpdx| | | | | | | | | | | --------------------------------------------------------------------------------- 6 | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- 7 | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- 8 | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- 9 | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- A | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- B | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- C | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- D | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- E | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- F | | | | | | | | | | | | | | | | | --------------------------------------------------------------------------------- fpdx = 12C ___ = don't care. These illegal opcodes will microtrap on the cycle following IID. MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 38 INSTRUCTION (I) BOX 09 Jan 85 2.7 Block Diagram I Box Block Diagram to/from Memory and DAL Interfaces from Control Store | | | ^ ^ | | | | | | | | imib<38:7> idal<31:0> | | ib_req | | | | ib_data_present | | kill_fill_if_enop | .-----V-----. | | ibfill_error | | reset | | | | | | | | | | .-V---------V---------V---------+----------+---------V-. | | | <---rd_id-----------------+ | .---------aw_bus<1:0>---> | | | | | <---set_halt(ucode)-------+ | | | Prefetcher | | | | .-b_bus<31:0>---> <---clear_halt(ucode)-----+ | | | | | | | | | | <---clear_halt(hardware)--+ | | | .-------> | | | | | | | <---flush--------+--------+ | | | delta_pc<2:0> `-+------+------^-------^--------^------+------+-----+-' | | | | | | | | | | | | | | | | | | | | ibmux0<7:0> | | | ib_half_dry | | | | | | | | | | ibmux1<7:0> | | | pf_halted | | | | | | | | | |id_length<1:0>| | | valid<1:0> | | | | | | | | | |id_position<1:0>| | | ib_pointer<1:0> | | | | | | | | | | | | | | | | | | | | .-V------V------+-------+--------+------V------V-----V-. | | | | | | | | | | | | | | | <---flush--------' | | to E Box | | | | | | | | | | | +---opcode<8:0>----------->-----------|----opcode---> | | | | | | | | | | | +---map_code<2:0>---------|-----------|-------------> | | | | | | | | | | | <---iid-------------------+ +----iid------> | | | | | | | | | | | <---nsd-------------------+ +----nsd------> | | | | | | | | | | | | | | to uSeq | | | | | | C | | | | | <---gsd-------------------+ O +----gsd------> | | | | | | N | | | | | <---ld_id-----------------+ T +----ld_id----> | | | | | | R | | | | | <---ld_id_long------------+ O | | | | | | | L | | | | | <---bit_ctl<3:0>----------+ | | | | | | | D | | | | | +---fpnt------------------> E | | | | | | | C | | | | | +---xfd-------------------> O | | | | | Microaddress Generator | | D | | | | | and IPLA +---rmode-----------------> E | MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 39 INSTRUCTION (I) BOX 09 Jan 85 | | +-------+ | | R | | | | | +---no_fpu_pres-----------> | from | | delta_pc<2:0> | | | | Interrupt | | | | +---execu_st--------------> | Logic | | | | | | | | | | | +---ib_dry----------------> <----fpd_irq--- | | | | | | | | | | | <---iid_irq---------------|-----------|-------------- | | | | | | | | | | | | | | from E Box | | | | <---psl_tp----------------|-----------|-------------- | | | | | | | | | | | <---psl_v-----------------|-----------|-------------- | | | | | | | | | | | | | | to/from uSeq | | | | +---ov_trap---------------|-----------|-------------> | | | | | | | | | | | +---ill_opc---------------|-----------|-------------> | | | | | | | | | | | +---nab<11:0>-------------|-----------|-------------> | | | | | | | | | | | +----. | <----utest----> | | | `------+-----+-----+-----^-----^---------------^-----+-' | | | | | | | | | | | | | | | | | | | ld_ib_dlat | | psl_fpd | | | | | | to/from | | | | ib_dl<1:0>| | psl_iv | ib_rn<3:0> | | | E Box, | | | | | ib_at<1:0>| | | | spec_valid | | to Memory | | | | | | | | | | | | | Interface | | | .-V-----V-----V-----+-----+-. | | | | | | | | | <---dl<1:0>---+-----|------|-------------------->-----------|----dl<1:0>--> | | | | | | | | | | | | | +---at<1:0>---------|------|-------------------->-----------|----at<1:0>--> | +-------|---b_bus----+ | | | | | | | | <4:0> | <---rd_dl-----------|------|--------------------+ | | | | | Data Length and | | | | | | | | | Access Type Logic <---wr_dl-----------|------|--------------------+ | | | | | | | | | | | | | | <---rd_kdl----------|------|--------------------+ | +-------|-------|---aw_bus---+ | | | | | | | | <27,5:0> | <---pop_rlog--------|------|--------------------+ | | | | | | | | | | | | | | <-+-wr_psl----------|------|--------------------+ | | | | `---------------------------' | | | | | | | | | .------------|------|--------------------+ | | | | | | | | | | | | | | | | | | | | | | | | .-----V------V-----. | | | | | | | | <---inc_rn-----+ | | | | | | | | | | | | | | | | <---dec_rn-----+ | | | | | | | Register | | | | | | | | | Number <---sc_rn------+ | | | | | | | Logic | | | | | | | | | <---pop_rlog---+ <-----------. | | | | | | | | | | aw_bus | | | | | <---clear_rn---+ | wrpr_w_dest MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 40 INSTRUCTION (I) BOX 09 Jan 85 <27,5:0>| | | | | | | | | | | | | | | <---rn<3:0>-+--> <-----. | | b_bus<31:0> | wr_psl | `---------^--------' | | | | | | | | | | | | `-----------' | | | | delta_pc<2:0> |rd_int_level sc<3:0> | wrpr_source | | | | | | | | | | V V V V V | V | | to/from E Box to Interrupt Logic to/from E Box MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 41 EXECUTION (E) BOX 09 Jan 85 3.0 EXECUTION (E) BOX The E Box contains the main execution data path. It consists of the following major functions: o General purpose registers o Temporary storage for 19 longwords of data or addresses o Program Counter (PC) o Constant generator o Shift Counter (SC) o Arithmetic logical unit (ALU) o Shifter o ALU, shifter, and PSL condition code logic o State logic o Register logging (RLOG) stack The E Box is connected to the IDAL. It does address and data transfers to and from the other subsystems over this bus. The Data Path receives instruction data from the I Box. It is controlled by the microinstruction and a limited amount of internal state. 3.1 Register File The Register File consists of three sub-files: the general purpose registers, the temporary registers, and the working registers. 3.1.1 General Purpose Registers (GPR[0:E]) - Fifteen of the locations in the register file are the General Purpose Registers, GPR[0] - GPR[E]. GPR[0] - GPR[D] are the user visible registers R0 - R13. GPR[E] is the user visible SP. GPR[F] is the PC and is located in the PC block. The address to the GPR's is either the A field of the microinstruction, the RN register, or the output of logic that adds one to the RN register. This is determined by the micro opcode and the associated Source/Destination field. This file is read onto the A_Bus and can be written from either the AW_Bus or the D_Bus. The D_Bus is the data path from the DAL. The AW_Bus is the path from the ALU and Shifter outputs. Writes are data length dependent: if FORCE_LONG%I_M%P24_H is asserted, the length is long; otherwise, the length is specified by the DL register. MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 42 EXECUTION (E) BOX 09 Jan 85 3.1.2 Temporary Registers (T[0:B]) - Twelve of the locations in the register file are the temporary registers, T[0] - T[B]. These may be used as general purpose temporary storage for intermediate results of microcode routines, or to hold architecturally specified registers or data. They are addressed by the A field of the microinstruction. This file is read onto the A_Bus and can be written from either the AW_Bus or the D_Bus. Transfers to and from the temporary registers are longwords only. T[0] through T[B] are general purpose temporary registers and reside in the E Box register file. T[C] is the VA' register and T[D] is the VIBA register, both of which reside in the M Box. T[E] is the opcode register, which resides in the I Box. T[F] is the Memory Management Status register, which resides in the M Box. T[C:F] may only be used with a limited subset of the microinstructions. T[C:E] are read only; T[F] is write only. 3.1.3 Working Registers (WR[0:6]) - Seven of the locations in the register file are the dual-ported working registers, WR[0] - WR[6]. These are used as general purpose storage of intermediate microcode routine results. WR[0] through WR[5] are general-purpose temporaries. WR[6] can be used as a destination register for three address arithmetic. It is loadable as WR[6] or can be written with the MISC field. It is always read as WR[6]. WR[7] is the SC register. While SC is usable as a normal working register, it has other functions. For a description of these functions, see the SC Logic section. Working registers are always addressed by the A and B fields; the register addressed by the A field appears on the A_Bus when selected, and the one addressed by the B field appears on the B_Bus. The AW_Bus data can be loaded into any of the working registers under control of the microword. WR[6,7] can be loaded in parallel with the other working registers or other temporaries under control of the MISC field. 3.1.4 Functional Summary - The following tables summarize the read/write operation of the register file as a function of the microinstruction. Note: Register file writes may be from one of two sources: the AW_Bus or the D_Bus, dependent on the microinstruction type. The source is the D_Bus for MXPR, FBOX XFER, and MEM REQ, and the AW_Bus otherwise. Note: During the MEM REQ READ microinstruction (data transfer from memory to E Box), the DAL Interface always zero extends the incoming data. On MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 43 EXECUTION (E) BOX 09 Jan 85 transfers of this type, the destination register will be written with this zero extended data. Note: PC and SC are also written from the register file bit lines, so these rules apply to the writing of these registers as well. 3.1.4.1 BASIC Source And Destination Control Field, CS<32:28> - A_Bus B_Bus Dest ----- ----- ---- 0 WR/PR[A] WR[B] WR/PR[A] 1 WR/PR[A] WR[B] None 2 WR/PR[A] WR[B] WR[B] 3 GPR[A] WR[B] None 4 WR/PR[A] MR[B] WR/PR[A] 5 WR/PR[A] MR[B] None 6 T[A] WR[B] None 7 8 GPR[A] MR[B] None 9 GPR[A] MR[B] GPR[A] A GPR[A] WR[B] WR[B] B GPR[A] WR[B] GPR[A] C T[A] MR[B] None D T[A] MR[B] T[A] E T[A] WR[B] WR[B] F T[A] WR[B] T[A] 10 GPR[RN] WR[B] WR/PR[A] 11 GPR[RN] WR[B] GPR[RN] & WR/PR[A] 12 GPR[RN+1] WR[B] WR/PR[A] 13 WR/PR[A] WR[B] GPR[RN+1] 14 15 GPR[RN] MR[B] GPR[RN] & WR/PR[A] 16 17 18 GPR[RN] MR[B] WR/PR[A] 19 WR/PR[A] MR[B] GPR[RN] 1A 1B 1C 1D 1E T[RN] WR[B] WR/PR[A] 1F MicroVAX CPU CHIP DESIGN SPECIFICATION (Company Confidential) Page 44 EXECUTION (E) BOX 09 Jan 85 3.1.4.2 CONSTANT Source And Destination Control Field, CS<31:29> - A_Bus Dest ----- ---- 0 WR/PR[A] WR/PR[A] 1 T[A] T[A] 2 GPR[A] GPR[A] 3 GPR[A] VA 4 WR/PR[A] None 5 WR/PR[A] WR6 6 WR/PR[A] SC 7 WR/PR[A] VA 3.1.4.3 SHIFT Source And Destination Control Field, CS<30:27> - A_Bus B_Bus Dest ----- ----- ---- 0 WR/PR[A] #0 WR[B] 1 WR/PR[A] #0 WR[B] 2 WR/PR[A] WR[B] None 3 WR/PR[A] WR[B] WR[B] 4 WR/PR[A] #0 WR/PR[A] 5 6 #0 WR[B] WR/PR[A] 7 #0 WR[B] WR/PR[A] 8 WR/PR[A] #0 None 9 A WR/PR[A] WR[B]