Mariah (there never was an xVAX name) was an intermediate step between Rigel and NVAX. Mostly a conversion of Rigel into CMOS3, it included two new features: a redesigned cache chip that supported write back caching, and support for the (new at the time) 32b physical memory ECO.
Starting with Mariah, my information on the microprocessor chips becomes less detailed.
Mariah was implemented in DEC's 1u triple-metal CMOS process (CMOS3). Depending on bin points, it ran at 62Mhz-71Mhz.
| Name | Number | Size | Transistors | Comments |
| Mariah CPU | The Mariah CPU was a conversion of the Rigel CPU to CMOS3. New
features:
|
|||
| Mariah FPU | The Mariah FPU was a conversion of the Rigel FPU to CMOS3. | |||
| Mariah Cache Controller | The Mariah cache controller supported up to 256KB of write through or write back cache. |
Mariah shipped in 1990 as an upgrade to VAX workstations and to the mid-range VAX 6000 series. The low-end system group (VAX 4000) chose to skip Mariah and go directly to NVAX.
While Mariah started on my watch as manager of the Microprocessor Group, it finished under my successor's (Dan Casaletto). Mariah was intended to stretch the life-time of the VAX 6000 by supporting write-back instead of write-through caching, which would ease the burden on the main memory bus (the XMI).
Mariah had a companion Advanced Development project, Mistral. The goal of Mistral was to build a much higher speed version of Mariah by cooling the chip-set to liquid nitrogen temperatures. The A/D team did pioneering work on the process and system implications of super-cooling, only to find that simply waiting for the next-generation chip produced an equivalent system solution as quickly at lower investment.
Updated 24-Feb-2008 by Bob Supnik (simh AT trailing-edge DOT com - anti-spam encoded)
