MPP (1987)

MPP (Massively Parallel Processor) was an experimental, large-scale SIMD (single instruction multiple data) parallel processor. It was targeted at providing supercomputer levels of performance in array applications such as simulation, fluid dynamics, and imaging. Built out of arrays of simple 4b processors coupled together by a scalable routing network, with a maximum of 65,536 processors, MPP was a direct descendent of the Goodyear SIMD processor and a predecessor to the Connection Machine.

MPP consisted of two chip types, both replicable: the MPP PE (processor element) chip and the MPP Router chip. They were implemented in DEC's 2u double-metal CMOS1 process and ran at 10Mhz.

Name Number Size Transistors Comments
MPP PE DC540 408x372 242,252 The MPP PE chip implements 32 processors of the MPP array. Key features include:
  • 32 4b processors per chip
    • 4b or 1b arithmetic and logical operations
    • 32b selectable size shift register
    • 12b selectable size shift register
    • Optimizations to support floating point arithmetic
  • 1Kb of memory per processor
    • Accessible in 4b or 1b sizes
    • Local address register for indirect addressing
    • Neighbor mode allows processors to 'borrow' memory
  • Grid routing network
    • North-east-south-west communication on and off chip
    • Row and column broadcast modes
  • Support for "wire or" of all processing elements in the array
  • High performance
    • 320 million 4b operations per second OR
    • 40 million 32b operations per second
  • Low power
  • Single +5V supply

Power: 0.5W.

MPP Router DC539 408x367 134,520 The MPP router implements a random routing network over the processor array. Its key features are:
  • 64 message inputs switched simultaneously to 64b message outputs
  • Configurable as 16 x 16 crossbar or 64 x 16 x 4 router
  • Bidirectional operation
  • Multiple paths per message for reduced blocking
  • Automatic detection and acknowledgement of blocked messages
  • Automatic detection and bypassing of broken wires
  • 160MB/s throughput
  • Low power
  • Single +5V supply

Power: 1W.

Personal Narrative

As MicroVAX wound down towards release in late 1984, the team members began developing other ideas. Dan Dobberpuhl and Rich Witek explored RISC technology. Bob Grondalski, the memory management unit designer, became interested in SIMD technology. By early 1985, he had an architecture for, and a performance model of, a SIMD system implemented in VLSI CMOS that would perform at (gasp!) 10 gigaflops per second. Working essentially alone, he produced a behavioral model for the core processing chip and went to the RAD Committee (an internal funding source for risky new projects) for funding to continue the work. The RAD Committee provided enough additional funds to hire a software developer, and the project went forward. By the end of the year, Bob had finished the logic, circuit, and layout design of both chips essentially single-handedly. With part-time help from a layout designer, and after a short delay while the fab's mask making facility was offline, the Router taped out in May, 1986, and the PE chip a month later. Both were functional, at speed, on first pass. A second pass of the PE chip in early 1987 added additional features and fixed a few bugs.

Lack of funding and resources delayed the system and software effort. A complete miniature system, with 8 PE's and 3 Routers, was functional by mid 1987, and a system with 64b PE's by September. At that point, the company decided to license MPP to Jeff Kalb, formerly the VP of the VLSI Group, who had left to do an MPP startup (MassPar). The decision was reversed at the end of the year, but the entire project was stalled for more than 3 months; by the end of 1987, only a 256 PE system had been assembled. The 512 PE system (16K processors) was finished in March, 1988.

Thereafter, the project simply got lost in the company's processes. Although approved for product development, changes in direction and competing claims for resources prevented any serious MPP productization effort from getting off the ground. The project simply faded away, and by 1989 the technology had been shelved.

Updated 30-Jan-2007 by Bob Supnik (simh AT trailing-edge DOT com - anti-spam encoded)