; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 1 ; Table of Contents ; 1 DEFINE.MCD ; 2 REVISION 3.27 ; 9 Revision History ; 49 Introductory Remarks ; 62 Microassembler Word Field Definitions ; 113 Microinstruction Opcodes ; 118 Operate Class ; 186 Literal Class ; 203 Address Class ; 215 Internal Input/Output Class ; 223 External Input/Output Class ; 233 Jump Class ; 246 Operand Length ; 257 Control Fields ; 259 Operate Type ; 279 Literal Type ; 284 Address Type ; 356 Internal Input/Output Type ; 426 External Input/Output Type ; 437 Jump Type ; 448 Register Selection ; 522 Diagnostics ; 540 PLA Field Definitions ; 542 PLA Input Fields ; 584 Override Fields ; 590 Validity Expressions ; 668 Macro Definitions ; 670 Instruction Mnemonics ; 672 Operate Class ; 674 Arithmetic Group ; 796 Logical Group ; 899 Shift Group ; 943 Multiply/Divide Group ; 967 Decimal Group ; 984 Prefetch Group ; 988 Literal Class ; 1040 Address Class ; 1063 Internal Input/Output Class ; 1077 External Input/Output Class ; 1095 Jump Class ; 1109 Control Field Mnemonics ; 1111 Operate Type ; 1117 Address Type ; 1137 External Input/Output Type ; 1144 Diagnostic Type ; 1153 PLA Mnemonics ; 1155 PLA Input Mnemonics ; 1177 PLA Override Mnemonics ; 1195 ; 1196 ; 1197 ; 1198 ; 1199 ; 1200 ; 1201 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 2 ; Table of Contents ; 1209 BASE.MCD ; 1210 REVISION 3.39 ; 1217 Revision History ; 1285 Introductory Remarks ; 1292 Power Up ; 1478 Power Up Test ; 1750 ID1 Q-Logic Next Addresses ; 1872 Prefetch Pipeline Resynchronization Sequences ; 1955 SOPs, DOPs, and Q-Logic Organization ; 2110 DOP Source Mode Decode ; 2142 Source Mode 1 ; 2188 Source Mode 2 ; 2255 Source Mode 3 ; 2343 Source Mode 4 ; 2431 Source Mode 5 ; 2539 Source Mode 6 ; 2594 Source Mode 7 ; 2676 SOP and DOP Destination Mode Decode ; 2714 Destination Mode 1 ; 2886 Destination Mode 2 ; 3098 Destination Mode 3 ; 3294 Destination Mode 4 ; 3501 Destination Mode 5 ; 3715 Destination Mode 6 ; 3904 Destination Mode 7 ; 4141 SOP and DOP Execution ; 4166 SOP Execution ; 4419 DOP Execution ; 4587 MTPS ; 4641 MFPI and MFPD ; 4690 MTPI and MTPD ; 4772 TSTSET and WRTLCK ; 4841 CSM ; 4972 EIS - Extended Instruction Set ; 4974 MUL - Multiply ; 5069 DIV - Divide ; 5232 ASH - Arithmetic Shift ; 5391 ASHC - Arithmetic Shift Combined ; 5600 JOP Decode ; 5638 JOP Mode 0 ; 5681 JOP Mode 1 ; 5767 JOP Mode 2 ; 5865 JOP Mode 3 ; 5994 JOP Mode 4 ; 6091 JOP Mode 5 ; 6197 JOP Mode 6 ; 6335 JOP Mode 7 ; 6442 Miscellaneous Instruction Decode ; 6459 Branches ; 6510 RTI and RTT ; 6569 RTS ; 6619 BPT, IOT, EMT, and TRAP ; 6657 CCC, SCC, and NOP ; 6694 MARK ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 3 ; Table of Contents ; 6728 RESET ; 6816 HALT ; 6875 MFPT ; 6900 SPL ; 6963 CIS Breakout ; 6991 Illegal Instructions ; 7016 WAIT ; 7047 Interrupt Service Decode ; 7219 Abort Service Decode ; 7240 Base Code Abort ; 7331 Micro Trap ; 7440 Multiple and ODT Abort, Power Up Breakout ; 7565 General Purpose Abort Return ; 7587 ODT.MCD ; 7588 REVISION 2.07 ; 7594 Revision History ; 7621 Introductory Remarks ; 7622 ODT States ; 7746 Register Assignments ; 7779 Notes ; 7807 Initialization ; 7842 Command Input and Breakout ; 7879 Default PLA Term ; 7906 R, $, and S ; 7934 0-7 Octal Digits ; 7972 P, G ; 8013 Slash ; 8113 Carriage Return ; 8177 Line Feed ; 8283 Control-Shift-S ; 8334 Subroutines ; 8336 Input Routine ; 8395 Output Routine ; 8455 Carriage Return and Line Feed ; 8484 Print Routine ; 8556 FP11.MCD ; 8557 REVISION 3.37 ; 8563 Revision History ; 8637 Introductory Remarks ; 8645 Floating Point Addressing ; 9045 SRC Addressing ; 9137 FSRC Addressing ; 9322 DST/FDST Addressing ; 9527 Post-addressing ; 9529 Warm DST/FDST ; 9573 Hot Support ; 9735 No Addressing ; 9805 Warm Floating Point Execution ; 9807 SRC Instructions ; 9809 LDFPS ; 9838 LDEXP ; 9878 LDCif ; 9955 DST Instructions ; 9957 STST ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 4 ; Table of Contents ; 9981 STFPS ; 10008 STEXP ; 10057 STCfi ; 10220 FSRC Instructions ; 10227 TSTf ; 10280 LDf ; 10335 LDCfd ; 10407 Arithmetics ; 10460 CMPf ; 10620 ADDf, SUBf ; 11079 MULf ; 11355 MODf ; 11652 DIVf ; 11855 Arithmetic Routines ; 11861 Normalization ; 12024 Rounding ; 12104 Store/update FCCs ; 12155 Under/overflow ; 12283 FDST Instructions ; 12285 STf ; 12335 STCfd ; 12462 CLRf ; 12516 FRMW Instructions ; 12518 ABSf, NEGf ; 12632 Common Routines ; 12634 uInstruction/NAF overrides ; 12636 Normalization PLAs ; 12719 Exponent Extractors ; 12773 Mantissa Extractors ; 12812 FN and FZ Overrides ; 12833 FD Override ; 12849 Miscellaneous ; 12851 Store FCC/AC/Exit ; 12885 Exact Zero ; 12934 FIUV Check ; 12977 Interrupt Check ; 13010 Abort Processing ; 13033 Register Restore ; 13101 Trap Handler ; 13158 PLADEF.MCD ; 13159 REVISION 3.07 ; 13165 Revision History ; 13188 Introductory Remarks ; 13195 PLA Address Assignments ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 5 ; DEFINE.MCD [242,1110] DEFINE.MCD ;1 .TOC "DEFINE.MCD" ;2 .TOC "REVISION 3.27" ;3 ;4 ;5 .NOBIN ;6 ;7 ;8 ;9 .TOC " Revision History" ;10 ;11 ; ;12 ; Revision History ;13 ; ---------------- ;14 ; ;15 ; Rev Date Explaination ;16 ; --- ---- ------------ ;17 ; Release ;18 ; 3.27 07/14/82 KEH; Redefined FEATMP as warm AC5.3 freeing ;19 ; old FEC code for MMUTMP2. Moved chip testing ;20 ; jump off chip into this code. ;21 ; Release ;22 ; 2.26 01/26/82 KEH; Modified revision code to represent chip pass. ;23 ; 2.25 12/17/81 KEH; Switched FEC and NPDR, and FEA and FPS ;24 ; INPR OUTR codes. ;25 ; 2.24 12/01/81 KEH; Added new MMU scratchpad mnemonics. ;26 ; 2.23 11/20/81 KEH; Changed GP address definitions for 2nd pass code. ;27 ; Release ;28 ; 1.22 04/14/81 KEH; Changed RSYNC to specify A-PORT/PS for branches. ;29 ; 1.21 03/21/81 KEH; Added two PLA macros which take mnemonics ;30 ; for NA field. ;31 ; 1.20 03/17/81 KEH; Switched OUTS MSTK and FPS control bits. ;32 ; 1.19 03/04/81 KEH; Updated GP code definitions. ;33 ; 1.18 02/05/81 KEH; Changed LOAD_ to LD_, CLOCK_ to CLK_. ;34 ; 1.17 01/16/81 KEH; Added alternate PS select codes. ;35 ; Changed mnemonics to CLK_FPS and LD_FPS. ;36 ; 1.16 01/06/81 KEH; Added NAF field value IRDF = 460. ;37 ; 1.15 12/15/80 KEH; Added SIR (Shadow IR). ;38 ; 1.12 10/30/80 KEH; Eliminated validity check on ADD.L [Rb.H, Ra], etc. ;39 ; 1.11 10/13/80 KEH; Changed breakpoint definitions for TUMS model. ;40 ; 1.10 09/22/80 KEH; Changed SOPs to take two arguements for consistency. ;41 ; Changed field names for JETI consistency. ;42 ; 1.09 08/20/80 KEH; PLA features added. Miscellaneous corrections. ;43 ; 1.08 07/21/80 KEH; Initial Release. No PLA features. ;44 ; 1.00 06/06/80 KEH; Preliminary. ;45 ; ;46 ; ;47 ;48 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 6 ; DEFINE.MCD [242,1110] Introductory Remarks ;49 .PAGE " Introductory Remarks" ;50 ;51 ; ;52 ; This file supplies field definitions, field values, macro ;53 ; definitions, and expression names to MICRO2. This procedure, ;54 ; combined with MICRO2's standard facilities, defines a custom ;55 ; microassembler for the J-11 chip set. This includes the ;56 ; microinstruction mnemonics, microassembler syntax, and ;57 ; microassembler error checking facilities. ;58 ; ;59 ;60 ;61 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 7 ; DEFINE.MCD [242,1110] Microassembler Word Field Definitions ;62 .PAGE " Microassembler Word Field Definitions" ;63 ;64 ; ;65 ; The J-11 microword is 32-bits wide. The microassembler ;66 ; microword as defined here is 48-bits wide however. The extra ;67 ; bits provide for PLA input declarations and special features in ;68 ; the TUMS and engineering tester simulators. ;69 ; ;70 ; ;71 ; ;72 ; ;73 ; 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 ;74 ; 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 ;75 ; +-----------------------------------------------------------------------------------------------+ ;76 ; | | D | | D | | ;77 ; | | I | | I | | ;78 ; | 0 | A | M I C R O I N S T R U C T I O N | A | N A F | ;79 ; | | G | | G | | ;80 ; | | . | | . | | ;81 ; +-----------------------------------------------------------------------------------------------+ ;82 ; ;83 ;84 ;85 ;86 .WIDTH/48 ; The microassembler word width is 48 ;87 ; (decimal) ;88 ;89 .RTOL ; The numbering system is right to left ;90 ;91 .OCTAL ; The default program radix is octal ;92 ;93 ; ;94 ; Note: ;95 ; All integers are interpreted as octal unless explicitly represented ;96 ; in decimal (e.g. 9. ) or binary (e.g. ^01 ) or if used in a field ;97 ; definition (decimal is always assumed). ;98 ; ;99 ;100 ;101 MICROINSTRUCTION/=<33:12>, .DEFAULT=17777777 ;102 ;103 NAF/=<9:0>, .NEXTADDRESS ;104 ;105 ID1 = 0477, .VALIDITY= ; Instruction Decode 1 ;106 ID2 = 0474 ; Instruction Decode 2 ;107 ID3 = 0471 ; Instruction Decode 3 ;108 IRDF = 0460 ; Instruction Read Demand Prefetch ;109 RFS = 0777 ; Return From Subroutine ;110 ;111 .NOCREF ;112 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 8 ; DEFINE.MCD [242,1110] Microinstruction Opcodes ;113 .TOC " Microinstruction Opcodes" ;114 ;115 ;116 OPC/=<33:27>, .DEFAULT=177 ;117 ;118 .TOC " Operate Class" ;119 ;120 ; Arithmetic group ;121 ;122 ADD = 144, .VALIDITY= ; Add ;123 ADDC = 160, .VALIDITY= ; Add with carry ;124 INC = 136, .VALIDITY= ; Increment ;125 ADC = 164, .VALIDITY= ; Add carry ;126 SUB = 141, .VALIDITY= ; Subtract ;127 SUBC = 165, .VALIDITY= ; Subtract with carry ;128 DEC = 145, .VALIDITY= ; Decrement ;129 SBC = 161, .VALIDITY= ; Subtract carry ;130 AOBC = 172, .VALIDITY= ; Add on branch condition ;131 SOBC = 140, .VALIDITY= ; Subtract on branch condition ;132 NEG = 133, .VALIDITY= ; Negate ;133 NEGC = 137, .VALIDITY= ; Negate with carry ;134 CNEG = 103, .VALIDITY= ; Conditional negate (if C = 1) ;135 ACNEG = 113, .VALIDITY= ; Conditional negate (if AC = 1) ;136 NNEG = 107, .VALIDITY= ; Conditional negate (if N = 1) ;137 ANNEG = 117, .VALIDITY= ; Conditional negate (if AN = 1) ;138 CMP = 143, .VALIDITY= ; Compare ;139 ;140 ; Logical group ;141 ;142 MOV = 156, .VALIDITY= ; Move ;143 MOVPM = 112, .VALIDITY= ; Move using previous mode ;144 MOVS = 102, .VALIDITY= ; Move sign extended ;145 CLR = 104, .VALIDITY= ; Clear ;146 COM = 147, .VALIDITY= ; Complement ;147 SXT = 106, .VALIDITY= ; Sign extend ;148 AND = 151, .VALIDITY= ; And ;149 BIC = 155, .VALIDITY= ; Bit clear ;150 BIS = 157, .VALIDITY= ; Bit set ;151 XOR = 154, .VALIDITY= ; Exclusive-or ;152 BIT = 150 ; Bit test ;153 TST = 166 ; Test ;154 MTST = 167 ; Multiply test ;155 SWAB = 146, .VALIDITY= ; Swap bytes ;156 NOP = 177, .VALIDITY= ; No operation ;157 ;158 ; Shift group ;159 ;160 ASR = 134, .VALIDITY= ; Arithmetic shift right ;161 ROR = 124, .VALIDITY= ; Rotate right ;162 LSR = 120, .VALIDITY= ; Logical shift right ;163 LSRQ = 130, .VALIDITY= ; Logical shift right quadword ;164 ASL = 123, .VALIDITY= ; Arithmetic shift left ;165 ROL = 121, .VALIDITY= ; Rotate left ;166 ASLQ = 131, .VALIDITY= ; Arithmetic shift left ;167 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 9 ; DEFINE.MCD [242,1110] Operate Class ;168 ; Multiply/divide group ;169 ;170 UMULS = 110, .VALIDITY= ; Unsigned multiply step ;171 SMULS = 114, .VALIDITY= ; Signed multiply step ;172 DIVS = 105, .VALIDITY= ; Divide step ;173 XLDIVS = 111, .VALIDITY= ; Extended low divide step ;174 XHDIVS = 115, .VALIDITY= ; Extended high divide step ;175 ;176 ; Decimal group ;177 ;178 DADP = 174, .VALIDITY= ; Decimal post-adjust ;179 PDAD = 170, .VALIDITY= ; Decimal pre-adjust ;180 ;181 ; Prefetch group ;182 ;183 RSYNC = 162 ; Resynchronize ;184 ;185 ;186 .TOC " Literal Class" ;187 ;188 LLD = 056 ; Load literal ;189 LLSW = 046 ; Load literal swapped ;190 LLCM = 047 ; Load literal complement ;191 LCNTR = 052 ; Load counter ;192 LMSTK = 053 ; Load stack ;193 LCMP = 043, .VALIDITY= ; Compare literal ;194 LADD = 044 ; Add literal ;195 LSUB = 041 ; Subtract literal ;196 LBIS = 057 ; Bit set literal ;197 LAND = 051 ; And literal ;198 LBIC = 055 ; Bit clear literal ;199 LBIT = 050, .VALIDITY= ; Bit test literal ;200 LXOR = 054 ; Exclusive-or literal ;201 ;202 ;203 .TOC " Address Class" ;204 ;205 AR = 073, .VALIDITY= ; Address read ;206 ARI = 070, .VALIDITY= ; Address read and increment ;207 ARD = 071, .VALIDITY= ; Address read and decrement ;208 AW = 077, .VALIDITY= ; Address write ;209 AWI = 074, .VALIDITY= ; Address write and increment ;210 AWD = 075, .VALIDITY= ; Address write and decrement ;211 ARG = 063 ; Address read general purpose ;212 AWG = 067 ; Address write general purpose ;213 ;214 ;215 .TOC " Internal Input/Output Class" ;216 ;217 INPR = 021 ; Read data from MMU register ;218 OUTR = 025 ; Write data to MMU register ;219 OUTS = 027, .VALIDITY= ; Write control chip status ;220 OUTC = 026, .VALIDITY= ; Write control chip control ;221 ;222 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 10 ; DEFINE.MCD [242,1110] External Input/Output Class ;223 .TOC " External Input/Output Class" ;224 ;225 RD = 032 ; Read data ;226 RMW = 033 ; Read-modify-write data ;227 RDG = 036 ; Read general purpose ;228 RDINTR = 037 ; Read interrupt vector ;229 RDI = 030, .VALIDITY= ; Read instruction stream ;230 RDF = 031 ; Read demand prefetch ;231 ;232 ;233 .TOC " Jump Class" ;234 ;235 JMP = 000 ; Jump unconditionally ;236 JAN = 017 ; Jump if AN flag = 1 ;237 JAZ = 011 ; Jump if AZ flag = 1 ;238 JAC = 013 ; Jump if AC flag = 1 ;239 JAV = 015 ; Jump if AV flag = 1 ;240 JN = 007 ; Jump if PS N flag = 1 ;241 JZ = 001 ; Jump if PS Z flag = 1 ;242 JC = 003 ; Jump if PS C flag = 1 ;243 JV = 005 ; Jump if PS V flag = 1 ;244 JKM = 016 ; Jump if kernel mode ;245 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 11 ; DEFINE.MCD [242,1110] Operand Length ;246 .TOC " Operand Length" ;247 ;248 LN/=<26:25>, .DEFAULT = 3 ;249 ;250 WORD = 0 ; Word operand ;251 LONG = 1, .VALIDITY= ; Longword operand ;252 WRD1 = 2 ; Word operand ;253 BYTE = 3 ; Byte operand ;254 ;255 ;256 ;257 .TOC " Control Fields" ;258 ;259 .TOC " Operate Type" ;260 ;261 CC/=<22>, .DEFAULT = 1 ; Condition code control ;262 ;263 UPDATE = 0 ; Set from ALU flags ;264 SAME = 1 ; Leave unchanged ;265 ;266 ;267 DC/=<23>, .DEFAULT = 1 ; Counter control ;268 ;269 DECR = 0 ;270 NO = 1 ;271 ;272 ;273 PF/=<24>, .DEFAULT = 1 ; Prefetch control ;274 ;275 YES = 0 ;276 NO = 1 ;277 ;278 ;279 .TOC " Literal Type" ;280 ;281 LIT/=<24:17>, .DEFAULT = 377 ; No other control fields ;282 ;283 ;284 .TOC " Address Type" ;285 ;286 SPACE/=<18:17>, .DEFAULT = 3 ; I/D space select ;287 ;288 I = 0 ; I space unconditionally ;289 MFPI = 1 ; I space unless PS<15:12> = 1111 ;290 D = 2 ; D space unconditionally ;291 NORMAL = 3 ; D space unless Ra is PC ;292 ;293 ;294 ABORTS/=<19>, .DEFAULT = 1 ; Abort suppression ;295 ;296 DISABLE = 0 ; Disable aborts ;297 YES = 1 ; Map as usual ;298 ;299 ;300 TRAP/=<20>, .DEFAULT = 1 ; Odd address trap enable ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 12 ; DEFINE.MCD [242,1110] Address Type ;301 ;302 YES = 0 ; Enable trap ;303 NO = 1 ; No effect ;304 ;305 ;306 OVF/=<21>, .DEFAULT = 1 ; Stack overflow logic enable ;307 ;308 YES = 0 ; Enable ;309 NO = 1 ; Disable ;310 ;311 ;312 MODE/=<23:22>, .DEFAULT = 3 ; Mode selection ;313 ;314 KERNEL = 0 ;315 PREVIOUS= 1 ;316 CONSOLE = 2 ;317 CURRENT = 3 ;318 ;319 ;320 MMR1/=<24>, .DEFAULT = 1 ; Update MMR1 enable ;321 ;322 UPDATE = 0 ;323 NO = 1 ;324 ;325 .CREF ;326 ;327 GPA/=<24:17>, .DEFAULT = 377 ; ARG and AWG general purpose address field ;328 ;329 ; Read class ;330 OPTIONS = 000 ; Power up and HALT options. ;331 FPA_RD = 001 ; Read FPA's FCC/integer. ;332 OPTIONS_CLR = 002 ; Board options/clear FPA's FPS. ;333 FPA_ACK = 003 ; Read FPA's FEC/acknowledge. ;334 ; Write class ;335 FPA_ON = 001 ; Enable FPA. ;336 FPA_OFF = 002 ; Disable FPA. ;337 FPA_WR = 003 ; Write FPA data. ;338 LED1_ON = 220 ; Light LED1. ;339 LED2_ON = 224 ; Light LED2. ;340 LED3_ON = 230 ; Light LED3. ;341 LED4_ON = 234 ; Light LED4. ;342 LED4_OFF = 034 ; Clear LED4. ;343 BINIT_ON = 014 ; Assert BINIT L. ;344 BINIT_OFF = 214 ; Deassert BINIT L. ;345 BEVNT_ACK = 100 ; BEVNT acknowledge. ;346 PWRF_ACK = 140 ; Power fail acknowledge. ;347 NMI_ACK = 040 ; NMI acknowledge. ;348 ; RDINTR class ;349 IRL7 = 010 ; Interrupt Reguest level 7. ;350 IRL6 = 004 ; Interrupt Reguest level 6. ;351 IRL5 = 002 ; Interrupt Reguest level 5. ;352 IRL4 = 001 ; Interrupt Reguest level 4. ;353 ;354 ;355 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 13 ; DEFINE.MCD [242,1110] Internal Input/Output Type ;356 .TOC " Internal Input/Output Type" ;357 ;358 RMMU/=<24:17>, .DEFAULT = 377 ; For INPR and OUTR ;359 ;360 CPAR = 147 ; Console PAR ;361 CPU = 157 ; CPU error register ;362 ;363 FEA = 057 ; Floating exception address. Old FPS. ;364 FPS = 056 ; Floating point status. Old FEA. ;365 ; FPS code must be even ! ;366 FEC = 046 ; Floating exception code. Old NPDR. ;367 FEATMP = 155 ; Hot FEA support register. ;368 ; Same as warm AC5.3. ;369 MMUTMP2 = 156 ; Scratchpad. Old FEC. ;370 MMUTMP = 047 ; Scratchpad. Old CPDR. ;371 ;372 ; Indirect FP accumulator codes ;373 AC20.0= 341 ; n = IR<2:0> , AC[n]<15:0> ;374 AC20.1= 241 ; n = IR<2:0> , AC[n]<31:16> ;375 AC20.2= 351 ; n = IR<2:0> , AC[n]<47:32> ;376 AC20.3= 251 ; n = IR<2:0> , AC[n]<63:48> ;377 AC76.0= 342 ; n = IR<7:6> , AC[n]<15:0> ;378 AC76.1= 242 ; n = IR<7:6> , AC[n]<31:16> ;379 AC76.2= 352 ; n = IR<7:6> , AC[n]<47:32> ;380 AC76.3= 252 ; n = IR<7:6> , AC[n]<63:48> ;381 AC76+1.0= 344 ; n = IR<7:6> OR 1, AC[n]<15:0> ;382 AC76+1.1= 244 ; n = IR<7:6> OR 1, AC[n]<31:16> ;383 AC76+1.2= 354 ; n = IR<7:6> OR 1, AC[n]<47:32> ;384 AC76+1.3= 254 ; n = IR<7:6> OR 1, AC[n]<63:48> ;385 ;386 MMR0 = 200 ;387 MMR1 = 201 ;388 MMR3 = 202 ;389 PIRQ = 203 ;390 CCR = 204 ;391 HIT_MISS= 205 ;392 SR = 206 ;393 SIR = 207 ;394 ;395 ;396 OUTS_CONTROL/=<24:17>, .DEFAULT = 377 ;397 ;398 INTERRUPTS = 376 ; Load interrupt service ;399 ABORTS = 375 ; Load abort service ;400 LD_FPS = 373 ; Load FP FFs and MDAL<11:0> into PIR. ;401 MSTK = 367 ; Load control chip stack ;402 LD_PIR = 357 ; Load PIR from MDAL ;403 LD_CNTR = 337 ; Load control chip counter ;404 PSW = 277 ; Load control chip PS ;405 CLK_FPS = 177 ; Clock FP FFs from MDAL<7:5>. ;406 ;407 LD_PIR_CNTR = 317 ; Load PIR and CNTR from MDAL. ;408 ;409 ;410 OUTC_CONTROL/=<24:17>, .DEFAULT = 377 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 14 ; DEFINE.MCD [242,1110] Internal Input/Output Type ;411 ;412 SET_SSFF = 375 ;413 CLR_SSFF = 374 ;414 SET_CPFF = 373 ;415 CLR_CPFF = 372 ;416 CPY_T-BIT = 357 ;417 CLR_SOVFF = 337 ;418 CLR_ITFF = 277 ;419 CLR_PTYFF = 177 ;420 CLR_ALL = 030 ; PTYFF, SOVFF, ITFF, SSFF, CPFF ;421 CLR_SVC_FFS = 034 ; PTYFF, SOVFF, ITFF, SSFF ;422 CPY_TBIT-CLR_SSFF = 354 ; Copy PS<4> and Clear SSFF. ;423 INI_ALL = 031 ; Clear PTYFF, SOVFF, and ITFF, ;424 ; set SSFF and CPFF ;425 ;426 .TOC " External Input/Output Type" ;427 ;428 .NOCREF ;429 ;430 RD_CONTROL/=<24:17>, .DEFAULT = 377 ;431 ;432 RTI-RTT = 357 ; PS protection ;433 VECTOR = 337 ; PS protection ;434 LOCKED = 177 ; Read locked ;435 ;436 ;437 .TOC " Jump Type" ;438 ;439 CJAR/=<26:17>, .DEFAULT = 1777 ; Also used for LMSTK ;440 ;441 CSEL/=<16:12>, .DEFAULT = 37 ;442 ;443 BASE = 0 ;444 CIS1 = 3 ;445 CIS2 = 2 ;446 WCS = 1 ;447 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 15 ; DEFINE.MCD [242,1110] Register Selection ;448 .TOC " Register Selection" ;449 ;450 A-PORT/=<16:12>, .DEFAULT = 37 ;451 ;452 PS = 0 ;453 PS1 = 1 ; Alternate ;454 PS2 = 2 ; Alternate ;455 RSRC+1 = 3 ; R(n), n = IR<8:6> OR 1 ;456 RE+ = 4 ; Alternate code for RE<31:0> ;457 RF+ = 5 ; Alternate code for RF<31:0> ;458 RDST = 6 ; R(n), n = IR<2:0> ;459 RSRC = 7 ; R(n), n = IR<8:6> ;460 R8.H = 10, .VALIDITY= ; R8<31:16> ;461 R9.H = 11, .VALIDITY= ; R9<31:16> ;462 RA.H = 12, .VALIDITY= ; RA<31:16> ;463 RB.H = 13, .VALIDITY= ; RB<31:16> ;464 RC.H = 14, .VALIDITY= ; RC<31:16> ;465 RD.H = 15, .VALIDITY= ; RD<31:16> ;466 RE.H = 16, .VALIDITY= ; RE<31:16> ;467 RF.H = 17, .VALIDITY= ; RF<31:16> ;468 R0 = 20 ;469 R1 = 21 ;470 R2 = 22 ;471 R3 = 23 ;472 R4 = 24 ;473 R5 = 25 ;474 SP = 26 ;475 PC = 27 ;476 R8 = 30 ; R8<31:0> ;477 R9 = 31 ; R9<31:0> ;478 RA = 32 ; RA<31:0> ;479 RB = 33 ; RB<31:0> ;480 RC = 34 ; RC<31:0> ;481 RD = 35 ; RD<31:0> ;482 RE = 36 ; RE<31:0> ;483 RF = 37 ; RF<31:0> ;484 ;485 ;486 B-PORT/=<21:17>, .DEFAULT = 37 ;487 ;488 PS = 0 ;489 IRFE = 1 ; IR field extractor ;490 MMR2 = 2 ;491 RSRC+1 = 3 ; R(n), n = IR<8:6> OR 1 ;492 RE+ = 4 ; Alternate code for RE<31:0> ;493 RF+ = 5 ; Alternate code for RF<31:0> ;494 RDST = 6 ; R(n), n = IR<2:0> ;495 RSRC = 7 ; R(n), n = IR<8:6> ;496 R8.H = 10, .VALIDITY= ; R8<31:16> ;497 R9.H = 11, .VALIDITY= ; R9<31:16> ;498 RA.H = 12, .VALIDITY= ; RA<31:16> ;499 RB.H = 13, .VALIDITY= ; RB<31:16> ;500 RC.H = 14, .VALIDITY= ; RC<31:16> ;501 RD.H = 15, .VALIDITY= ; RD<31:16> ;502 RE.H = 16, .VALIDITY= ; RE<31:16> ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 16 ; DEFINE.MCD [242,1110] Register Selection ;503 RF.H = 17, .VALIDITY= ; RF<31:16> ;504 R0 = 20 ;505 R1 = 21 ;506 R2 = 22 ;507 R3 = 23 ;508 R4 = 24 ;509 R5 = 25 ;510 SP = 26 ;511 PC = 27 ;512 R8 = 30 ; R8<31:0> ;513 R9 = 31 ; R9<31:0> ;514 RA = 32 ; RA<31:0> ;515 RB = 33 ; RB<31:0> ;516 RC = 34 ; RC<31:0> ;517 RD = 35 ; RD<31:0> ;518 RE = 36 ; RE<31:0> ;519 RF = 37 ; RF<31:0> ;520 ;521 ;522 .TOC " Diagnostics" ;523 ;524 BR0/=<10>, .DEFAULT = 0 ;525 ;526 ON = 1 ;527 ;528 BR1/=<11>, .DEFAULT = 0 ;529 ;530 ON = 1 ;531 ;532 BR2/=<34>, .DEFAULT = 0 ;533 ;534 ON = 1 ;535 ;536 BR3/=<35>, .DEFAULT = 0 ;537 ;538 ON = 1 ;539 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 17 ; DEFINE.MCD [242,1110] PLA Field Definitions ;540 .TOC " PLA Field Definitions" ;541 ;542 .TOC " PLA Input Fields" ;543 ;544 ; ;545 ; The PLA input conditions are specified in four separate fields of ;546 ; the microassembler word as shown graphically below: ;547 ; ;548 ; ;549 ; ;550 ; 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 ;551 ; 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 ;552 ; +-----------------------------------------------------------------------------------------------+ ;553 ; | | | | | ;554 ; | N A | P I R | N A | P I R | ;555 ; | D O N ' T | D O N ' T | | | ;556 ; | C A R E | C A R E | O N E S | O N E S | ;557 ; | | | | | ;558 ; +-----------------------------------------------------------------------------------------------+ ;559 ; ;560 ; ;561 ; The PIR and NA ONES fields specify which PIR and NA inputs must be ones. ;562 ; The PIR and NA DON'T CARE fields specify which bits are don't cares. ;563 ; ;564 ; The PLA0 and PLA1 banks are represented as being in the fictitious ;565 ; addressing ranges 2000-2777, and 3000-3777 respectively. In these ;566 ; ranges, an even numbered address specifies the PLA AND term (input ;567 ; conditions) as defined above, and an odd numbered address specifies ;568 ; the PLA OR term (microinstruction) as defined for ROM code. The PLA ;569 ; AND term must be immediately followed by it's associated OR term. ;570 ; ;571 ;572 ;573 PIR1/=<16:00>, .DEFAULT = 377777 ;574 ;575 NAF0/=<23:17>, .DEFAULT = 177, .VALIDITY = ;576 ; Different VALIDITY expressions ;577 NAF1/=<23:17>, .VALIDITY = ; check for consistent address specifier. ;578 ;579 PIRX/=<40:24>, .DEFAULT = 1777 ;580 ;581 NAFX/=<47:41> ;582 ;583 ;584 .TOC " Override Fields" ;585 ;586 PLAOPC/=<33:27>, .DEFAULT = 177, .VALIDITY = ;587 ;588 RDOVR = 173 ; For WRITE --> READ override. ;589 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 18 ; DEFINE.MCD [242,1110] Validity Expressions ;590 .TOC " Validity Expressions" ;591 ;592 ;593 ; Not valid if A-PORT code selects high word. ;594 ;595 .SET/V1 = <.NOT[<.LEQ[10, , 17]>]> ;596 ;597 ;598 ; Not valid if B-PORT code selects high word. ;599 ;600 ; .SET/V2 = <.NOT[<.LEQ[10, , 17]>]> ;601 .SET/V2 = 1 ;602 ;603 ;604 ; Not valid if LONGWORD is specified. ;605 ;606 ; .SET/V3 = <.NEQ[, ]> ;607 ;608 ;609 ; Not valid if NAF is ID1. ;610 ;611 .SET/V4 = <.NEQ[, 477]> ;612 ;613 ;614 ; Not valid if A-PORT contains PC. ;615 ;616 .SET/V6 = <.NEQ[, ]> ;617 ;618 ;619 ; Not valid if MICROINSTRUCTION is all ones AND PLA OR term. ;620 ;621 .SET/V7 = <.NOT[<.AND[<.EQL[, 17777777]>, V27]>]> ;622 ;623 ;624 ; Not valid if LONGWORD or NAF is ID1. ;625 ;626 ; .SET/V10 = <.AND[V3, V4]> ;627 ;628 ;629 ; Not valid if PREFETCH and A-PORT contains PC. ;630 ;631 .SET/V11 = <.OR[<.NEQ[, ]>, V6]> ;632 ;633 ;634 ; Not valid if B-PORT selects high word or PREFETCH and PC. ;635 ;636 .SET/V12 = <.AND[V2, V11]> ;637 ;638 ;639 ; Valid if address is even. ;640 ;641 .SET/V20 = <.NOT[<.MOD[., 2]>]> ;642 ;643 ;644 ; Valid if PLA0 addressing range. ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 19 ; DEFINE.MCD [242,1110] Validity Expressions ;645 ;646 .SET/V21 = <.LEQ[2000, ., 2777]> ;647 ;648 ;649 ; Valid if PLA1 addressing range. ;650 ;651 .SET/V22 = <.LEQ[3000, ., 3777]> ;652 ;653 ;654 ; Valid if PLA bank 0. ;655 ;656 .SET/V25 = <.AND[V20, V21]> ;657 ;658 ;659 ; Valid if PLA bank 1. ;660 ;661 .SET/V26 = <.AND[V20, V22]> ;662 ;663 ;664 ; Valid for PLAs only. ;665 ;666 .SET/V27 = <.OR[V21, V22]> ;667 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 20 ; DEFINE.MCD [242,1110] Macro Definitions ;668 .TOC " Macro Definitions" ;669 ;670 .TOC " Instruction Mnemonics" ;671 ;672 .TOC " Operate Class" ;673 ;674 .TOC " Arithmetic Group" ;675 ;676 .CREF ;677 ADD.B [ , ] "OPC/ADD, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;678 ADD.W [ , ] "OPC/ADD, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;679 ADD.L [ , ] "OPC/ADD, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;680 ADD.B* [ , ] "OPC/ADD, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;681 ADD.W* [ , ] "OPC/ADD, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;682 ADD.L* [ , ] "OPC/ADD, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;683 ;684 ADDC.B [ , ] "OPC/ADDC, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;685 ADDC.W [ , ] "OPC/ADDC, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;686 ADDC.L [ , ] "OPC/ADDC, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;687 ADDC.B* [ , ] "OPC/ADDC, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;688 ADDC.W* [ , ] "OPC/ADDC, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;689 ADDC.L* [ , ] "OPC/ADDC, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;690 ;691 INC.B [ , ] "OPC/INC, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;692 INC.W [ , ] "OPC/INC, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;693 INC.L [ , ] "OPC/INC, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;694 INC.B* [ , ] "OPC/INC, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;695 INC.W* [ , ] "OPC/INC, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;696 INC.L* [ , ] "OPC/INC, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;697 ;698 ADC.B [ , ] "OPC/ADC, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;699 ADC.W [ , ] "OPC/ADC, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;700 ADC.L [ , ] "OPC/ADC, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;701 ADC.B* [ , ] "OPC/ADC, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;702 ADC.W* [ , ] "OPC/ADC, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;703 ADC.L* [ , ] "OPC/ADC, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;704 ;705 SUB.B [ , ] "OPC/SUB, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;706 SUB.W [ , ] "OPC/SUB, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;707 SUB.L [ , ] "OPC/SUB, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;708 SUB.B* [ , ] "OPC/SUB, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;709 SUB.W* [ , ] "OPC/SUB, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;710 SUB.L* [ , ] "OPC/SUB, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;711 ;712 SUBC.B [ , ] "OPC/SUBC, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;713 SUBC.W [ , ] "OPC/SUBC, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;714 SUBC.L [ , ] "OPC/SUBC, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;715 SUBC.B* [ , ] "OPC/SUBC, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;716 SUBC.W* [ , ] "OPC/SUBC, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;717 SUBC.L* [ , ] "OPC/SUBC, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;718 ;719 DEC.B [ , ] "OPC/DEC, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;720 DEC.W [ , ] "OPC/DEC, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;721 DEC.L [ , ] "OPC/DEC, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;722 DEC.B* [ , ] "OPC/DEC, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 21 ; DEFINE.MCD [242,1110] Arithmetic Group ;723 DEC.W* [ , ] "OPC/DEC, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;724 DEC.L* [ , ] "OPC/DEC, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;725 ;726 SBC.B [ , ] "OPC/SBC, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;727 SBC.W [ , ] "OPC/SBC, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;728 SBC.L [ , ] "OPC/SBC, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;729 SBC.B* [ , ] "OPC/SBC, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;730 SBC.W* [ , ] "OPC/SBC, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;731 SBC.L* [ , ] "OPC/SBC, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;732 ;733 AOBC.B [ , ] "OPC/AOBC, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;734 AOBC.W [ , ] "OPC/AOBC, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;735 AOBC.L [ , ] "OPC/AOBC, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;736 AOBC.B* [ , ] "OPC/AOBC, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;737 AOBC.W* [ , ] "OPC/AOBC, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;738 AOBC.L* [ , ] "OPC/AOBC, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;739 ;740 SOBC.B [ , ] "OPC/SOBC, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;741 SOBC.W [ , ] "OPC/SOBC, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;742 SOBC.L [ , ] "OPC/SOBC, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;743 SOBC.B* [ , ] "OPC/SOBC, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;744 SOBC.W* [ , ] "OPC/SOBC, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;745 SOBC.L* [ , ] "OPC/SOBC, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;746 ;747 NEG.B [ , ] "OPC/NEG, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;748 NEG.W [ , ] "OPC/NEG, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;749 NEG.L [ , ] "OPC/NEG, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;750 NEG.B* [ , ] "OPC/NEG, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;751 NEG.W* [ , ] "OPC/NEG, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;752 NEG.L* [ , ] "OPC/NEG, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;753 ;754 NEGC.B [ , ] "OPC/NEGC, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;755 NEGC.W [ , ] "OPC/NEGC, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;756 NEGC.L [ , ] "OPC/NEGC, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;757 NEGC.B* [ , ] "OPC/NEGC, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;758 NEGC.W* [ , ] "OPC/NEGC, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;759 NEGC.L* [ , ] "OPC/NEGC, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;760 ;761 CNEG.B [ , ] "OPC/CNEG, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;762 CNEG.W [ , ] "OPC/CNEG, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;763 CNEG.L [ , ] "OPC/CNEG, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;764 CNEG.B* [ , ] "OPC/CNEG, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;765 CNEG.W* [ , ] "OPC/CNEG, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;766 CNEG.L* [ , ] "OPC/CNEG, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;767 ;768 ACNEG.B [ , ] "OPC/ACNEG, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;769 ACNEG.W [ , ] "OPC/ACNEG, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;770 ACNEG.L [ , ] "OPC/ACNEG, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;771 ACNEG.B* [ , ] "OPC/ACNEG, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;772 ACNEG.W* [ , ] "OPC/ACNEG, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;773 ACNEG.L* [ , ] "OPC/ACNEG, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;774 ;775 NNEG.B [ , ] "OPC/NNEG, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;776 NNEG.W [ , ] "OPC/NNEG, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;777 NNEG.L [ , ] "OPC/NNEG, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 22 ; DEFINE.MCD [242,1110] Arithmetic Group ;778 NNEG.B* [ , ] "OPC/NNEG, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;779 NNEG.W* [ , ] "OPC/NNEG, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;780 NNEG.L* [ , ] "OPC/NNEG, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;781 ;782 ANNEG.B [ , ] "OPC/ANNEG, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;783 ANNEG.W [ , ] "OPC/ANNEG, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;784 ANNEG.L [ , ] "OPC/ANNEG, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;785 ANNEG.B* [ , ] "OPC/ANNEG, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;786 ANNEG.W* [ , ] "OPC/ANNEG, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;787 ANNEG.L* [ , ] "OPC/ANNEG, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;788 ;789 CMP.B [ , ] "OPC/CMP, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;790 CMP.W [ , ] "OPC/CMP, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;791 CMP.L [ , ] "OPC/CMP, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;792 CMP.B* [ , ] "OPC/CMP, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;793 CMP.W* [ , ] "OPC/CMP, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;794 CMP.L* [ , ] "OPC/CMP, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;795 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 23 ; DEFINE.MCD [242,1110] Logical Group ;796 .TOC " Logical Group" ;797 ;798 MOV.B [ , ] "OPC/MOV, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;799 MOV.W [ , ] "OPC/MOV, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;800 MOV.L [ , ] "OPC/MOV, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;801 MOV.B* [ , ] "OPC/MOV, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;802 MOV.W* [ , ] "OPC/MOV, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;803 MOV.L* [ , ] "OPC/MOV, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;804 ;805 MOVPM.B [ , ] "OPC/MOVPM, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;806 MOVPM.W [ , ] "OPC/MOVPM, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;807 MOVPM.L [ , ] "OPC/MOVPM, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;808 MOVPM.B* [ , ] "OPC/MOVPM, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;809 MOVPM.W* [ , ] "OPC/MOVPM, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;810 MOVPM.L* [ , ] "OPC/MOVPM, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;811 ;812 MOVS.B [ , ] "OPC/MOVS, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;813 MOVS.W [ , ] "OPC/MOVS, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;814 MOVS.L [ , ] "OPC/MOVS, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;815 MOVS.B* [ , ] "OPC/MOVS, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;816 MOVS.W* [ , ] "OPC/MOVS, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;817 MOVS.L* [ , ] "OPC/MOVS, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;818 ;819 CLR.B [ , ] "OPC/CLR, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;820 CLR.W [ , ] "OPC/CLR, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;821 CLR.L [ , ] "OPC/CLR, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;822 CLR.B* [ , ] "OPC/CLR, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;823 CLR.W* [ , ] "OPC/CLR, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;824 CLR.L* [ , ] "OPC/CLR, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;825 ;826 COM.B [ , ] "OPC/COM, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;827 COM.W [ , ] "OPC/COM, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;828 COM.L [ , ] "OPC/COM, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;829 COM.B* [ , ] "OPC/COM, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;830 COM.W* [ , ] "OPC/COM, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;831 COM.L* [ , ] "OPC/COM, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;832 ;833 SXT.B [ , ] "OPC/SXT, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;834 SXT.W [ , ] "OPC/SXT, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;835 SXT.L [ , ] "OPC/SXT, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;836 SXT.B* [ , ] "OPC/SXT, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;837 SXT.W* [ , ] "OPC/SXT, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;838 SXT.L* [ , ] "OPC/SXT, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;839 ;840 AND.B [ , ] "OPC/AND, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;841 AND.W [ , ] "OPC/AND, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;842 AND.L [ , ] "OPC/AND, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;843 AND.B* [ , ] "OPC/AND, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;844 AND.W* [ , ] "OPC/AND, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;845 AND.L* [ , ] "OPC/AND, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;846 ;847 BIC.B [ , ] "OPC/BIC, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;848 BIC.W [ , ] "OPC/BIC, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;849 BIC.L [ , ] "OPC/BIC, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;850 BIC.B* [ , ] "OPC/BIC, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 24 ; DEFINE.MCD [242,1110] Logical Group ;851 BIC.W* [ , ] "OPC/BIC, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;852 BIC.L* [ , ] "OPC/BIC, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;853 ;854 BIS.B [ , ] "OPC/BIS, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;855 BIS.W [ , ] "OPC/BIS, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;856 BIS.L [ , ] "OPC/BIS, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;857 BIS.B* [ , ] "OPC/BIS, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;858 BIS.W* [ , ] "OPC/BIS, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;859 BIS.L* [ , ] "OPC/BIS, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;860 ;861 XOR.B [ , ] "OPC/XOR, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;862 XOR.W [ , ] "OPC/XOR, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;863 XOR.L [ , ] "OPC/XOR, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;864 XOR.B* [ , ] "OPC/XOR, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;865 XOR.W* [ , ] "OPC/XOR, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;866 XOR.L* [ , ] "OPC/XOR, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;867 ;868 BIT.B [ , ] "OPC/BIT, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;869 BIT.W [ , ] "OPC/BIT, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;870 BIT.L [ , ] "OPC/BIT, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;871 BIT.B* [ , ] "OPC/BIT, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;872 BIT.W* [ , ] "OPC/BIT, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;873 BIT.L* [ , ] "OPC/BIT, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;874 ;875 TST.B [ , ] "OPC/TST, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;876 TST.W [ , ] "OPC/TST, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;877 TST.L [ , ] "OPC/TST, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;878 TST.B* [ , ] "OPC/TST, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;879 TST.W* [ , ] "OPC/TST, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;880 TST.L* [ , ] "OPC/TST, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;881 ;882 MTST [ , ] "OPC/MTST, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;883 MTST* [ , ] "OPC/MTST, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;884 ;885 SWAB.B [ , ] "OPC/SWAB, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;886 SWAB.W [ , ] "OPC/SWAB, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;887 SWAB.L [ , ] "OPC/SWAB, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;888 SWAB.B* [ , ] "OPC/SWAB, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;889 SWAB.W* [ , ] "OPC/SWAB, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;890 SWAB.L* [ , ] "OPC/SWAB, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;891 ;892 NOP.B [ , ] "OPC/NOP, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;893 NOP.W [ , ] "OPC/NOP, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;894 NOP.L [ , ] "OPC/NOP, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;895 NOP.B* [ , ] "OPC/NOP, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;896 NOP.W* [ , ] "OPC/NOP, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;897 NOP.L* [ , ] "OPC/NOP, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;898 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 25 ; DEFINE.MCD [242,1110] Shift Group ;899 .TOC " Shift Group" ;900 ;901 ASR.B [ , ] "OPC/ASR, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;902 ASR.W [ , ] "OPC/ASR, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;903 ASR.L [ , ] "OPC/ASR, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;904 ASR.B* [ , ] "OPC/ASR, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;905 ASR.W* [ , ] "OPC/ASR, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;906 ASR.L* [ , ] "OPC/ASR, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;907 ;908 ROR.B [ , ] "OPC/ROR, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;909 ROR.W [ , ] "OPC/ROR, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;910 ROR.L [ , ] "OPC/ROR, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;911 ROR.B* [ , ] "OPC/ROR, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;912 ROR.W* [ , ] "OPC/ROR, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;913 ROR.L* [ , ] "OPC/ROR, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;914 ;915 LSR.B [ , ] "OPC/LSR, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;916 LSR.W [ , ] "OPC/LSR, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;917 LSR.L [ , ] "OPC/LSR, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;918 LSR.B* [ , ] "OPC/LSR, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;919 LSR.W* [ , ] "OPC/LSR, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;920 LSR.L* [ , ] "OPC/LSR, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;921 ;922 LSR.Q [ , ] "OPC/LSRQ, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;923 LSR.Q* [ , ] "OPC/LSRQ, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;924 ;925 ASL.B [ , ] "OPC/ASL, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;926 ASL.W [ , ] "OPC/ASL, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;927 ASL.L [ , ] "OPC/ASL, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;928 ASL.B* [ , ] "OPC/ASL, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;929 ASL.W* [ , ] "OPC/ASL, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;930 ASL.L* [ , ] "OPC/ASL, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;931 ;932 ASL.Q [ , ] "OPC/ASLQ, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;933 ASL.Q* [ , ] "OPC/ASLQ, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;934 ;935 ROL.B [ , ] "OPC/ROL, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@2" ;936 ROL.W [ , ] "OPC/ROL, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;937 ROL.L [ , ] "OPC/ROL, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;938 ROL.B* [ , ] "OPC/ROL, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;939 ROL.W* [ , ] "OPC/ROL, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;940 ROL.L* [ , ] "OPC/ROL, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;941 ;942 ;943 .TOC " Multiply/Divide Group" ;944 ;945 UMULS.W [ , ] "OPC/UMULS, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;946 UMULS.L [ , ] "OPC/UMULS, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;947 UMULS.W* [ , ] "OPC/UMULS, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;948 UMULS.L* [ , ] "OPC/UMULS, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;949 ;950 SMULS.W [ , ] "OPC/SMULS, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;951 SMULS.L [ , ] "OPC/SMULS, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;952 SMULS.W* [ , ] "OPC/SMULS, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;953 SMULS.L* [ , ] "OPC/SMULS, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 26 ; DEFINE.MCD [242,1110] Multiply/Divide Group ;954 ;955 DIVS.W [ , ] "OPC/DIVS, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@2" ;956 DIVS.L [ , ] "OPC/DIVS, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;957 DIVS.W* [ , ] "OPC/DIVS, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;958 DIVS.L* [ , ] "OPC/DIVS, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;959 ;960 XLDIVS [ , ] "OPC/XLDIVS, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;961 XLDIVS* [ , ] "OPC/XLDIVS, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;962 ;963 XHDIVS [ , ] "OPC/XHDIVS, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@2" ;964 XHDIVS* [ , ] "OPC/XHDIVS, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@2" ;965 ;966 ;967 .TOC " Decimal Group" ;968 ;969 DADP.B [ ] "OPC/DADP, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@1" ;970 DADP.W [ ] "OPC/DADP, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@1" ;971 DADP.L [ ] "OPC/DADP, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@1" ;972 DADP.B* [ ] "OPC/DADP, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@1" ;973 DADP.W* [ ] "OPC/DADP, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@1" ;974 DADP.L* [ ] "OPC/DADP, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@1" ;975 ;976 PDAD.B [ ] "OPC/PDAD, LN/BYTE, CC/SAME, B-PORT/@1, A-PORT/@1" ;977 PDAD.W [ ] "OPC/PDAD, LN/WORD, CC/SAME, B-PORT/@1, A-PORT/@1" ;978 PDAD.L [ ] "OPC/PDAD, LN/LONG, CC/SAME, B-PORT/@1, A-PORT/@1" ;979 PDAD.B* [ ] "OPC/PDAD, LN/BYTE, CC/UPDATE, B-PORT/@1, A-PORT/@1" ;980 PDAD.W* [ ] "OPC/PDAD, LN/WORD, CC/UPDATE, B-PORT/@1, A-PORT/@1" ;981 PDAD.L* [ ] "OPC/PDAD, LN/LONG, CC/UPDATE, B-PORT/@1, A-PORT/@1" ;982 ;983 ;984 .TOC " Prefetch Group" ;985 ;986 RSYNC "OPC/RSYNC, LN/WORD, CC/SAME, A-PORT/PS" ;987 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 27 ; DEFINE.MCD [242,1110] Literal Class ;988 .TOC " Literal Class" ;989 ;990 LLD.B [ , ] "OPC/LLD, LN/BYTE, LIT/@1, A-PORT/@2" ;991 LLD.W [ , ] "OPC/LLD, LN/WORD, LIT/@1, A-PORT/@2" ;992 LLD.L [ , ] "OPC/LLD, LN/LONG, LIT/@1, A-PORT/@2" ;993 ;994 LLSW.B [ , ] "OPC/LLSW, LN/BYTE, LIT/@1, A-PORT/@2" ;995 LLSW.W [ , ] "OPC/LLSW, LN/WORD, LIT/@1, A-PORT/@2" ;996 LLSW.L [ , ] "OPC/LLSW, LN/LONG, LIT/@1, A-PORT/@2" ;997 ;998 LLCM.B [ , ] "OPC/LLCM, LN/BYTE, LIT/@1, A-PORT/@2" ;999 LLCM.W [ , ] "OPC/LLCM, LN/WORD, LIT/@1, A-PORT/@2" ;1000 LLCM.L [ , ] "OPC/LLCM, LN/LONG, LIT/@1, A-PORT/@2" ;1001 ;1002 LCNTR.B [ , ] "OPC/LCNTR, LN/BYTE, LIT/@1, A-PORT/@2" ;1003 LCNTR.W [ , ] "OPC/LCNTR, LN/WORD, LIT/@1, A-PORT/@2" ;1004 LCNTR.L [ , ] "OPC/LCNTR, LN/LONG, LIT/@1, A-PORT/@2" ;1005 ;1006 LMSTK [ , ] "OPC/LMSTK, CJAR/, A-PORT/@2" ;1007 ;1008 LCMP.B [ , ] "OPC/LCMP, LN/BYTE, LIT/@1, A-PORT/@2" ;1009 LCMP.W [ , ] "OPC/LCMP, LN/WORD, LIT/@1, A-PORT/@2" ;1010 LCMP.L [ , ] "OPC/LCMP, LN/LONG, LIT/@1, A-PORT/@2" ;1011 ;1012 LADD.B [ , ] "OPC/LADD, LN/BYTE, LIT/@1, A-PORT/@2" ;1013 LADD.W [ , ] "OPC/LADD, LN/WORD, LIT/@1, A-PORT/@2" ;1014 LADD.L [ , ] "OPC/LADD, LN/LONG, LIT/@1, A-PORT/@2" ;1015 ;1016 LSUB.B [ , ] "OPC/LSUB, LN/BYTE, LIT/@1, A-PORT/@2" ;1017 LSUB.W [ , ] "OPC/LSUB, LN/WORD, LIT/@1, A-PORT/@2" ;1018 LSUB.L [ , ] "OPC/LSUB, LN/LONG, LIT/@1, A-PORT/@2" ;1019 ;1020 LBIS.B [ , ] "OPC/LBIS, LN/BYTE, LIT/@1, A-PORT/@2" ;1021 LBIS.W [ , ] "OPC/LBIS, LN/WORD, LIT/@1, A-PORT/@2" ;1022 LBIS.L [ , ] "OPC/LBIS, LN/LONG, LIT/@1, A-PORT/@2" ;1023 ;1024 LAND.B [ , ] "OPC/LAND, LN/BYTE, LIT/@1, A-PORT/@2" ;1025 LAND.W [ , ] "OPC/LAND, LN/WORD, LIT/@1, A-PORT/@2" ;1026 LAND.L [ , ] "OPC/LAND, LN/LONG, LIT/@1, A-PORT/@2" ;1027 ;1028 LBIC.B [ , ] "OPC/LBIC, LN/BYTE, LIT/@1, A-PORT/@2" ;1029 LBIC.W [ , ] "OPC/LBIC, LN/WORD, LIT/@1, A-PORT/@2" ;1030 LBIC.L [ , ] "OPC/LBIC, LN/LONG, LIT/@1, A-PORT/@2" ;1031 ;1032 LBIT.B [ , ] "OPC/LBIT, LN/BYTE, LIT/@1, A-PORT/@2" ;1033 LBIT.W [ , ] "OPC/LBIT, LN/WORD, LIT/@1, A-PORT/@2" ;1034 LBIT.L [ , ] "OPC/LBIT, LN/LONG, LIT/@1, A-PORT/@2" ;1035 ;1036 LXOR.B [ , ] "OPC/LXOR, LN/BYTE, LIT/@1, A-PORT/@2" ;1037 LXOR.W [ , ] "OPC/LXOR, LN/WORD, LIT/@1, A-PORT/@2" ;1038 LXOR.L [ , ] "OPC/LXOR, LN/LONG, LIT/@1, A-PORT/@2" ;1039 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 28 ; DEFINE.MCD [242,1110] Address Class ;1040 .TOC " Address Class" ;1041 ;1042 AR [ ] "OPC/AR, LN/WORD, A-PORT/@1" ;1043 ;1044 ARI.B [ ] "OPC/ARI, LN/WRD1, A-PORT/@1" ;1045 ARI.W [ ] "OPC/ARI, LN/WORD, A-PORT/@1" ;1046 ;1047 ARD.B [ ] "OPC/ARD, LN/WRD1, A-PORT/@1" ;1048 ARD.W [ ] "OPC/ARD, LN/WORD, A-PORT/@1" ;1049 ;1050 AW [ ] "OPC/AW, LN/WORD, A-PORT/@1" ;1051 ;1052 AWI.B [ ] "OPC/AWI, LN/WRD1, A-PORT/@1" ;1053 AWI.W [ ] "OPC/AWI, LN/WORD, A-PORT/@1" ;1054 ;1055 AWD.B [ ] "OPC/AWD, LN/WRD1, A-PORT/@1" ;1056 AWD.W [ ] "OPC/AWD, LN/WORD, A-PORT/@1" ;1057 ;1058 ARG.W [ ] "OPC/ARG, LN/WORD, GPA/@1" ;1059 ;1060 AWG.W [ ] "OPC/AWG, LN/WORD, GPA/@1" ;1061 ;1062 ;1063 .TOC " Internal Input/Output Class" ;1064 ;1065 INPR.W [ , ] "OPC/INPR, LN/WORD, RMMU/@1, A-PORT/@2" ;1066 INPR.L [ , ] "OPC/INPR, LN/LONG, RMMU/@1, A-PORT/@2" ;1067 ;1068 OUTR.W [ , ] "OPC/OUTR, LN/WORD, RMMU/@1, A-PORT/@2" ;1069 OUTR.L [ , ] "OPC/OUTR, LN/LONG, RMMU/@1, A-PORT/@2" ;1070 ;1071 OUTS [ ] "OPC/OUTS, LN/WORD, OUTS_CONTROL/@1" ;1072 OUTS [ , ] "OPC/OUTS, LN/WORD, OUTS_CONTROL/@1, A-PORT/@2" ;1073 ;1074 OUTC [ ] "OPC/OUTC, LN/WORD, OUTC_CONTROL/@1" ;1075 ;1076 ;1077 .TOC " External Input/Output Class" ;1078 ;1079 RD.B [ ] "OPC/RD, LN/BYTE, A-PORT/@1" ;1080 RD.W [ ] "OPC/RD, LN/WORD, A-PORT/@1" ;1081 ;1082 RMW.B [ ] "OPC/RMW, LN/BYTE, A-PORT/@1" ;1083 RMW.W [ ] "OPC/RMW, LN/WORD, A-PORT/@1" ;1084 ;1085 RDG.B [ ] "OPC/RDG, LN/BYTE, A-PORT/@1" ;1086 RDG.W [ ] "OPC/RDG, LN/WORD, A-PORT/@1" ;1087 ;1088 RDINTR [ ] "OPC/RDINTR, LN/WORD, A-PORT/@1" ;1089 ;1090 RDI [ ] "OPC/RDI, LN/WORD, A-PORT/@1" ;1091 ;1092 RDF "OPC/RDF, LN/WORD" ;1093 ;1094 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 29 ; DEFINE.MCD [242,1110] Jump Class ;1095 .TOC " Jump Class" ;1096 ;1097 JAN [ ] "OPC/JAN, CJAR/" ;1098 JAZ [ ] "OPC/JAZ, CJAR/" ;1099 JAC [ ] "OPC/JAC, CJAR/" ;1100 JAV [ ] "OPC/JAV, CJAR/" ;1101 JN [ ] "OPC/JN, CJAR/" ;1102 JZ [ ] "OPC/JZ, CJAR/" ;1103 JC [ ] "OPC/JC, CJAR/" ;1104 JV [ ] "OPC/JV, CJAR/" ;1105 JKM [ ] "OPC/JKM, CJAR/" ;1106 ;1107 JMP [ , ] "OPC/JMP, CJAR/, CSEL/@2" ;1108 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 30 ; DEFINE.MCD [242,1110] Control Field Mnemonics ;1109 .TOC " Control Field Mnemonics" ;1110 ;1111 .TOC " Operate Type" ;1112 ;1113 PREFETCH "PF/YES" ;1114 DECR CNTR "DC/DECR" ;1115 ;1116 ;1117 .TOC " Address Type" ;1118 ;1119 I SPACE "SPACE/I" ;1120 D SPACE "SPACE/D" ;1121 MFPI SPACE "SPACE/MFPI" ;1122 ;1123 NO ABORTS "ABORTS/DISABLE" ;1124 16-BIT MAP "ABORTS/DISABLE" ;1125 ;1126 ODD TRAP "TRAP/YES" ;1127 ;1128 SOVFF "OVF/YES" ;1129 ;1130 KERNEL MODE "MODE/KERNEL" ;1131 PREVIOUS MODE "MODE/PREVIOUS" ;1132 CONSOLE MODE "MODE/CONSOLE" ;1133 ;1134 LD MMR1 "MMR1/UPDATE" ;1135 ;1136 ;1137 .TOC " External Input/Output Type" ;1138 ;1139 RTI-RTT PS PROTECT "RD_CONTROL/RTI-RTT" ;1140 VECTOR PS PROTECT "RD_CONTROL/VECTOR" ;1141 READ LOCKED "RD_CONTROL/LOCKED" ;1142 ;1143 ;1144 .TOC " Diagnostic Type" ;1145 ;1146 .NOCREF ;1147 ;1148 BK25 "BR0/ON" ;1149 BK125 "BR1/ON" ;1150 BK225 "BR2/ON" ;1151 BK325 "BR3/ON" ;1152 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 31 ; DEFINE.MCD [242,1110] PLA Mnemonics ;1153 .TOC " PLA Mnemonics" ;1154 ;1155 .TOC " PLA Input Mnemonics" ;1156 ;1157 PLA0 [ , ] "NAF0/<.GETONES[@1]>, ;1158 NAFX/<.GETXS[@1]>, ;1159 PIR1/<.GETONES[@2]>, ;1160 PIRX/<.GETXS[@2]>" ;1161 ;1162 PLA1 [ , ] "NAF1/<.GETONES[@1]>, ;1163 NAFX/<.GETXS[@1]>, ;1164 PIR1/<.GETONES[@2]>, ;1165 PIRX/<.GETXS[@2]>" ;1166 ;1167 NPLA0 [ , ] "NAF0/<.AND[,177]>, ;1168 NAFX/0, ;1169 PIR1/<.GETONES[@2]>, ;1170 PIRX/<.GETXS[@2]>" ;1171 ;1172 NPLA1 [ , ] "NAF1/<.AND[,177]>, ;1173 NAFX/0, ;1174 PIR1/<.GETONES[@2]>, ;1175 PIRX/<.GETXS[@2]>" ;1176 ;1177 .TOC " PLA Override Mnemonics" ;1178 ;1179 BYTE --> WORD "LN/WORD" ;1180 ;1181 WRITE --> READ "PLAOPC/RDOVR" ;1182 ;1183 RE_RE --> RDST_RDST "MICROINSTRUCTION/17776347" ;1184 ;1185 ;1186 ;1187 ;1188 .REGION/0,377/1000,3777 ;1189 ;1190 ;1191 1252: ; This ROM based jump for chip testing. ;1192 JMP [1777, 37], ; Mask code inserted in jump field ;1193 NAF/1777 ; and NAF. ;1194 ;1195 .TOC "" ; Start code listing on new page. ;1196 .TOC "" ;1197 .TOC "" ;1198 .TOC "" ;1199 .TOC "" ;1200 .TOC "" ;1201 .TOC "" ;1202 ;1203 ;1204 ;1205 .BIN ;1206 .CREF ;1207 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 32 ; BASE .MCD [242,1110] ;1208 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 33 ; BASE .MCD [242,1110] BASE.MCD ;1209 .TOC "BASE.MCD" ;1210 .TOC "REVISION 3.39" ;1211 ;1212 ;1213 .NOBIN ;1214 ;1215 ;1216 ;1217 .TOC " Revision History" ;1218 ;1219 ; ;1220 ; Revision History ;1221 ; ---------------- ;1222 ; ;1223 ; Rev. Date Explaination ;1224 ; ---- ---- ------------ ;1225 ; ;1226 ; 3.39 01/20/83 Hard coded certain addresses such as yellow zone ;1227 ; and resync to make certain they do not change. ;1228 ; Release 01/04/83 (Mini-pass for RTI-RTT fix) ;1229 ; 3.38 01/04/83 KEH; Add FEC masking (LAND.W) during FPE service ;1230 ; 3.37 01/03/83 VO; Changed RTI-RTT code to perform PS protection ;1231 ; directly in microcode due to Data-chip problems ;1232 ; Release ;1233 ; 3.36 07/14/82 KEH; Move chip testing jump off chip to DEFINE.MCD. ;1234 ; Release ;1235 ; 2.35 01/27/82 KEH; Changed use of RF to RD in P-U-T due to confict ;1236 ; with power up option 3. ;1237 ; 2.34 01/26/82 KEH; Integrated Power Up Test into this code. ;1238 ; 2.33 01/26/82 KEH; Modified revision code to represent chip pass. ;1239 ; 2.32 01/15/82 KEH; Switched sense of CPFF for warm FP. ;1240 ; 2.31 01/02/82 KEH; Moved P.OPTION to bank 0 by changing option 0 ;1241 ; and P-U-T entry point. ;1242 ; 2.30 12/15/81 KEH; Added LED 4 write for ODT exit (at PWR-UP-ODT). ;1243 ; 2.29 11/25/81 KEH; Integrated NPLA for pass two code. No code change. ;1244 ; 2.28 11/20/81 KEH; Saved two words. RESET5 shared with ODT and SI ;1245 ; initialization during power up. RESET5 is used to ;1246 ; set NAs of miscellaneous aborts. Also updated all ;1247 ; GP mnemonics and functions. ;1248 ; 2.27 11/18/81 KEH; Used LMSTK to load constant in CSM; saved a word. ;1249 ; 2.26 10/01/81 KEH; Changed RESET-NOP register for FP11 (RA => RF). ;1250 ; 2.25 08/10/81 KEH; Changed FPE acknowledge for FP11. ;1251 ; Release ;1252 ; 1.24 06/23/81 KEH; Added Power Up Test, MEVENT-L, and JMP off chip. ;1253 ; 1.23 05/11/81 KEH; Changed power up option 3 as to new specification. ;1254 ; 1.22 04/04/81 KEH; Fixed bug with RSYNC, ID1 by altering DEFINE.MCD; ;1255 ; must specify 16-bit register on MPRDC-L. ;1256 ; Eliminated unnecessary constraints by changing ;1257 ; RE -> RDST NAF overrides. Renamed an FP11 symbol. ;1258 ; 1.21 03/18/81 KEH; Fixed bug with not updating CC's for MFPx and MTPx. ;1259 ; 1.20 03/08/81 KEH; Added TSTSET and WRTLCK, multiprocessor hooks. ;1260 ; 1.19 03/05/81 KEH; Added corrections suggested at code review. ;1261 ; Changes to Power Up - added abort to ODT mechanism, ;1262 ; changed options 2 and 3 around, and added abort ;1263 ; on CCR as well as MSER initialization. ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 34 ; BASE .MCD [242,1110] Revision History ;1264 ; Added that RESET clears PIRQ. ;1265 ; Added that CSM fetches new PC from I Space. ;1266 ; 1.18 03/02/81 KEH; Changed Base Code Abort and Multiple Abort to ;1267 ; reflect change in Abort Service information. ;1268 ; Also removed CPU Error register<15>. ;1269 ; 1.17 02/15/81 KEH; Added CC twittle at DIV0 for 11/70 compatibility (no cost). ;1270 ; 1.16 02/10/81 KEH; Removed LD MMR1 when powering up through vector 24. ;1271 ; 1.15 02/09/81 KEH; Added restoration of original operands when DIV overflows. ;1272 ; 1.14 01/30/81 KEH; Major modifications to ASH, ASHC, and SPL. Reduced overhead ;1273 ; in ASH and ASHC. Reduced ROM count in exchange for PLA. ;1274 ; 1.13 01/16/81 KEH; Fixed oversite in Rev 1.12 and added PLA for MFPS Mode 0. ;1275 ; 1.12 01/15/81 KEH; Reorganized JOPs and added JSR Mode 37 optimization. ;1276 ; 1.11 01/15/81 KEH; Fixed bug in Source Modes 4 and 5. ;1277 ; 1.10 01/11/81 KEH; Cleaned up WAIT, Interrupt Service, Base Abort, and M-TRAP. ;1278 ; 1.09 01/06/81 KEH; Started changes for Q-Logic IRDF fix. ;1279 ; 1.08 01/05/81 KEH; Made power-up sequence a subroutine for ODT. ;1280 ; 1.05 12/04/80 KEH; Changed M-TRAP and Multiple Abort routines for sunset loop prevention. ;1281 ; 1.00 11/13/80 KEH; Edited and assembled. ;1282 ; 0.76 08/04/80 KEH; Preliminary. ;1283 ; ;1284 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 35 ; BASE .MCD [242,1110] Introductory Remarks ;1285 .PAGE " Introductory Remarks" ;1286 ;1287 ; ;1288 ; This microcode implements the PDP-11 Base Instruction Set. ;1289 ; This includes power-up and all interrupt and abort processing. ;1290 ; ;1291 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 36 ; BASE .MCD [242,1110] Power Up ;1292 .TOC " Power Up" ;1293 ;1294 ; ;1295 ; Entry Conditions: ;1296 ; ;1297 ; NA = 000; NA was zeroed by MINIT-L. ;1298 ; ;1299 ; Entered on Power Up. ;1300 ; ;1301 ; Exit Conditions: ;1302 ; ;1303 ; Dependent on Power Up options. ;1304 ; ;1305 ; Option Result ;1306 ; ------ ------ ;1307 ; 0 Vector through location 24. ;1308 ; 1 Enter ODT. ;1309 ; 2 Power up to 173000. ;1310 ; 3 Power up to user boot address. ;1311 ; ;1312 ; Method: ;1313 ; ;1314 ; The BINIT-L line is asserted through use of a GP code and MMR0 and MMR3 ;1315 ; are cleared. The CPU Error Register and Floating Point Status registers ;1316 ; are cleared. A GP code then reads in POKH and the Power Up options and ;1317 ; waits for POKH to be asserted. The CPFF is also set (if specified) at ;1318 ; this time. The external Memory System Error (if it exists), the Cache ;1319 ; Control, and the Programmed Interrupt Request Registers are then also ;1320 ; cleared using explicit addresses. The Power Up Test is executed and ;1321 ; finally, the Power Up options are decoded and each one is serviced ;1322 ; accordingly. ;1323 ; ;1324 ; Assumptions: ;1325 ; ;1326 ; It is assumed that a set of jumpers on the CPU board which can be ;1327 ; read with the GP code "OPTIONS" is configured as follows: ;1328 ; ;1329 ; 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ;1330 ; +---------------------------------------------------------------+ ;1331 ; | | | |H O| | | ;1332 ; | USER |F H| |A P| POWER | P | ;1333 ; | SUPPLIED |P E| MODULE |L T| UP | O | ;1334 ; | BOOT |A R| ID |T I| OPTION| K | ;1335 ; | ADDRESS | E| | O| | H | ;1336 ; | | | | N| | | ;1337 ; +---------------------------------------------------------------+ ;1338 ; ;1339 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 37 ; BASE .MCD [242,1110] Power Up ;1340 .BIN ;1341 ;1342 ; See Multiple Abort routine for actual context. ;1343 ;1344 ;0: ;1345 ;MULTIPLE-ABORT: ;1346 ; OUTS [ABORTS] ; PIR<12,7,4:0> <-- HLTFF, SSFF, ABFF<4:0>. ;1347 ; ;1348 ; NOP.W [RF, RF], ; Allow time for PLA translation. ;1349 ; NAF/407 ; Invoke PLA decode. ;1350 ; ;1351 ;H-POKH-F: ; POKH is not asserted. ;1352 ;POWER-UP: ; ABFF<0> = 0. Power up. ;1353 ;=10********0 ;1354 ;PLA0 [^0 00X 111, ^X XXX XXX XXX XXX XX0] ;1355 ; LMSTK [P-U-T1, RA], ; Set up return to do Power Up Test. ;1356 ; NAF/PWR-UP-ODT ; Go to "Power Up" sequence. ;1357 ;= ;1358 PWR-UP-ODT: ; Entry for console "G" initialization. U 0007, 0000,0670,1637,0013 ;1359 AWG.W [LED4_OFF] ; Signal exit from ODT. ;1360 ;1361 ; See constraint on PWR-UP1. U 0013, 0000,0530,0172,0014 ;1362 LMSTK [PWR-UP1, RA] ; Load return from bus init routine. ;1363 ;1364 OUTC [INI_ALL], ; Clear PTYFF, ITFF and SOVFF, set CPFF and SSFF. U 0014, 0000,0260,1477,0032 ;1365 NAF/RESET-SUB ; Go reset the bus. ;1366 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 38 ; BASE .MCD [242,1110] Power Up ;1367 ; Reset the bus and turn off Memory Management. ;1368 ;1369 RESET-SUB: U 0032, 0000,0670,0637,1500 ;1370 AWG.W [BINIT_ON] ; Assert BINIT L next cycle. ;1371 ;1372 1500: ; For TUMS use only. ;1373 LCNTR.W [105, RA], ; Load CNTR for 10 us wait (69.). U 1500, 0000,0520,4272,0017 ;1374 NAF/RESET1 ; Start wait loop. Skip next instruction. ;1375 =0 ; Constrain NAF for CNTR loop. ;1376 AWG.W [BINIT_OFF], ; Deassert BINIT L next cycle. U 0016, 0000,0671,0637,1501 ;1377 NAF/RESET2 ; Go turn off BINIT L. Skip next instruction. ;1378 RESET1: ;1379 CLR.W [RA, RA], ; Clear EU register for OUTR. ;1380 DECR CNTR, ; Loop here for a while. U 0017, 0000,1041,3532,0017 ;1381 NAF/RESET1 ; Go back one when done. ;1382 = ;1383 1501: ; For TUMS use only. ;1384 RESET2: ;1385 LCNTR.W [310, RB], ; Load CNTR for 90 us wait (200.). U 1501, 0000,0521,4433,0055 ;1386 NAF/RESET3 ; Skip past next instruction. ;1387 ;1388 =0 ; Constrain NAF for CNTR loop. ;1389 LLCM.W [005, RE], ; RE <-- 177772, PIRQ. U 0054, 0000,0470,0276,0070 ;1390 NAF/RESET4 ; Skip over loop. ;1391 RESET3: U 0055, 0000,0251,0032,0041 ;1392 OUTR.W [MMR0, RA] ; Clear MMR0. ;1393 = U 0041, 0000,0251,0132,0043 ;1394 OUTR.W [MMR3, RA] ; Clear MMR3. ;1395 ;1396 MOV.W [PC, PC], ; Clear PPCV since MMU gets turned off. ;1397 DECR CNTR, ; Decrement the loop counter. U 0043, 0000,1561,3367,0055 ;1398 NAF/RESET3 ; Loop on three microinstructions. ;1399 RESET4: ;1400 AW [RE], ; Stuff PIRQ address into OL. MMU is off. U 0070, 0000,0771,7776,0024 ;1401 NAF/RESET5 ; Write a zero to PIRQ. ;1402 ;1403 ;=0*0****0 ; Abort to ROM[0] for ODT I/O routines. ;1404 ;RESET5: ; Return from print loop in ODT. ;1405 ; CLR.W [RA, RA], ; For RESET-SUB, clear PIRQ in all chips. ;1406 ; NAF/240 ; For RESET-SUB, abort to ROM[MSTK AND 240]. ;1407 ; ; For SI power up, abort to ROM[240]. ;1408 ; ; For ODT, save code; return. ;1409 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 39 ; BASE .MCD [242,1110] Power Up ;1410 ; Guarantee LMSTK.W for LED 4 write. ;1411 =00*0***** ; Abort to ROM[0] and go to ODT-ABORT ;1412 PWR-UP1: ; just in case PIRQ aborts (it won't). U 0003, 0000,0250,2732,0076 ;1413 OUTR.W [FPS, RA] ; Clear the Floating Point Status. ;1414 = U 0076, 0000,0270,7772,0102 ;1415 OUTS [CLK_FPS, RA] ; Clear Control chip copy of FPS. ;1416 ;1417 ;1418 ; Read in power up options and decode POKH, then FPA status. ;1419 ;1420 PWR-UP2: U 0102, 0000,0630,0137,0111 ;1421 ARG.W [OPTIONS_CLR] ; Read in POKH and options from SI. ;1422 ; Clear FPA's FPS for ODT "G". ;1423 U 0111, 0000,0361,7777,0114 ;1424 RDG.W [RF] ; Read them into RF. ;1425 U 0114, 0000,0271,6777,0116 ;1426 OUTS [LD_PIR, RF] ; Now stuff it into PIR. ;1427 ;1428 OUTR.W [CPU, RA], ; Clear the CPU error register. U 0116, 0000,0250,6772,0415 ;1429 NAF/P.POKH ; Decode options and POKH. ;1430 ;1431 =10********0 ; Turns on if POKH is NOT asserted. U 2000, 0037,7776,0640,0000 ;1432 NPLA0 [P.POKH, ^X XXX XXX XXX XXX XX0] ;1433 NOP.W [RF, RF], ; Wait for POKH before going on. U 2001, 0000,1771,7777,0102 ;1434 NAF/PWR-UP2 ; Loop back and re-read POKH. ;1435 = ;1436 =10********0 ; Turns on if POKH is asserted and FPA NOT present. U 2002, 0037,7376,0640,0001 ;1437 NPLA0 [P.POKH, ^X XXX XXX 0XX XXX XX1] ;1438 OUTC [SET_CPFF], ; Set the NOT CPFF in Control chips. U 2003, 0000,0261,7577,0123 ;1439 NAF/PWR-UP3 ;1440 = ;1441 =10********0 ; Turns on if POKH is asserted and FPA present. U 2004, 0037,7376,0640,0401 ;1442 NPLA0 [P.POKH, ^X XXX XXX 1XX XXX XX1] U 2005, 0000,0261,7537,0123 ;1443 OUTC [CLR_CPFF] ; Clear the NOT CPFF in Control chips. ;1444 = ;1445 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 40 ; BASE .MCD [242,1110] Power Up ;1446 ; Now initialize the SI registers. Since the CCR and MSER may not always ;1447 ; be implemented, an abort must not alter this sequence. RESET5 is used to ;1448 ; guarantee abort control. ;1449 ;1450 PWR-UP3: U 0123, 0000,0530,7076,0125 ;1451 LMSTK [PWR-UP4, RE] ; Return to PWR-UP4 if abort on CCR. ;1452 U 0125, 0000,0470,1476,0132 ;1453 LLCM.W [031, RE] ; RE <-- 177746, Cache Control Register address. ;1454 U 0132, 0000,0751,7776,0155 ;1455 AWD.W [RE] ; Stuff CCR address into OL. MMU is off. ;1456 ;1457 LLSW.W [001, RB], ; Flush the Cache, all zeros in other bits. U 0155, 0000,0460,0073,0024 ;1458 NAF/RESET5 ; Let abort occur un-noticed. ;1459 PWR-UP4: U 0161, 0000,0771,7776,0171 ;1460 AW [RE] ; RE = 177744, Memory System Error Register. ;1461 ;1462 CLR.W [PS, PS], ; Clear the MSER. Clear PS for ODT "G" U 0171, 0000,1041,6000,0024 ;1463 NAF/RESET5 ; or Power Up Option 1. ;1464 ;1465 ;=0*0****0 ; Abort to ROM[0] for ODT I/O routines. ;1466 ;RESET5: ; Return from print loop in ODT. ;1467 ; CLR.W [RA, RA], ; For RESET-SUB, clear PIRQ in all chips. ;1468 ; NAF/240 ; For RESET-SUB, abort to ROM[MSTK AND 240]. ;1469 ; ; For SI power up, abort to ROM[240]. ;1470 ; ; For ODT, save code; return. ;1471 ;1472 ; Pop PSW-LOAD from MSTK for ODT "G". ;1473 ;1474 ; Pop P-U-T1 from MSTK on power up. ;1475 ;1476 .NOBIN ;1477 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 41 ; BASE .MCD [242,1110] Power Up Test ;1478 .TOC " Power Up Test" ;1479 ;1480 ; ;1481 ; The purpose of the J-11 power up test is to aid in diagnosing systems ;1482 ; which will not load macro diagnostics or respond to micro ODT. The problem ;1483 ; for the field service technician is in determining if the problem ;1484 ; is with the CPU, system bus, serial line, or console terminal. Therefore, the ;1485 ; goal of the power up test is to aid in isolating the fault to one of ;1486 ; these four causes. ;1487 ; ;1488 ; The method of communicating the information from the test to the field ;1489 ; service tech will be via a set of LEDs on the CPU module. The meaning ;1490 ; of the LEDs will be: ;1491 ; ;1492 ; 1) J-11 chip set and interface logic are functioning. ;1493 ; (Note that functioning does not mean 100% functional) ;1494 ; 2) Processor is able to address memory via system bus. ;1495 ; 3) Serial line responds to read cycle (i.e. does not time out). ;1496 ; 4) Processor is in ODT. ;1497 ; ;1498 ; From these four LEDs the most probable failing unit would be: ;1499 ; ;1500 ; LED ;1501 ; 1 2 3 4 Probable Cause of Problem ;1502 ; --- --- --- --- ------------------------------ ;1503 ; off off off X CPU module, power supply ;1504 ; off off on X CPU module (unusual combination) ;1505 ; off on off X CPU module (unusual combination) ;1506 ; off on on X CPU module (unusual combination) ;1507 ; on off off X Hung bus ;1508 ; on off on X Bus problem ;1509 ; on on off X SLU module ;1510 ; on on on X SLU module, terminal or cable problem ;1511 ; ;1512 ; The normal status during program execution is LEDs 1, 2, and 3 on and ;1513 ; LED 4 off. During ODT all four LEDs are on. ;1514 ; ;1515 ; Once the ODT communication link has been established it will be possible ;1516 ; to gain more information to aid in further diagnosis using standard ;1517 ; techniques (remote diagnosis, techmate, etc.). ;1518 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 42 ; BASE .MCD [242,1110] Power Up Test ;1519 ; ;1520 ; The overall test flow is: ;1521 ; ;1522 ; Assert BINIT for 10 uS with GP write * ;1523 ; Deassert BINIT with GP write * ;1524 ; Wait 90 uS ;1525 ; Clear MMR0 (implicit) ;1526 ; Clear MMR3 (implicit) ;1527 ; Clear PIRQ (explicit) * ;1528 ; Clear FPS ;1529 ; Read POKH and FPA present bit with GP read * ;1530 ; Clear CPU Error Register (implicit) ;1531 ; Set CCR<8> (flush bit) (explicit) * ;1532 ; Clear MSER (explicit) * ;1533 ; Write to CPU Error Register (implicit) ;1534 ; Read CPU Error Register (explicit) * ;1535 ; Clear CPU Error Register ;1536 ; Compare data written to data read ;1537 ; If equal then ;1538 ; Turn on LED 1 with GP write * ;1539 ; Read memory location 00000000 ** ;1540 ; If no abort then ;1541 ; Begin ;1542 ; Read memory location 17777700 * ;1543 ; If abort then ;1544 ; Turn on LED 2 with GP write * ;1545 ; End ;1546 ; Read RCSR (memory location 17777560) * ;1547 ; If no abort then ;1548 ; Turn on LED 3 with GP write * ;1549 ; Read Power Up Options and Resume Power Up ;1550 ; (Vector through 24, Address 173000, ODT, or user supplied boot address) ;1551 ; ;1552 ; * J-11 chipset will stretch for I/O and System Interface must assert ;1553 ; MCONT-L to continue. ;1554 ; ;1555 ; ** J-11 chipset will stretch for I/O if MMISS-L is asserted and System ;1556 ; Interface must assert MCONT-L to continue. ;1557 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 43 ; BASE .MCD [242,1110] Power Up Test ;1558 ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ;1559 ; ;1560 ; Test for part of the MMU and J-11 interface logic ;1561 ; ;1562 ; This test will write a known value to the CPU Error Register using an ;1563 ; OUTR and read it back using an address relocation cycle in order to give ;1564 ; more confidence that the J-11 chip set and interface are partially ;1565 ; functional before testing the system bus. Since the CPU Error Register ;1566 ; is internal to the J-11 chip set it can be addressed without using the ;1567 ; system bus. ;1568 ; ;1569 ; Successful completion of this test lights LED 1 on the CPU module. ;1570 ; ;1571 ;----------------------------------------------------------------------------- ;1572 ;1573 .BIN ;1574 ;1575 P-U-T1: U 0173, 0000,0470,0476,0222 ;1576 LLCM.W [011, RE] ; RE <= CPU Error Register address. ;1577 U 0222, 0000,0250,6776,0237 ;1578 OUTR.W [CPU, RE] ; CPU Error Register <= its address. ;1579 ;1580 AR [RE], ; Initiate read from CPU Error Register U 0237, 0000,0731,7576,0257 ;1581 16-BIT MAP ; using no relocation mode. ;1582 U 0257, 0000,0321,7775,0261 ;1583 RD.W [RD] ; Read its contents into RD. ;1584 U 0261, 0000,1411,7735,0031 ;1585 SUB.W [RE, RD] ; Compare read data with expected data. ;1586 ;1587 =0*0***** ; If read aborts, override to ROM[0] ;1588 ; and eventually enter at ODT-ABORT. U 0031, 0000,0111,5177,0301 ;1589 JAZ [P-U-T2] ; Does the data match ? ;1590 = ;1591 OUTR.W [CPU, RA], ; Re-initialize the CPU Error Register. U 0301, 0000,0250,6772,0331 ;1592 NAF/P-U-T3 ; If no match, skip lighting LED1; ;1593 ; otherwise, take JAZ to light LED 1. ;1594 P-U-T2: U 0323, 0000,0671,1037,0331 ;1595 AWG.W [LED1_ON] ; GP code to light LED 1 next cycle. ;1596 ;1597 ; Finish write to LED 1 if successful. ;1598 P-U-T3: ; Either way, continue P-U-T. U 0331, 0000,0470,3776,0337 ;1599 LLCM.W [077, RE] ; RE <= Address 177700 for next test. ;1600 ;1601 .NOBIN ;1602 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 44 ; BASE .MCD [242,1110] Power Up Test ;1603 ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ;1604 ; ;1605 ; Test to see if the bus works ;1606 ; ;1607 ; The test will assume the following: ;1608 ; 1) ROM[240] (accessed after abort override) will do a return from ;1609 ; micro-subroutine. ;1610 ; 2) Memory location 00000000 will not abort. ;1611 ; 3) Memory location 17777700 (address of R0 in older PDP-11s) will abort. ;1612 ; ;1613 ; The test will read location 0 (no abort should occur) and location ;1614 ; 17777700 (should cause NXM abort). The test is run after the cache has been ;1615 ; flushed to insure that the reads are not cached (i.e. the read cycle passes ;1616 ; through to the system bus) and that no cache parity errors occur. Also, ;1617 ; main memory parity or ECC must be disabled during this test. ;1618 ; ;1619 ; Successful completion of this test lights LED 2 on the CPU module. ;1620 ; If this test is not successful, the Power Up Test is continued without ;1621 ; lighting LED 2. This is to allow for systems which do not conform to ;1622 ; assumptions 2 and 3 above to power up normally. ;1623 ; ;1624 ;----------------------------------------------------------------------------- ;1625 ;1626 .BIN ;1627 ;1628 ; Read memory location 00000000. Failure will be ;1629 ; detected by a bus time out (abort override to ROM[240]). ;1630 ;1631 ; ; Finish write to LED 1 if successful. ;1632 ;P-U-T3: ; Either way, continue P-U-T. ;1633 ; LLCM.W [077, RE] ; RE <= Address 177700 for next test. ;1634 U 0337, 0000,0534,4075,0371 ;1635 LMSTK [P-U-T4, RD] ; MSTK <= Continuation address if ;1636 ; MEM[0] aborts. ;1637 AR [RA], ; Initiate read of MEM[0] U 0371, 0000,0731,7572,0373 ;1638 16-BIT MAP ; using no relocation mode. ;1639 U 0373, 0000,0321,7775,1021 ;1640 RD.W [RD] ; Test for no bus NXM abort. ;1641 ; If this aborts, test SLU without ;1642 ; lighting LED 2. ;1643 ; Read memory location 17777700. ;1644 ; Failure will be detected by no bus time out. ;1645 U 1021, 0000,0534,2735,0241 ;1646 LMSTK [P-U-T5, RD] ; MSTK <= Continuation address if ;1647 ; address 17777700 aborts. ;1648 ;1649 =1*1***** ; If last read aborts, override to ;1650 ; ROM[240] and pop MSTK to P-U-T4. ;1651 AR [RE], ; Generate physical address 17777700 U 0241, 0000,0731,7576,1030 ;1652 16-BIT MAP ; using no relocation mode. ;1653 = ;1654 RD.W [RE], ; Test for bus NXM abort. U 1030, 0000,0321,7776,1101 ;1655 NAF/P-U-T4 ; On abort (successful), go to ROM[240] ;1656 ; and pop MSTK to P-U-T5. ;1657 P-U-T5: ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 45 ; BASE .MCD [242,1110] Power Up Test U 1056, 0000,0671,1237,1101 ;1658 AWG.W [LED2_ON] ; GP code to light LED 2 next cycle. ;1659 ;1660 ; Finish write to LED 2 if successful. ;1661 P-U-T4: ; Either way, continue P-U-T. U 1101, 0000,0471,0776,0242 ;1662 LLCM.W [217, RE] ; RE <= RCSR address for next test. ;1663 ;1664 .NOBIN ;1665 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 46 ; BASE .MCD [242,1110] Power Up Test ;1666 ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ;1667 ; ;1668 ; Read RCSR (Serial line reciever control/status register) ;1669 ; ;1670 ; This test will read location 17777560 (RCSR). If no time out abort occurs ;1671 ; then LED 3 will be turned on and power up will continue. Otherwise, ;1672 ; power up will continue without turning on LED 3. ;1673 ; ;1674 ;----------------------------------------------------------------------------- ;1675 ;1676 .BIN ;1677 ;1678 ; ; Finish write to LED 2 if successful. ;1679 ;P-U-T4: ; Either way, continue P-U-T. ;1680 ; LLCM.W [217, RE] ; RE <= RCSR address for next test. ;1681 ;1682 =1*1***** ; Force ROM[240] abort for last test. U 0242, 0000,0531,2175,1126 ;1683 LMSTK [PWR-UP5, RD] ; MSTK <= Continuation address if ;1684 = ; RCSR aborts. ;1685 ;1686 AR [RE], ; Initiate read from RCSR U 1126, 0000,0731,7576,1127 ;1687 16-BIT MAP ; using no relocation mode. ;1688 U 1127, 0000,0321,7776,1130 ;1689 RD.W [RE] ; Test for RCSR responce. ;1690 ;1691 ; This cycle NOPed on abort. ;1692 AWG.W [LED3_ON], ; GP code to light LED 3 next cycle. U 1130, 0000,0671,1437,0243 ;1693 NAF/PWR-UP5 ; Finish write and decode options. ;1694 ; PWR-UP5 must abort to ROM[240]. ;1695 ;1696 ; End of Power Up Test ;1697 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 47 ; BASE .MCD [242,1110] Power Up Test ;1698 ; Now decode the power up options. ;1699 ;1700 =1*1***** ; Abort to ROM[240] for P-U-T. ;1701 PWR-UP5: ; Finish P-U-T GP write. ;1702 LLD.W [024, RA], ; Load vector address for option 0. U 0243, 0000,0560,1232,0411 ;1703 NAF/P.OPTION ; Dispatch. ;1704 = ;1705 =10********0 ; Option 0. Vector through 24. U 2006, 0037,7771,0440,0000 ;1706 NPLA0 [P.OPTION, ^X XXX XXX XXX XXX 00X] U 2007, 0000,0701,7772,1131 ;1707 ARI.W [RA] ; Shove the address into Output Latch. ;1708 = U 1131, 0000,0321,7767,1132 ;1709 RD.W [PC] ; Read in the PC from the vector. ;1710 U 1132, 0000,0701,7772,0033 ;1711 ARI.W [RA] ; Now get address of the PS. ;1712 ;1713 =0*0***** ; If PC fetch aborts, go to ODT-ABORT. ;1714 RD.W [PS], ; Read it in and ;1715 VECTOR PS PROTECT, ; load PS<13:12>. U 0033, 0000,0321,5740,0107 ;1716 NAF/PSW-LOAD ; End up with common code. ;1717 = ;1718 =10********0 ; Option 1. Enter ODT. U 2010, 0037,7771,0440,0002 ;1719 NPLA0 [P.OPTION, ^X XXX XXX XXX XXX 01X] ;1720 NOP.W [RF, RF], ; TBS U 2011, 0000,1771,7777,1317 ;1721 NAF/ENTER-ODT ; Go to standard ODT entry. ;1722 = ;1723 =10********0 ; Option 2. Boot address is 173000. U 2012, 0037,7771,0440,0004 ;1724 NPLA0 [P.OPTION, ^X XXX XXX XXX XXX 10X] ;1725 LLSW.W [366, PC], ; Generate address 173000. U 2013, 0000,0461,7327,1134 ;1726 NAF/PWR-UP6 ; Join code below. ;1727 = ;1728 =10********0 ; Option 3. User specified boot address. U 2014, 0037,7771,0440,0006 ;1729 NPLA0 [P.OPTION, ^X XXX XXX XXX XXX 11X] U 2015, 0000,0461,7727,1133 ;1730 LLSW.W [376, PC] ; Construct mask for user boot address. ;1731 = U 1133, 0000,1511,7767,1134 ;1732 AND.W [RF, PC] ; Obtain VA<15:9>, starting address. ;1733 ;1734 PWR-UP6: U 1134, 0000,0561,6000,0107 ;1735 LLD.W [340, PS] ; Block interrupts for Options 2 and 3. ;1736 ;1737 =0*0***** ; Abort to ROM[0] for M-TRAP. ;1738 PSW-LOAD: U 0107, 0000,0271,3740,0113 ;1739 OUTS [PSW, PS] ; Update new Control chip PS<7:4> to ;1740 = ; arbitrate interrupt priority and Trace Trap. ;1741 ;1742 =0*0***** ; Abort to ROM[0] for "Power Up". ;1743 PSW-LOAD1: ; Clear SSFF for POWER-UP and ODT "G". ;1744 OUTC [CPY_TBIT-CLR_SSFF], ; Copy ITFF from PS<4>. U 0113, 0000,0261,6637,0044 ;1745 NAF/RE-SYNC ; Wait for Interrupt Blocking Logic ;1746 = ; before ckecking interrupts at IRDF. ;1747 ;1748 .NOBIN ;1749 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 48 ; BASE .MCD [242,1110] ID1 Q-Logic Next Addresses ;1750 .TOC " ID1 Q-Logic Next Addresses" ;1751 ;1752 ; ;1753 ; The Q-Logic is specifically designed to aid the microcode implementation ;1754 ; of the PDP11 Base Instruction Set. In addition, the Q-logic facilitates ;1755 ; interrupt service handling and is also integrally related to the J-11 ;1756 ; Prefetch and Predecode mechanism. ;1757 ; ;1758 ; The Q-Logic's major components consist of the QIR, the QPLA, the ID/RFS ;1759 ; Detection Logic, and the Q-Logic Override Logic. ;1760 ; ;1761 ; The Q-Logic is activated upon detection of certain predefined NAFs ;1762 ; known as the ID (Instruction Decode) addresses. These addresses are ;1763 ; detected by the ID/RFS Detection Logic. When detected, the Q-Logic ;1764 ; Override Logic is enabled to zero bits of the NA based on the output ;1765 ; of the QPLA. The input to the QPLA is the QIR (which normally contains ;1766 ; the Opcode of the instruction currently being executed), the signal ;1767 ; ID1SVC (which indicates a service condition), and DPPC and DPPB ;1768 ; (flip-flops which indicate the status of the Prefetch mechanism). ;1769 ; ;1770 ; ID1 (NAF of 477) is the main Instruction Decode address. This address ;1771 ; is an input into the equation which generates the signal MPRDC-L. ;1772 ; ;1773 ; MPRDC-L = ID1.DATAV.-ID1SVC ;1774 ; ;1775 ; That is, MPRDC-L is asserted only if ID1 (the NAF is 477 and no demand ;1776 ; abort), the data in the Prefetch Buffer is valid (the PPC is then valid), ;1777 ; and there are no service conditions pending. When MPRDC-L is received by ;1778 ; the Data chip, the contents of the Prefetch Buffer is loaded into the IR ;1779 ; and the PC is incremented by two. Thus starts the beginning of the ;1780 ; execution of a new PDP11 macroinstruction. ;1781 ; ;1782 ; The Q-logic can modify the microinstruction flow as shown graphically ;1783 ; on the following page. Thus the next microinstruction can be accessed ;1784 ; from a number of different Next Addresses (NAs). ;1785 ; ;1786 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 49 ; BASE .MCD [242,1110] ID1 Q-Logic Next Addresses ;1787 ; ;1788 ; ;1789 ; ;1790 ; 477 ID1 (Instruction Decode One) 477 ;1791 ; ------------------------------------------------------------------------------- ;1792 ; 400| 440| 460| 467| 470| 471| 474| 475| 476| 477| ;1793 ; | | | | | | | | | | ;1794 ; | | | | | | | | | | ;1795 ; | | | | | | | | | ------- ;1796 ; | | | | | | | | | Misc. ;1797 ; | | | | | | | | | Decode ;1798 ; | | | | | | | | ------- ;1799 ; | | | | | | | | DOP ;1800 ; | | | | | | | | Source ;1801 ; | | | | | | | | Mode ;1802 ; | | | | | | | | Decode ;1803 ; | | | | | | | ------- ;1804 ; | | | | | | | SOP ;1805 ; | | | | | | | Destination ;1806 ; | | | | | | | Mode ;1807 ; | | | | | | | Decode ;1808 ; | | | | | | ------- ;1809 ; | | | | | | DOP ;1810 ; | | | | | | Destination ;1811 ; | | | | | | Mode ;1812 ; | | | | | | Decode ;1813 ; | | | | | ------- ;1814 ; | | | | | SOP ;1815 ; | | | | | Execution ;1816 ; | | | | ------- ;1817 ; | | | | DOP ;1818 ; | | | | Execution ;1819 ; | | | ------- ;1820 ; | | | JOP ;1821 ; | | | Decode ;1822 ; | | ------- ;1823 ; | | Prefetch ;1824 ; | | Buffer ;1825 ; | | Invalid ;1826 ; | ------- ;1827 ; | PPC ;1828 ; | Invalid ;1829 ; ------- ;1830 ; Service ;1831 ; Decode ;1832 ; ;1833 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 50 ; BASE .MCD [242,1110] ID1 Q-Logic Next Addresses ;1834 ; ;1835 ; The following equations specify the resulting NA at ID1 based on the ;1836 ; Q-Logic inputs: ;1837 ; ;1838 ; DOP = The QIR contains a Double Operand instruction ;1839 ; SOP = The QIR contains a Single Operand instruction ;1840 ; JOP = The QIR contains a JMP or JSR instruction ;1841 ; DATAV = The Prefetch Buffer Data is valid ;1842 ; PPCV = The Physical Program Counter is valid ;1843 ; ID1SVC = An interrupt is pending ;1844 ; SM0 = The Source Mode is zero ;1845 ; DM0 = The Desination Mode is zero ;1846 ; ;1847 ; ;1848 ; NA Condition ;1849 ; ---- --------- ;1850 ; ;1851 ; 477 -DOP.-SOP.-JOP.DATAV.PPCV.-ID1SVC ;1852 ; ;1853 ; 476 DOP.-SM0.DATAV.PPCV.-ID1SVC ;1854 ; ;1855 ; 475 SOP.-DM0.DATAV.PPCV.-ID1SVC ;1856 ; ;1857 ; 474 DOP.SM0.-DM0.DATAV.PPCV.-ID1SVC ;1858 ; ;1859 ; 471 SOP.DM0.DATAV.PPCV.-ID1SVC ;1860 ; ;1861 ; 470 DOP.SM0.DM0.DATAV.PPCV.-ID1SVC ;1862 ; ;1863 ; 467 JOP.DATAV.PPCV.-ID1SVC ;1864 ; ;1865 ; 460 -DATAV.PPCV.-ID1SVC ;1866 ; ;1867 ; 440 -PPCV.-ID1SVC ;1868 ; ;1869 ; 400 ID1SVC ;1870 ; ;1871 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 51 ; BASE .MCD [242,1110] Prefetch Pipeline Resynchronization Sequences ;1872 .TOC " Prefetch Pipeline Resynchronization Sequences" ;1873 ;1874 ; ;1875 ; The Q-logic can detect the conditions Physical Program Counter Invalid ;1876 ; (from the flip-flop DPPC), and Prefetch Buffer Invalid (from the flip ;1877 ; -flop DPPB). If these conditions exist at ID1 (477), the Q-Logic ;1878 ; overrides the NA to 440 (PPC Invalid) or 460 (Prefetch Buffer Invalid). ;1879 ; ;1880 ; The signal MKPB-L from the Data chip sets DPPC and DPPB if any one of ;1881 ; the following is detected: ;1882 ; ;1883 ; 1) Explicit writes to the PS ;1884 ; 2) Explicit writes to the MMU registers ;1885 ; 3) Instruction stream overwrites ;1886 ; 4) Writes to the PC ;1887 ; 5) Writes to the Cache Control Register ;1888 ; ;1889 ; DPPB is also set if MABORT-L is asserted during a Prefetch operation, ;1890 ; and remains set if a demand RDI microinstruction is executed. ;1891 ; ;1892 ; ;1893 .BIN ;1894 ;1895 PPC-INVALID: ; Physical Program Counter Invalid. ;1896 =10********0 U 2016, 0037,7777,2000,0000 ;1897 PLA0 [^0 100 000, ^X] U 2017, 0000,1561,7367,0044 ;1898 MOV.W [PC, PC] ; VPC <-- PC. Start from scratch. ;1899 = ;1900 =0*1***** ; Must abort to ROM[40]. ;1901 RE-SYNC: ; Resynchronize and check interrupts. ;1902 RSYNC, ; PPC <-- Relocated(VPC). VPC <-- VPC + 2. U 0044, 0000,1621,7740,0460 ;1903 NAF/IRDF ; Now load Prefetch Buffer. Q-Logic can ;1904 = ; override to 400, Interrupt Service Decode. ;1905 ;1906 DPPC: ; Prefetch Buffer Invalid. ;1907 =10********0 U 2020, 0037,7777,3000,0000 ;1908 PLA0 [^0 110 000, ^X] ; NAF = 460 aborts to ROM[40] as required. ;1909 RDF, ; Demand Prefetch. PB <-- M[PPC]. ;1910 ; PPC <-- Relocated(VPC). VPC <-- VPC + 2. U 2021, 0000,0311,7777,1477 ;1911 NAF/NOP-PF ;1912 = ;1913 ; IR, PIR, QIR <-- [PB]. PB <-- M[PPC]. ;1914 ; PPC <-- Relocated(VPC). VPC <-- VPC + 2. ;1915 ; PC <-- PC + 2. ;1916 ;1477: ; Must be overridable to ID1 (477). ;1917 ;NOP-PF: ; Must also abort to ROM[40]. ;1918 ; NOP.W [RF, PS], ; Do nothing, but allow Predecode to write ;1919 ; ; IR on A-bus<31:16> from Prefetch Buffer. ;1920 ; PREFETCH, ; Initiate a Prefetch request cycle now ;1921 ; ; that all other bus cycles are completed. ;1922 ; NAF/ID1 ; Initiate Predecode. See "ID1 Q-Logic Next ;1923 ; ; Addresses" for possible NAs. ;1924 ;1925 ;1926 .NOBIN ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 52 ; BASE .MCD [242,1110] Prefetch Pipeline Resynchronization Sequences ;1927 ;1928 ; ;1929 ; After this sequence is executed (assuming no aborts or relocation errors), ;1930 ; the prefetch pipeline is said to be in steady state. Steady state is sometimes ;1931 ; represented as follows: ;1932 ; ;1933 ; Pipeline ;1934 ; Level State ;1935 ; -------- ----- ;1936 ; ;1937 ; 1 IR <-- M[Relocated(PC at last predecode)] ;1938 ; ;1939 ; 2 PB <-- M[Relocated(PC)] ;1940 ; PV <-- 1 (Data chip copy) ;1941 ; DATAV <-- 1 (Control chip copy) ;1942 ; ;1943 ; 3 PPC <-- Relocated(PC+2) ;1944 ; PCS<0> <-- 0 (Data chip copy) ;1945 ; PPCV <-- 1 (Control chip copy) ;1946 ; ;1947 ; 4 VPC <-- PC+4 ;1948 ; ;1949 ; ;1950 ; Note that: ;1951 ; DPPB = -DATAV ;1952 ; DPPC = -PPCV ;1953 ; ;1954 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 53 ; BASE .MCD [242,1110] SOPs, DOPs, and Q-Logic Organization ;1955 .TOC " SOPs, DOPs, and Q-Logic Organization" ;1956 ;1957 ; ;1958 ; This section is intended to show, mainly graphically, the operation of ;1959 ; the Q-Logic as it pertains to SOPs and DOPs only. It is included here ;1960 ; because of it's "hidden" effect upon microinstruction sequencing. ;1961 ; Without a good understanding of the Q-Logic it is quite difficult to ;1962 ; follow SOP and DOP execution. For further information, refer to the ;1963 ; J-11 Control Chip Specification and the section entitled "ID1 Q-Logic ;1964 ; Next Addresses" in this document. ;1965 ; ;1966 ; The Q-Logic provides for a fast decode of SOPs and DOPs and for Source ;1967 ; Mode or Destination Mode 0. This information is realized with NA ;1968 ; overrides. That is, the Q-Logic converts an NAF as accesses from the ;1969 ; PLA/ROM array to an NA which accesses the next microinstruction. ;1970 ; ;1971 ; The following symbols are used to illustrate SOP and DOP execution: ;1972 ; ;1973 ; ID1 Instruction Decode one ;1974 ; ID2 Instruction Decode two ;1975 ; ID3 Instruction Decode three ;1976 ; DM0 Destination Mode zero ;1977 ; SM0 Source Mode zero ;1978 ; Dst.adr The Destination Operand's address ;1979 ; Src.adr The Source Operand's address ;1980 ; M[x] The contents of Memory at address x ;1981 ; DOP[x, y] The result of a function of two variables x and y ;1982 ; SOP[x] The result of a function of one variable x ;1983 ; PREFETCH The initiation of a bus cycle to fetch an I-stream word ;1984 ; ;1985 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 54 ; BASE .MCD [242,1110] SOPs, DOPs, and Q-Logic Organization ;1986 ; ;1987 ; The following diagram illustrates the general flow of a SOP. ;1988 ; ;1989 ; ;1990 ; ID1(477) / Q-Logic ;1991 ; ------------------ ;1992 ; | ;1993 ; | ;1994 ; 475 -DM0 | ;1995 ; --------------------<---| ;1996 ; | | ;1997 ; | | ;1998 ; V V DM0 ;1999 ; | ;2000 ; RE <-- M[Dst.adr] | ;2001 ; | ;2002 ; | | ;2003 ; ID3 V (473/471) | (471) ID3 ;2004 ; ------------------------|------------------------ ;2005 ; | | ;2006 ; | | ;2007 ; -DM0 V V DM0 ;2008 ; ;2009 ; M[Dst.adr] <-- SOP[RE] RDST <-- SOP[RDST], ;2010 ; ;2011 ; | PREFETCH ;2012 ; V ;2013 ; | ;2014 ; NOP, | ;2015 ; | ;2016 ; PREFETCH | ;2017 ; | ;2018 ; | | ;2019 ; V ID1(477) / Q-Logic V ;2020 ; ----------------------------------- ;2021 ; ;2022 ; ;2023 ; Upon detection of a SOP in the QIR, the Q-Logic will override the NAF to ;2024 ; ID3 (471) for Destination Mode 0, or 475 otherwise. If 475, the Destination ;2025 ; Operand, in memory, is fetched into scratch register RE and the NAF is set ;2026 ; to ID3 (473 or 471) by microcode. At ID3, microcode then makes a decision as ;2027 ; to Mode 0. If Mode 0, the SOP is executed upon the general register RDST. ;2028 ; A bus cycle is simultaneously conducted to fetch a future I-stream word. ;2029 ; If not Mode 0, the SOP is executed upon the scratch register RE which also ;2030 ; writes the result back to memory. A separate cycle is needed to fetch the ;2031 ; I-stream word. ;2032 ; ;2033 ; There are exceptions to the general flow shown above. For example, CLR(B) ;2034 ; and SXT only write to the destination address; TST(B) only reads. In ;2035 ; addition, some instructions are treated as SOPs by the Q-Logic which aren't ;2036 ; really SOPs at all (e.g. EIS instructions, CSM and MTPS). ;2037 ; ;2038 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 55 ; BASE .MCD [242,1110] SOPs, DOPs, and Q-Logic Organization ;2039 ; ;2040 ; The following diagram illustrates the general flow of a DOP. ;2041 ; ;2042 ; ;2043 ; ID1(477) / Q-Logic ;2044 ; ------------------ ;2045 ; | ;2046 ; | ;2047 ; 476 -SM0 | ;2048 ; --------------------<---| ;2049 ; | | ;2050 ; | | ;2051 ; V V SM0 ;2052 ; | ;2053 ; RF <-- M[Src.adr] | ;2054 ; | ;2055 ; | | ;2056 ; ID2(474) V | -DM0 (474)ID2 ;2057 ; ------------->----------|--->-------------------- ;2058 ; | | ;2059 ; | | ;2060 ; DM0 V V ;2061 ; | ;2062 ; | RE <-- M[Dst.adr] ;2063 ; | ;2064 ; | | ;2065 ; ID3 (470) | (472/470) V ID3 ;2066 ; --------------------------------|-------------------------------- ;2067 ; SM0.DM0 | -SM0.DM0 | | SM0.-DM0 | -SM0.-DM0 ;2068 ; | | | | ;2069 ; | | | V ;2070 ; | | | ;2071 ; | | | M[Dst.adr] <-- DOP[RF, RE] ;2072 ; | | V ;2073 ; | | | ;2074 ; | | M[Dst.adr] <-- DOP[RSRC, RE] | ;2075 ; | V | ;2076 ; | | | ;2077 ; | RDST <-- DOP[RF, RDST], | | ;2078 ; | | | ;2079 ; | PREFETCH | | ;2080 ; V V V ;2081 ; | ;2082 ; RDST <-- DOP[RSRC, RDST], | NOP, NOP, ;2083 ; | ;2084 ; PREFETCH | PREFETCH PREFETCH ;2085 ; | ;2086 ; | | | | ;2087 ; V ID1(477) V Q-Logic V ID1(477) V ;2088 ; ------------------------------------------------------------------- ;2089 ; ;2090 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 56 ; BASE .MCD [242,1110] SOPs, DOPs, and Q-Logic Organization ;2091 ; ;2092 ; Upon detection of a DOP in the QIR at ID1, the Q-Logic overrides to 476, ;2093 ; if the Source Mode is not 0, to ID2 (474) if the Source Mode is 0 but the ;2094 ; Destination Mode is not 0, or to ID3 (470) if both Modes are 0. At 476, ;2095 ; the Source Operand, in memory, is fetch into scratch register RF and the NAF ;2096 ; is set to ID2 (474) by microcode. At ID2, the Q-logic will override to ;2097 ; ID3 (470) if the Destination Mode is 0. If the Q-logic does not override, ;2098 ; the Destination Operand, in memory, is fetch into scratch register RE and the ;2099 ; NAF is set to ID3 (472/470) by microcode. At ID3, microcode then makes ;2100 ; decisions as to where to locate the two operands. If the Destination Mode is ;2101 ; not 0, the result of the DOP operation is written back to memory. A separate ;2102 ; bus cycle is needed to fetch the future I-stream word. If the Destination ;2103 ; Operand is a general register, the bus can simultaneously be used to fetch ;2104 ; from the I-stream. ;2105 ; ;2106 ; There are exceptions to the general flow shown above. For example, MOV(B) ;2107 ; only writes to the destination address; CMP(B) and BIT(B) only read. In ;2108 ; addition, if the destination is the PC, a PREFETCH cannot occur the same cycle. ;2109 ; ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 57 ; BASE .MCD [242,1110] DOP Source Mode Decode ;2110 .TOC " DOP Source Mode Decode" ;2111 ;2112 ; ;2113 ; This code is executed for Double Operand instructions (DOPs) only, ;2114 ; and then only if the Source Mode is not zero. This code fetches ;2115 ; the source operand according to the mode and register specified ;2116 ; in bits<11:6> of the macroinstruction. ;2117 ; ;2118 ; The last microinstruction executed had an NAF of ID1 (477). This ;2119 ; initiated a Predecode operation and enabled the Q-Logic. The Q-Logic ;2120 ; detected a DOP with a Source Mode not equal to zero and therefore ;2121 ; zeroed NA<0> only indicating that Source Mode addressing must be done. ;2122 ; ;2123 ; ;2124 ; Entry conditions: ;2125 ; ;2126 ; NA = 476 ;2127 ; QIR contains Opcode (DOP) ;2128 ; PIR contains Opcode (DOP) ;2129 ; ;2130 ; Exit conditions: ;2131 ; ;2132 ; NAF = 474 (ID2) ;2133 ; RF<7:0> contains source operand for byte operations ;2134 ; RF<15:0> contains source operand for word operations ;2135 ; ;2136 ; Method: ;2137 ; ;2138 ; PLAs are used almost exclusively to separate the various addressing ;2139 ; modes and provide necessary byte to word overrides. ;2140 ; ;2141 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 58 ; BASE .MCD [242,1110] Source Mode 1 ;2142 .TOC " Source Mode 1" ;2143 ;2144 ; ;2145 ; Mode 1: ;2146 ; ;2147 ; Register specifies operand address. ;2148 ; ;2149 ; Do: ;2150 ; AR [RSRC] ; Relocate operand address. ;2151 ; RD.() [RF], ; Read byte or word operand. ;2152 ; NAF/ID2 ; Do second instruction decode. ;2153 ; ;2154 ; ;2155 ; ;2156 .BIN ;2157 ;2158 SRC-MODE-1: ; Relocate operand address for Mode 1. ;2159 =10********0 U 2022, 0037,0777,3700,1000 ;2160 PLA0 [^0 111 110, ^X XXX 001 XXX XXX XXX] ;2161 AR [RSRC], ; ODD TRAP enabled for word OPs (WRD-OVR). U 2023, 0000,0731,7747,0576 ;2162 NAF/576 ; SRC-RD-X. Finish bus cycle. ;2163 = ;2164 SRC-RD-X: ; Read operand or operand address. ;2165 =10********0 U 2024, 0437,7777,7300,0000 ;2166 PLA0 [^1 11X 110, ^X] ;2167 RD.B [RF], ; RD.W for word OP (WRD-OVR) or address (ODD-OVR). U 2025, 0000,0327,7777,0474 ;2168 NAF/474 ; ID2. Do second decode. NAF override (ODD-OVR) to ;2169 = ; SRC-ADDR-X (464) for indirect, Modes 3,5, or 7. ;2170 ;2171 WRD-OVR-1: ; Detect Word SOPs or DOPs, EIS instructions, and CSM. ;2172 =10********0 U 2026, 4527,7777,3200,0000 ;2173 PLA0 [^X 11X 1X0, ^0 XXX XXX XXX XXX XXX] ; See NOTE 1. ;2174 BYTE --> WORD, ; Force word Read or Address increment by two. ;2175 ODD TRAP, ; Force ODD TRAP enable for Address instructions. U 2027, 0000,1771,7377,1777 ;2176 NAF/1777 ; Do not alter NAF. ;2177 = ;2178 WRD-OVR-2: ; Detect SUB (subtract is a word operation). ;2179 =10********0 U 2030, 5520,7777,2216,0000 ;2180 PLA0 [^X 1XX 1X0, ^1 110 XXX XXX XXX XXX] ; See NOTE 2. ;2181 BYTE --> WORD, ; Force word Read or Address increment by two. ;2182 ODD TRAP, ; Force ODD TRAP enable for Address instructions. U 2031, 0000,1771,7377,1777 ;2183 NAF/1777 ; Do not alter NAF. ;2184 = ;2185 ;2186 .NOBIN ;2187 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 59 ; BASE .MCD [242,1110] Source Mode 2 ;2188 .TOC " Source Mode 2" ;2189 ;2190 ; ;2191 ; Mode 2: ;2192 ; ;2193 ; Register specifies operand address. ;2194 ; Register is post-autoincremented. ;2195 ; ;2196 ; Do: ;2197 ; ARI.() [RSRC] ; Relocate operand address and autoincrement. ;2198 ; RD.() [RF], ; Read byte or word operand. ;2199 ; NAF/ID2 ; Do second instruction decode. ;2200 ; ;2201 ; Or: ;2202 ; RDI [RF], ; Read I-stream word for Mode 27. ;2203 ; NAF/ID2 ; Go directly to second decode. ;2204 ; ;2205 ; ;2206 ; ;2207 .BIN ;2208 ;2209 SRC-MODE-2: ; Relocate operand address for Mode 2. ;2210 =10********0 U 2032, 0037,0777,3700,2000 ;2211 PLA0 [^0 111 110, ^X XXX 010 XXX XXX XXX] ;2212 ARI.B [RSRC], ; Word overrides cause ODD TRAP to be enabled ;2213 ; and increment by two not one (WRD-OVR). ;2214 LD MMR1, ; MMR1 records the amount. U 2033, 0000,0704,7747,0576 ;2215 NAF/576 ; SRC-RD-X. Finish bus cycle. ;2216 = ;2217 ;SRC-RD-X: ; Read operand or operand address. ;2218 ;=10********0 ;2219 ;PLA0 [^1 11X 110, ^X] ;2220 ; RD.B [RF], ; RD.W for word OP (WRD-OVR) or address (ODD-OVR). ;2221 ; NAF/474 ; ID2. Do second decode. NAF override (ODD-OVR) to ;2222 ;= ; SRC-ADDR-X (464) for indirect, Modes 3,5, or 7. ;2223 ;2224 SRC-MODE-27-37: ; Do I-stream read for Modes 27, or 37. ;2225 =10********0 U 2034, 0037,1077,3700,2700 ;2226 PLA0 [^0 111 110, ^X XXX 01X 111 XXX XXX] ;2227 RDI [RF+], ; Override both ARI and RSRC and ;2228 ; read Prefetch Buffer instead. U 2035, 0000,0301,7745,0474 ;2229 NAF/474 ; Go to ID2 for Mode 2, or ;2230 = ; SRC-ADDR-X (464) for Mode 3 (566 AND 474). ;2231 ;2232 WRD-OVR-3: ; Detect R6 (SP) and increment/decrement by two. ;2233 =10********0 U 2036, 0037,6077,3700,0600 ;2234 PLA0 [^0 111 110, ^X XXX XX0 110 XXX XXX] ;2235 BYTE --> WORD, ; Force Address increment/decrement by two. U 2037, 0000,1771,7777,1777 ;2236 NAF/1777 ; Do not alter NAF. ;2237 = ;2238 ;WRD-OVR-1: ; Detect Word SOPs or DOPs, EIS instructions, and CSM. ;2239 ;=10********0 ;2240 ;PLA0 [^X 11X 1X0, ^0 XXX XXX XXX XXX XXX] ; See NOTE 1. ;2241 ; BYTE --> WORD, ; Force word Read or Address increment by two. ;2242 ; ODD TRAP, ; Force ODD TRAP enable for Address instructions. ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 60 ; BASE .MCD [242,1110] Source Mode 2 ;2243 ; NAF/1777 ; Do not alter NAF. ;2244 ;= ;2245 ;WRD-OVR-2: ; Detect SUB (subtract is a word operation). ;2246 ;=10********0 ;2247 ;PLA0 [^X 1XX 1X0, ^1 110 XXX XXX XXX XXX] ; See NOTE 2. ;2248 ; BYTE --> WORD, ; Force word Read or Address increment by two. ;2249 ; ODD TRAP, ; Force ODD TRAP enable for Address instructions. ;2250 ; NAF/1777 ; Do not alter NAF. ;2251 ;= ;2252 ;2253 .NOBIN ;2254 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 61 ; BASE .MCD [242,1110] Source Mode 3 ;2255 .TOC " Source Mode 3" ;2256 ;2257 ; ;2258 ; Mode 3: ;2259 ; ;2260 ; Register specifies pointer to operand address. ;2261 ; Register is post-autoincremented. ;2262 ; ;2263 ; Do: ;2264 ; ARI.W [RSRC] ; Relocate pointer and autoincrement. ;2265 ; RD.W [RF] ; Read word length operand address. ;2266 ; AR [RF] ; Relocate operand address. ;2267 ; RD.() [RF], ; Read byte or word operand. ;2268 ; NAF/ID2 ; Do second instruction decode. ;2269 ; ;2270 ; Or: ;2271 ; RDI [RF] ; Read I-stream word for Mode 37. ;2272 ; AR [RF] ; Relocate operand address. ;2273 ; RD.() [RF], ; Read byte or word operand. ;2274 ; NAF/ID2 ; Do second instruction decode. ;2275 ; ;2276 ; ;2277 ; ;2278 .BIN ;2279 ;2280 SRC-MODE-3: ; Relocate pointer for Mode 3. ;2281 =10********0 U 2040, 0037,0777,3700,3000 ;2282 PLA0 [^0 111 110, ^X XXX 011 XXX XXX XXX] ;2283 ARI.W [RSRC], ; Always increment by two. ;2284 LD MMR1, ; MMR1 records the amount. ;2285 ODD TRAP, ; Must be a word address. U 2041, 0000,0700,7347,0566 ;2286 NAF/566 ; SRC-RD-0. Finish first bus cycle. ;2287 = ;2288 ;SRC-RD-X: ; Read operand or operand address. ;2289 ;=10********0 ;2290 ;PLA0 [^1 11X 110, ^X] ;2291 ; RD.B [RF], ; RD.W for word OP (WRD-OVR) or address (ODD-OVR). ;2292 ; NAF/474 ; ID2. Do second decode. NAF override (ODD-OVR) to ;2293 ;= ; SRC-ADDR-X (464) for indirect, Modes 3,5, or 7. ;2294 ;2295 ; Turns on at SRC-RD-0 (566) or SRC-ADDR-0 (564). ;2296 ODD-OVR: ; Override for operand address fetch. ;2297 =10********0 U 2042, 0137,6777,7200,1000 ;2298 PLA0 [^1 110 1X0, ^X XXX XX1 XXX XXX XXX] ; Any odd mode. ;2299 BYTE --> WORD, ; Do word read at SRC-RD-0. ;2300 ODD TRAP, ; Enable ODD TRAP at SRC-ADDR-0. U 2043, 0000,1771,7377,1767 ;2301 NAF/1767 ; Clear NAF<3> to indicate first bus cycle. ;2302 = ; Go to 464 (SRC-ADDR-X) or 566 (SRC-RD-0). ;2303 ;2304 ;SRC-MODE-27-37:; Do I-stream read for Modes 27, or 37. ;2305 ;=10********0 ;2306 ;PLA0 [^0 111 110, ^X XXX 01X 111 XXX XXX] ;2307 ; RDI [RF+], ; Override both ARI and RSRC and ;2308 ; ; read Prefetch Buffer instead. ;2309 ; NAF/474 ; Go to ID2 for Mode 2, or ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 62 ; BASE .MCD [242,1110] Source Mode 3 ;2310 ;= ; SRC-ADDR-X (464) for Mode 3 (566 AND 474). ;2311 ;2312 SRC-ADDR-X: ; Relocate operand or pointer address. ;2313 =10********0 U 2044, 4037,7777,3200,0000 ;2314 PLA0 [^X 110 100, ^X] ;2315 AR [RF], ; ODD TRAP with (WRD-OVR), or indirect (ODD-OVR). U 2045, 0000,0731,7777,0576 ;2316 NAF/576 ; SRC-RD-X for last reference, or ;2317 = ; SRC-RD-0 (566) for indirect reference (ODD-OVR). ;2318 ;2319 ;SRC-RD-X: ; Read operand or operand address. ;2320 ;=10********0 ;2321 ;PLA0 [^1 11X 110, ^X] ;2322 ; RD.B [RF], ; RD.W for word OP (WRD-OVR) or address (ODD-OVR). ;2323 ; NAF/474 ; ID2. Do second decode. NAF override (ODD-OVR) to ;2324 ;= ; SRC-ADDR-X (464) for indirect, Modes 3,5, or 7. ;2325 ;2326 ;WRD-OVR-1: ; Detect Word SOPs or DOPs, EIS instructions, and CSM. ;2327 ;=10********0 ;2328 ;PLA0 [^X 11X 1X0, ^0 XXX XXX XXX XXX XXX] ; See NOTE 1. ;2329 ; BYTE --> WORD, ; Force word Read or Address increment by two. ;2330 ; ODD TRAP, ; Force ODD TRAP enable for Address instructions. ;2331 ; NAF/1777 ; Do not alter NAF. ;2332 ;= ;2333 ;WRD-OVR-2: ; Detect SUB (subtract is a word operation). ;2334 ;=10********0 ;2335 ;PLA0 [^X 1XX 1X0, ^1 110 XXX XXX XXX XXX] ; See NOTE 2. ;2336 ; BYTE --> WORD, ; Force word Read or Address increment by two. ;2337 ; ODD TRAP, ; Force ODD TRAP enable for Address instructions. ;2338 ; NAF/1777 ; Do not alter NAF. ;2339 ;= ;2340 ;2341 .NOBIN ;2342 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 63 ; BASE .MCD [242,1110] Source Mode 4 ;2343 .TOC " Source Mode 4" ;2344 ;2345 ; ;2346 ; Mode 4: ;2347 ; ;2348 ; Register is pre-autodecremented. ;2349 ; Register specifies operand address. ;2350 ; ;2351 ; Do: ;2352 ; ARD.() [RSRC] ; Decrement address by one or two. ;2353 ; AR [RSRC] ; Relocate operand address. ;2354 ; RD.() [RF], ; Read byte or word operand. ;2355 ; NAF/ID2 ; Do second instruction decode. ;2356 ; ;2357 ; Or: (for Mode 47) ;2358 ; ARD.W [RSRC] ; Decrement address by two. ;2359 ; MOV.W [PC, PC] ; Load VPC. ;2360 ; RSYNC ; Relocate new VPC to PPC. ;2361 ; RD.() [RF], ; Read byte or word operand. PPC is address. ;2362 ; NAF/ID2 ; Do second instruction decode. ;2363 ; ;2364 ; ;2365 ; ;2366 .BIN ;2367 ;2368 SRC-MODE-4: ; Decrement address for Mode 4. ;2369 =10********0 U 2046, 0037,0777,3700,4000 ;2370 PLA0 [^0 111 110, ^X XXX 100 XXX XXX XXX] ;2371 ARD.B [RSRC], ; Word OPs decrement by two (WRD-OVR). ;2372 LD MMR1, ; MMR1 records the amount. ;2373 NO ABORTS, ; Disable aborts. Decrement and load MMR1 only. U 2047, 0000,0714,7547,0564 ;2374 NAF/564 ; SRC-ADDR-0. Go relocate operand address. ;2375 = ; SRC-RSYNC if Mode 47 (SRC-MODE-47-57). ;2376 ;2377 SRC-MODE-47-57: ; RSYNC (NAF) override for Modes 47, and 57. ;2378 =10********0 U 2050, 0037,1077,3700,4700 ;2379 PLA0 [^0 111 110, ^X XXX 10X 111 XXX XXX] ;2380 BYTE --> WORD, ; Decrement PC by two. U 2051, 0000,1771,7777,0060 ;2381 NAF/SRC-RSYNC ; Override 564 to do RSYNC. ;2382 = ;2383 =0*0***0*00 ; Must override from 0564. ;2384 SRC-RSYNC: U 0060, 0000,1561,7367,1135 ;2385 MOV.W [PC, PC] ; ARD does not load VPC. Update VPC. ;2386 = ;2387 RSYNC, ; Relocate new VPC and drive PPC next cycle. ;2388 ; Must provide correct address if RDI is ;2389 ; executed in "Destination Mode Decode". U 1135, 0000,1621,7740,0566 ;2390 NAF/566 ; SRC-RD-0. Read operand or operand address. ;2391 ;2392 ;SRC-ADDR-X: ; Relocate operand or pointer address. ;2393 SRC-ADDR-0: ; Override RF to RSRC for Mode 4, first reference Mode 5. ;2394 =10********0 U 2052, 0037,1777,7200,4000 ;2395 PLA0 [^1 110 100, ^X XXX 10X XXX XXX XXX] ;2396 AR [RSRC], ; ODD TRAP with (WRD-OVR), or indirect (ODD-OVR). ;2397 SOVFF, ; Check for Yellow Stack Overflow Trap. ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 64 ; BASE .MCD [242,1110] Source Mode 4 U 2053, 0000,0731,6747,0576 ;2398 NAF/576 ; SRC-RD-X for last reference, or ;2399 = ; SRC-RD-0 (566) for indirect reference (ODD-OVR). ;2400 ;2401 ;SRC-RD-X: ; Read operand or operand address. ;2402 ;=10********0 ;2403 ;PLA0 [^1 11X 110, ^X] ;2404 ; RD.B [RF], ; RD.W for word OP (WRD-OVR) or address (ODD-OVR). ;2405 ; NAF/474 ; ID2. Do second decode. NAF override (ODD-OVR) to ;2406 ;= ; SRC-ADDR-X (464) for indirect, Modes 3,5, or 7. ;2407 ;2408 ;WRD-OVR-3: ; Detect R6 (SP) and increment/decrement by two. ;2409 ;=10********0 ;2410 ;PLA0 [^0 111 110, ^X XXX XX0 110 XXX XXX] ;2411 ; BYTE --> WORD, ; Force Address increment/decrement by two. ;2412 ; NAF/1777 ; Do not alter NAF. ;2413 ;= ;2414 ;WRD-OVR-1: ; Detect Word SOPs or DOPs, EIS instructions, and CSM. ;2415 ;=10********0 ;2416 ;PLA0 [^X 11X 1X0, ^0 XXX XXX XXX XXX XXX] ; See NOTE 1. ;2417 ; BYTE --> WORD, ; Force word Read or Address increment by two. ;2418 ; ODD TRAP, ; Force ODD TRAP enable for Address instructions. ;2419 ; NAF/1777 ; Do not alter NAF. ;2420 ;= ;2421 ;WRD-OVR-2: ; Detect SUB (subtract is a word operation). ;2422 ;=10********0 ;2423 ;PLA0 [^X 1XX 1X0, ^1 110 XXX XXX XXX XXX] ; See NOTE 2. ;2424 ; BYTE --> WORD, ; Force word Read or Address increment by two. ;2425 ; ODD TRAP, ; Force ODD TRAP enable for Address instructions. ;2426 ; NAF/1777 ; Do not alter NAF. ;2427 ;= ;2428 ;2429 .NOBIN ;2430 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 65 ; BASE .MCD [242,1110] Source Mode 5 ;2431 .TOC " Source Mode 5" ;2432 ;2433 ; ;2434 ; Mode 5: ;2435 ; ;2436 ; Register is pre-autodecremented. ;2437 ; Register specifies pointer to operand address. ;2438 ; ;2439 ; Do: ;2440 ; ARD.W [RSRC] ; Decrement address by two. ;2441 ; AR [RSRC] ; Relocate pointer address. ;2442 ; RD.W [RF] ; Read operand address. ;2443 ; ;2444 ; Or: (for Mode 57) ;2445 ; ARD.W [RSRC] ; Decrement address by two. ;2446 ; MOV.W [PC, PC] ; Load VPC. ;2447 ; RSYNC ; Relocate new VPC to PPC. ;2448 ; RD.W [RF] ; Read operand address. PPC is address. ;2449 ; ;2450 ; Then: ;2451 ; AR [RF] ; Relocate operand address. ;2452 ; RD.() [RF], ; Read byte or word operand. ;2453 ; NAF/ID2 ; Do second instruction decode. ;2454 ; ;2455 ; ;2456 ; ;2457 .BIN ;2458 ;2459 SRC-MODE-5: ; Decrement address for Mode 5. ;2460 =10********0 U 2054, 0037,0777,3700,5000 ;2461 PLA0 [^0 111 110, ^X XXX 101 XXX XXX XXX] ;2462 ARD.W [RSRC], ; Always decrement pointer by two. ;2463 LD MMR1, ; MMR1 records the amount. ;2464 NO ABORTS, ; Disable aborts. Decrement and load MMR1 only. U 2055, 0000,0710,7547,0564 ;2465 NAF/564 ; SRC-ADDR-0. Go relocate pointer address. ;2466 = ; SRC-RSYNC if Mode 57 (SRC-MODE-47-57). ;2467 ;2468 ;SRC-MODE-47-57: ; RSYNC (NAF) override for Modes 47, and 57. ;2469 ;=10********0 ;2470 ;PLA0 [^0 111 110, ^X XXX 10X 111 XXX XXX] ;2471 ; BYTE --> WORD, ; Decrement PC by two. ;2472 ; NAF/SRC-RSYNC ; Override 564 to do RSYNC. ;2473 ;= ;2474 ;=0*0***0*00 ; Must override from 0564. ;2475 ;SRC-RSYNC: ;2476 ; MOV.W [PC, PC] ; ARD does not load VPC. Update VPC. ;2477 ;= ;2478 ; RSYNC, ; Relocate new VPC and drive PPC next cycle. ;2479 ; ; Must provide correct address if RDI is ;2480 ; ; executed in "Destination Mode Decode". ;2481 ; NAF/566 ; SRC-RD-0. Read operand or operand address. ;2482 ; ;2483 ;SRC-ADDR-X: ; Relocate operand or pointer address. ;2484 ;SRC-ADDR-0: ; Override RF to RSRC for Mode 4, first reference Mode 5. ;2485 ;=10********0 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 66 ; BASE .MCD [242,1110] Source Mode 5 ;2486 ;PLA0 [^1 110 100, ^X XXX 10X XXX XXX XXX] ;2487 ; AR [RSRC], ; ODD TRAP with (WRD-OVR), or indirect (ODD-OVR). ;2488 ; SOVFF, ; Check for Yellow Stack Overflow Trap. ;2489 ; NAF/576 ; SRC-RD-X for last reference, or ;2490 ;= ; SRC-RD-0 (566) for indirect reference (ODD-OVR). ;2491 ; ;2492 ;SRC-RD-X: ; Read operand or operand address. ;2493 ;=10********0 ;2494 ;PLA0 [^1 11X 110, ^X] ;2495 ; RD.B [RF], ; RD.W for word OP (WRD-OVR) or address (ODD-OVR). ;2496 ; NAF/474 ; ID2. Do second decode. NAF override (ODD-OVR) to ;2497 ;= ; SRC-ADDR-X (464) for indirect, Modes 3,5, or 7. ;2498 ; ;2499 ; ; Turns on at SRC-RD-0 (566) or SRC-ADDR-0 (564). ;2500 ;ODD-OVR: ; Override for operand address fetch. ;2501 ;=10********0 ;2502 ;PLA0 [^1 110 1X0, ^X XXX XX1 XXX XXX XXX] ; Any odd mode. ;2503 ; BYTE --> WORD, ; Do word read at SRC-RD-0. ;2504 ; ODD TRAP, ; Enable ODD TRAP at SRC-ADDR-0. ;2505 ; NAF/1767 ; Clear NAF<3> to indicate first bus cycle. ;2506 ;= ; Go to 464 (SRC-ADDR-X) or 566 (SRC-RD-0). ;2507 ; ;2508 ;SRC-ADDR-X: ; Relocate operand or pointer address. ;2509 ;=10********0 ;2510 ;PLA0 [^X 110 100, ^X] ;2511 ; AR [RF], ; ODD TRAP with (WRD-OVR), or indirect (ODD-OVR). ;2512 ; NAF/576 ; SRC-RD-X for last reference, or ;2513 ;= ; SRC-RD-0 (566) for indirect reference (ODD-OVR). ;2514 ; ;2515 ;SRC-RD-X: ; Read operand or operand address. ;2516 ;=10********0 ;2517 ;PLA0 [^1 11X 110, ^X] ;2518 ; RD.B [RF], ; RD.W for word OP (WRD-OVR) or address (ODD-OVR). ;2519 ; NAF/474 ; ID2. Do second decode. NAF override (ODD-OVR) to ;2520 ;= ; SRC-ADDR-X (464) for indirect, Modes 3,5, or 7. ;2521 ;2522 ;WRD-OVR-1: ; Detect Word SOPs or DOPs, EIS instructions, and CSM. ;2523 ;=10********0 ;2524 ;PLA0 [^X 11X 1X0, ^0 XXX XXX XXX XXX XXX] ; See NOTE 1. ;2525 ; BYTE --> WORD, ; Force word Read or Address increment by two. ;2526 ; ODD TRAP, ; Force ODD TRAP enable for Address instructions. ;2527 ; NAF/1777 ; Do not alter NAF. ;2528 ;= ;2529 ;WRD-OVR-2: ; Detect SUB (subtract is a word operation). ;2530 ;=10********0 ;2531 ;PLA0 [^X 1XX 1X0, ^1 110 XXX XXX XXX XXX] ; See NOTE 2. ;2532 ; BYTE --> WORD, ; Force word Read or Address increment by two. ;2533 ; ODD TRAP, ; Force ODD TRAP enable for Address instructions. ;2534 ; NAF/1777 ; Do not alter NAF. ;2535 ;= ;2536 ;2537 .NOBIN ;2538 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 67 ; BASE .MCD [242,1110] Source Mode 6 ;2539 .TOC " Source Mode 6" ;2540 ;2541 ; ;2542 ; Mode 6: ;2543 ; ;2544 ; Register added to I-stream word is operand address. ;2545 ; ;2546 ; Do: ;2547 ; RDI [RF] ; Read I-stream word from Prefetch Buffer. ;2548 ; ADD.W [RSRC, RF] ; Add offset to calculate operand address. ;2549 ; AR [RF] ; Relocate operand address. ;2550 ; RD.() [RF], ; Read byte or word operand. ;2551 ; NAF/ID2 ; Do second instruction decode. ;2552 ; ;2553 ; ;2554 .BIN ;2555 ;2556 SRC-MODE-6-7: ; Read I-stream word for Modes 6 and 7. ;2557 =10********0 U 2056, 0037,1777,3700,6000 ;2558 PLA0 [^0 111 110, ^X XXX 11X XXX XXX XXX] U 2057, 0000,0301,7777,1136 ;2559 RDI [RF] ; Read I-stream data from Prefetch Buffer. ;2560 = ;2561 ADD.W [RSRC, RF], ; Add offset. Calculate operand or pointer address. U 1136, 0000,1441,6377,0564 ;2562 NAF/564 ; SRC-ADDR-0. Relocate calculated address. ;2563 ;2564 ;SRC-ADDR-X: ; Relocate operand or pointer address. ;2565 ;=10********0 ;2566 ;PLA0 [^X 110 100, ^X] ;2567 ; AR [RF], ; ODD TRAP with (WRD-OVR), or indirect (ODD-OVR). ;2568 ; NAF/576 ; SRC-RD-X for last reference, or ;2569 ;= ; SRC-RD-0 (566) for indirect reference (ODD-OVR). ;2570 ; ;2571 ;SRC-RD-X: ; Read operand or operand address. ;2572 ;=10********0 ;2573 ;PLA0 [^1 11X 110, ^X] ;2574 ; RD.B [RF], ; RD.W for word OP (WRD-OVR) or address (ODD-OVR). ;2575 ; NAF/474 ; ID2. Do second decode. NAF override (ODD-OVR) to ;2576 ;= ; SRC-ADDR-X (464) for indirect, Modes 3,5, or 7. ;2577 ;2578 ;WRD-OVR-1: ; Detect Word SOPs or DOPs, EIS instructions, and CSM. ;2579 ;=10********0 ;2580 ;PLA0 [^X 11X 1X0, ^0 XXX XXX XXX XXX XXX] ; See NOTE 1. ;2581 ; BYTE --> WORD, ; Force word Read or Address increment by two. ;2582 ; ODD TRAP, ; Force ODD TRAP enable for Address instructions. ;2583 ; NAF/1777 ; Do not alter NAF. ;2584 ;= ;2585 ;WRD-OVR-2: ; Detect SUB (subtract is a word operation). ;2586 ;=10********0 ;2587 ;PLA0 [^X 1XX 1X0, ^1 110 XXX XXX XXX XXX] ; See NOTE 2. ;2588 ; BYTE --> WORD, ; Force word Read or Address increment by two. ;2589 ; ODD TRAP, ; Force ODD TRAP enable for Address instructions. ;2590 ; NAF/1777 ; Do not alter NAF. ;2591 ;= ;2592 .NOBIN ;2593 ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 68 ; BASE .MCD [242,1110] Source Mode 7 ;2594 .TOC " Source Mode 7" ;2595 ;2596 ; ;2597 ; Mode 7: ;2598 ; ;2599 ; Register added to I-stream word is pointer to operand address. ;2600 ; ;2601 ; Do: ;2602 ; RDI [RF] ; Read I-stream word from Prefetch Buffer. ;2603 ; ADD.W [RSRC, RF] ; Add offset to calculate pointer to operand address. ;2604 ; AR [RF] ; Relocate pointer. ;2605 ; RD.W [RF] ; Read operand address. ;2606 ; AR [RF] ; Relocate operand address. ;2607 ; RD.() [RF], ; Read byte or word operand. ;2608 ; NAF/ID2 ; Do second instruction decode. ;2609 ; ;2610 ; ;2611 ; ;2612 .BIN ;2613 ;2614 ;SRC-MODE-6-7: ; Read I-stream word for Modes 6 and 7. ;2615 ;=10********0 ;2616 ;PLA0 [^0 111 110, ^X XXX 11X XXX XXX XXX] ;2617 ; RDI [RF] ; Read I-stream data from Prefetch Buffer. ;2618 ;= ;2619 ; ADD.W [RSRC, RF], ; Add offset. Calculate operand or pointer address. ;2620 ; NAF/564 ; SRC-ADDR-0. Relocate calculated address. ;2621 ; ;2622 ;SRC-ADDR-X: ; Relocate operand or pointer address. ;2623 ;=10********0 ;2624 ;PLA0 [^X 110 100, ^X] ;2625 ; AR [RF], ; ODD TRAP with (WRD-OVR), or indirect (ODD-OVR). ;2626 ; NAF/576 ; SRC-RD-X for last reference, or ;2627 ;= ; SRC-RD-0 (566) for indirect reference (ODD-OVR). ;2628 ; ;2629 ;SRC-RD-X: ; Read operand or operand address. ;2630 ;=10********0 ;2631 ;PLA0 [^1 11X 110, ^X] ;2632 ; RD.B [RF], ; RD.W for word OP (WRD-OVR) or address (ODD-OVR). ;2633 ; NAF/474 ; ID2. Do second decode. NAF override (ODD-OVR) to ;2634 ;= ; SRC-ADDR-X (464) for indirect, Modes 3,5, or 7. ;2635 ; ;2636 ; ; Turns on at SRC-RD-0 (566) or SRC-ADDR-0 (564). ;2637 ;ODD-OVR: ; Override for operand address fetch. ;2638 ;=10********0 ;2639 ;PLA0 [^1 110 1X0, ^X XXX XX1 XXX XXX XXX] ; Any odd mode. ;2640 ; BYTE --> WORD, ; Do word read at SRC-RD-0. ;2641 ; ODD TRAP, ; Enable ODD TRAP at SRC-ADDR-0. ;2642 ; NAF/1767 ; Clear NAF<3> to indicate first bus cycle. ;2643 ;= ; Go to 464 (SRC-ADDR-X) or 566 (SRC-RD-0). ;2644 ; ;2645 ;SRC-ADDR-X: ; Relocate operand or pointer address. ;2646 ;=10********0 ;2647 ;PLA0 [^X 110 100, ^X] ;2648 ; AR [RF], ; ODD TRAP with (WRD-OVR), or indirect (ODD-OVR). ; CTL0P3.MCR [242,1110] MICRO2 1H(17) 3-Feb-83 16:32:21 Page 69 ; BASE .MCD [242,1110] Source Mode 7 ;2649 ; NAF/576 ; SRC-RD-X for last reference, or ;2650 ;= ; SRC-RD-0 (566) for indirect reference (ODD-OVR). ;2651 ; ;2652 ;SRC-RD-X: ; Read operand or operand address. ;2653 ;=10********0 ;2654 ;PLA0 [^1 11X 110, ^X] ;2655 ; RD.B [RF], ; RD.W for word OP (WRD-OVR) or address (ODD-OVR). ;2656 ; NAF/474 ; ID2. Do second decode. NAF override (ODD-OVR) to ;2657 ;= ; SRC-ADDR-X (464) for indirect, Modes 3,5, or 7. ;2658 ;2659 ;WRD-OVR-1: ; Detect Word SOPs or DOPs, EIS instructions, and CSM. ;2660 ;=10********0 ;2