;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page    1
;			     Table of Contents									      /REV=
;
; 1	EBM.MIC -- Conditional Assembly Switches for the behavioral Model
; 2	Revision 1.0
; 28		Revision History
; 34		Conditional Assembly Switches
; 46	REV.MIC -- Microcode Revision Number
; 47	Revision 3.0
; 73		Revision History
; 89		Definition for Microcode Revision Number
; 126		Default for Microcode Patch Number
; 150	DEFINE.MIC -- Microword Definitions for NVAX Microcode
; 151	Revision 1.4
; 189		Revision History
; 279		Defaults for Conditional Assembly Switches
; 301		Introduction
; 315		Microword Formats
; 359		Standard Microinstruction Format
; 1031		Special Microinstruction Format
; 1119		Microsequencer Control Fields
; 1207		Simulation and Assembly Control Fields
; 1371		Validity Checks
; 1414	MACRO.MIC -- Macro Definitions
; 1415	Revision 1.1
; 1441		Revision History
; 1480		ALU Macros
; 1737		MEMREQ Macros
; 1770		SHIFT Macros
; 1873		SPECIAL Macros
; 1890		Q, L, V Field Macros
; 1898		MISC Field Macros
; 1921		Microsequencer Control Macros
; 1934		A/B Select Macros
; 1940		Error Macros
; 1953		Simulator Control Macros
; 1978	ALIGN.MIC -- Hardware Entry Point Assignments
; 1979	Revision 1.0
; 2005		Revision History
; 2061		Exception Dispatches
; 2094		Instruction Dispatches
; 2201	POWERUP.MIC -- Powerup Initialization
; 2202	Revision 1.5
; 2228		Revision History
; 2305		Powerup Initialization
; 2386		Powerup Entry Point
; 2429		Console Halt Entry Point
; 2683	INTEXC.MIC -- Interrupts and Exceptions
; 2684	Revision 1.6
; 2710		Revision History
; 3081		Instruction Dispatch Stall
; 3113		Branch Mispredict Microtrap
; 3157		FPD -- PSL<fpd> Set
; 3400		Double Parameter Exceptions -- Memory Management Fault
; 3738		Single Parameter Exceptions -- Arithmetic Traps and Faults
; 3904		Zero Parameter Exceptions -- Reserved Inst, Addr, Operand; Suspended Vector; Trace; KSNV
; 4090		Hardware Error
; 4152		Machine Check Exception
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page    2
;			     Table of Contents									      /REV=
;
; 4374		Interrupts
; 4820		Interrupt and Exception Handling Subroutines
; 5052		CPU Cleanup Subroutine
; 5257	INTLOGADR.MIC -- Integer, Logical, and Address Class Instructions
; 5258	Revision 1.0
; 5284		Revision History
; 5436		TSTx
; 5477		INCx, DECx
; 5535		CLRx
; 5590		CMPx, BITx
; 5648		ADDin, SUBin, BISxn, BICxn, XORxn, ADWC, SBWC
; 5859		MOVx, MOVAx, MOVZxy, PUSHL, PUSHAx, MCOMx, MNEGx
; 5987		ADAWI
; 6077		CVTBW, CVTBL, CVTWL
; 6135		CVTWB, CVTLB, CVTLW
; 6218		ROTL
; 6264		ASHL
; 6390		ASHQ
; 6593	VFIELD.MIC -- Variable-Length Bit Field Instructions
; 6594	Revision 1.1
; 6620		Revision History
; 6713		FFS, FFC, CMPV, CMPZV, EXTV, EXTZV
; 7241		INSV
; 7627	CTRL.MIC -- Control Instructions
; 7628	Revision 1.0
; 7654		Revision History
; 7739		BRx, Bxx, JMP
; 7836		BSBB, BSBW, JSB
; 7904		RSB
; 7945		CASEx
; 8061		SOBGTR, SOBGEQ
; 8111		AOBLSS, AOBLEQ
; 8167		ACBx
; 8275		BBx, BBxS, BBxC, BBxxI
; 8617		BLBx
; 8663	MULDIV.MIC -- Multiply and Divide Instructions
; 8664	Revision 1.2
; 8690		Revision History
; 8795		MULBn, MULWn, MULLn
; 8967		EMUL
; 9112		DIVBn, DIVWn, DIVLn
; 9359		EDIV
; 9864	CALLRET.MIC -- Procedure Call Instructions
; 9865	Revision 1.1
; 9891		Revision History
; 9981		CALLG, CALLS
; 10429 	RET
; 10740 MISC.MIC -- Miscellaneous Instructions
; 10741 Revision 1.0
; 10767 	Revision History
; 10822 	BPT, XFC
; 10894 	HALT
; 10959 	NOP
; 10998 	INDEX
; 11165 	BICPSW, BISPSW
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page    3
;			     Table of Contents									      /REV=
;
; 11241 	MOVPSL
; 11283 	POPR
; 11516 	PUSHR
; 11738 QUEUE.MIC -- Queue Instructions
; 11739 Revision 1.1
; 11765 	Revision History
; 11859 	INSQUE
; 11952 	REMQUE
; 12069 	INSQxI
; 12605 	REMQxI
; 12967 OPSYS.MIC -- Operating System Support Instructions
; 12968 Revision 1.6
; 12994 	Revision History
; 13175 	CHMx
; 13568 	REI
; 14186 	LDPCTX
; 14545 	SVPCTX
; 14789 	PROBEx
; 15053 	MTPR, MFPR
; 17019 CSTRING.MIC -- Character String Instructions
; 17020 Revision 1.0
; 17046 	Revision History
; 17144 	MOVC3, MOVC5
; 18073 	CMPC3, CMPC5
; 18464 	SCANC, SPANC
; 18695 	LOCC, SKPC
; 18890 	String Packup Routine
; 19054 	String Unpack Routine
; 19277 FPOINT.MIC -- Floating Point Instructions
; 19278 Revision 1.0
; 19305 	Revision History
; 19410 	Floating Point Instructions With Single Bus Operand Transfer
; 19411 		MOVF, MNEGF, CVTFi, CVTiF
; 19412 		CVTiD, CVTFD, CVTiG, CVTFG
; 19473 	Floating Point Instructions With Single Bus Operand Transfer, No Destination Write
; 19474 		TSTF
; 19509 	Floating Point Instructions With Double Bus Operand Transfer
; 19510 		MOVD, MOVG, MNEGD, MNEGG
; 19511 		CVTDi, CVTDF, CVTGi, CVTGF
; 19512 		ADDFx, SUBFx, MULFx, DIVFx
; 19587 	Floating Point Instructions With Double Bus Operand Transfer, No Destination Write
; 19588 		CMPF, TSTD, TSTG
; 19627 	Floating Point Instructions With Quadruple Bus Operand Transfer
; 19628 		ADDDx, SUBDx, MULDx, DIVDx, ADDGx, SUBGx, MULGx, DIVGx, CMPD, CMPG
; 19682 	Floating Point Instructions With Quadruple Bus Operand Transfer -- No destination
; 19683 		CMPD, CMPG
; 19720 VECTOR.MIC -- VAX Vector Instructions
; 19721 Revision 1.0
; 19747 	Revision History
; 19900 	Vector Load Instructions
; 19955 	Vector Store Instructions
; 20010 	Vector Gather Instructions
; 20057 	Vector Scatter Instructions
; 20104 	MFVP
; 20147 	MTVP
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page    4
;			     Table of Contents									      /REV=
;
; 20184 	VSYNC
; 20222 	Vector - Vector Operate Instructions
; 20284 	Longword Vector - Scalar Operate Instructions
; 20333 	Quadword Vector - Scalar Operate Instructions
; 20379 	Vector - Vector Compare Instructions
; 20419 	Longword Vector - Scalar Compare Instructions
; 20458 	Quadword Vector - Scalar Compare Instructions
; 20497 	IOTA
; 20535 EMULATE.MIC -- Emulation Support
; 20536 Revision 1.1
; 20562 	Revision History
; 20703 	Normal Emulation (FPD Clear)
; 21075 	Special Emulation (FPD Set)
; 21174 EBMCODE.MIC -- Behavioral Model Support
; 21175 Revision 1.2
; 21201 	Revision History
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page    5
;	EBM.MIC 	     EBM.MIC -- Conditional Assembly Switches for the behavioral Model			      /REV=
;
				;1	.TOC	"EBM.MIC -- Conditional Assembly Switches for the behavioral Model"
				;2	.TOC	"Revision 1.0"
				;3
				;4	;	Shawn Persels
				;5
;6	.nobin
;7	;****************************************************************************
;8	;*									    *
;9	;*  COPYRIGHT (c) 1988, 1989, 1990, 1991, 1992 BY			    *
;10	;*  DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASSACHUSETTS.		    *
;11	;*  ALL RIGHTS RESERVED.						    *
;12	;*									    *
;13	;*  THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED   *
;14	;*  ONLY IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE   *
;15	;*  INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE OR ANY  OTHER   *
;16	;*  COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY   *
;17	;*  OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE IS  HEREBY   *
;18	;*  TRANSFERRED.							    *
;19	;*									    *
;20	;*  THE INFORMATION IN THIS SOFTWARE IS  SUBJECT TO CHANGE WITHOUT NOTICE   *
;21	;*  AND  SHOULD  NOT  BE  CONSTRUED AS	A COMMITMENT BY DIGITAL EQUIPMENT   *
;22	;*  CORPORATION.							    *
;23	;*									    *
;24	;*  DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE  OR  RELIABILITY OF ITS   *
;25	;*  SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.		    *
;26	;*									    *
;27	;****************************************************************************
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page    6
;	EBM.MIC 	     Revision History									      /REV=
;
;28	.TOC	"	Revision History"
;29
;30	; Edit	  Date	 Who	     Description
;31	; ---- --------- ---	---------------------
;32	; (1)1 17-Jul-90 GMU	Initial production microcode.
;33	; (0)0 16-Aug-88 SDP	Trial microcode.
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page    7
;	EBM.MIC 	     Conditional Assembly Switches							      /REV=
;
;34	.TOC	"	Conditional Assembly Switches"
;35
;36
;37	; The following assignments are used as conditional assembly switches during
;38	; microcode assembly.
;39
;40	.SET/PERF.MODEL=	0		; 1 = include special hooks for the performance model
;41
;42	.SET/BEH.MODEL= 	1		; 1 = include special hooks for the behavioral model
;43
;44
				;45	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page    8
;	REV.MIC 	     REV.MIC -- Microcode Revision Number						      /REV=
;
				;46	.TOC	"REV.MIC -- Microcode Revision Number"
				;47	.TOC	"Revision 3.0"
				;48
				;49	;	Mike Uhler
				;50
;51	.nobin
;52	;****************************************************************************
;53	;*									    *
;54	;*  COPYRIGHT (c) 1990, 1991, 1992 BY					    *
;55	;*  DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASSACHUSETTS.		    *
;56	;*  ALL RIGHTS RESERVED.						    *
;57	;*									    *
;58	;*  THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED   *
;59	;*  ONLY IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE   *
;60	;*  INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE OR ANY  OTHER   *
;61	;*  COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY   *
;62	;*  OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE IS  HEREBY   *
;63	;*  TRANSFERRED.							    *
;64	;*									    *
;65	;*  THE INFORMATION IN THIS SOFTWARE IS  SUBJECT TO CHANGE WITHOUT NOTICE   *
;66	;*  AND  SHOULD  NOT  BE  CONSTRUED AS	A COMMITMENT BY DIGITAL EQUIPMENT   *
;67	;*  CORPORATION.							    *
;68	;*									    *
;69	;*  DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE  OR  RELIABILITY OF ITS   *
;70	;*  SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.		    *
;71	;*									    *
;72	;****************************************************************************
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page    9
;	REV.MIC 	     Revision History									      /REV=
;
;73	.TOC	"	Revision History"
;74
;75	; Edit	  Date	 Who	     Description
;76	; ---- --------- ---	---------------------
;77	; (3)0 06-Jun-91 GMU	Increment revision number to 3 to reflect pass 3 changes.
;78	;    1 01-Feb-91 GMU	Symptom: No mechanism for including a non-standard
;79	;				 patch flag in the source.
;80	;			Cure:	 Default the value MICROCODE.NONSTANDARD to zero
;81	;				 in this module.
;82	; (2)0 21-Jan-91 GMU	Increment revision number to 2 to reflect pass 2 changes.
;83	;
;84	;    1 28-Nov-90 GMU	Symptom: No mechanism for including a microcode
;85	;				 patch number in the source.
;86	;			Cure:	 Default the value of MICROCODE.PATCH
;87	;				 to zero in this module.
;88	; (1)0 17-Jul-90 GMU	Initial production microcode.
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   10
;	REV.MIC 	     Definition for Microcode Revision Number						      /REV=
;
;89	.TOC	"	Definition for Microcode Revision Number"
;90
;91
;92	;	The constant MICROCODE.REVISION is the number returned in bits
;93	;	<7:0> of the SID IPR.  At present, this constant is defined as having
;94	;	the following fields:
;95	;
;96	;		 07 06 05 04 03 02 01
;97	;		+--+--+--+--+--+--+--+
;98	;		|DP|	Edit Number  |
;99	;		+--+--+--+--+--+--+--+
;100	;
;101	;	where:
;102	;
;103	;		DP		= Development/Production flag:
;104	;					0 = Production microcode.
;105	;					1 = Development microcode.
;106	;		Edit Number	= Edit number of the microcode.
;107	;
;108	;	For development microcode, the edit number should be incremented any
;109	;	time a change is made that requires a corresponding model change.
;110	;
;111	;	For production microcode, the edit number should be incremented
;112	;	when any change is made to the microcode.
;113
;114
;115	;	Define the two parts of the microcode revision number.
;116
;117	.SET/MICROCODE.DP.FLAG=0		; development/production flag
;118
;119	.SET/MICROCODE.EDIT.NUMBER=3		; microcode edit number
;120
;121
;122	;	Post-process into the final value
;123
;124	.SET/MICROCODE.REVISION=<.OR[	<.SHIFT[<MICROCODE.DP.FLAG>,7]>,
;125					<MICROCODE.EDIT.NUMBER> 	]>
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   11
;	REV.MIC 	     Default for Microcode Patch Number 						      /REV=
;
;126	.TOC	"	Default for Microcode Patch Number"
;127
;128
;129	;	The constant MICROCODE.PATCH is the number of the last required
;130	;	microcode patch.  It can be thought of as a modifier to the
;131	;	microcode revision number.  The constant MICROCODE.PATCH is
;132	;	defaulted to 0 in this module and may be redefined by assembling
;133	;	the microcode with the REV_PATCH.MIC module.
;134	;
;135	;	The constant MICROCODE.NONSTANDARD is a boolean flag that indicates
;136	;	whether this microcode patch is a normal functional patch
;137	;	release or a non-standard (e.g., performance monitoring) patch.
;138	;	The constant is defaulted to 0 in this module and may be
;139	;	redefined by assembling the microcode with the REV_PATCH.MIC
;140	;	module.
;141
;142	;	Default the microcode patch number and the non-standard
;143	;	patch flag to 0.
;144
;145	.DEFAULT/MICROCODE.PATCH=0
;146
;147	.DEFAULT/MICROCODE.NONSTANDARD=0
;148
				;149	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   12
;    DEFINE.MIC 	     DEFINE.MIC -- Microword Definitions for NVAX Microcode				      /REV=
;
				;150	.TOC	"DEFINE.MIC -- Microword Definitions for NVAX Microcode"
				;151	.TOC	"Revision 1.4"
				;152
				;153	;	Bob Supnik, Mike Uhler
				;154
				;155	;	Assembly directives
				;156
				;157	.ecode
				;158	.hexadecimal
				;159	.rtol
				;160	.allmemfields
				;161	.random
				;162	.width/80				; FAKE machine microword length
				;163	; .width/61				; REAL machine microword length
				;164
;165	.nobin
;166	.nocref
;167
;168	;****************************************************************************
;169	;*									    *
;170	;*  COPYRIGHT (c) 1987, 1988, 1989, 1990, 1991, 1992 BY 		    *
;171	;*  DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASSACHUSETTS.		    *
;172	;*  ALL RIGHTS RESERVED.						    *
;173	;*									    *
;174	;*  THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED   *
;175	;*  ONLY IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE   *
;176	;*  INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE OR ANY  OTHER   *
;177	;*  COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY   *
;178	;*  OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE IS  HEREBY   *
;179	;*  TRANSFERRED.							    *
;180	;*									    *
;181	;*  THE INFORMATION IN THIS SOFTWARE IS  SUBJECT TO CHANGE WITHOUT NOTICE   *
;182	;*  AND  SHOULD  NOT  BE  CONSTRUED AS	A COMMITMENT BY DIGITAL EQUIPMENT   *
;183	;*  CORPORATION.							    *
;184	;*									    *
;185	;*  DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE  OR  RELIABILITY OF ITS   *
;186	;*  SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.		    *
;187	;*									    *
;188	;****************************************************************************
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   13
;    DEFINE.MIC 	     Revision History									      /REV=
;
;189	.TOC	"	Revision History"
;190
;191	; Edit	  Date	 Who	     Description
;192	; ---- --------- ---	---------------------
;193	;    4 24-Jul-91 JFB	Symptom: No symbolic constant defined for PCSTS
;194	;			Cure:	 Add IPR.PCSTS
;195	;    3 20-Feb-91 GMU	Symptom: No symbolic constant defined for P1BR and P1LR
;196	;				 bias values.
;197	;			Cure:	 Add P1BR.BIAS, P1LR.BIAS.SHIFTED, P1LR.BIAS.UNSHIFTED.
;198	;    2 28-Jan-91 GMU	Symptom: No symbolic definition for PCSCR PCS enable bit.
;199	;			Cure:	 Add PCSCR.PCS.ENB.
;200	;			Symptom: There is no easy way to extract the microcode
;201	;				 non-standard patch flag from the .ULD/.ULA file.
;202	;			Cure:	 Include the UCODE.NONSTANDARD value in the CONST
;203	;				 field and equate it to the MICROCODE.NONSTANDARD
;204	;				 constant.
;205	;    1 28-Nov-90 GMU	Symptom: There is no easy way to extract the microcode
;206	;				 revision number and the microcode
;207	;				 patch number from the .ULD/.ULA file.
;208	;			Cure:	 Include the UCODE.REVISION and UCODE.PATCH
;209	;				 values in the CONST field and equate them
;210	;				 to the MICROCODE.REVISION and MICROCODE.PATCH
;211	;				 constants.  This allows a program to find the
;212	;				 values by parsing the symbol table at the
;213	;				 end of the .ULD/.ULA.
;214	; (1)0 31-Jul-90 GMU	Initial production microcode.
;215	;
;216	; Begin version 1.0 here
;217	;   48 31-Jul-90 JFB	Add test pins to SEQ.COND/VECTOR field,
;218	;			and create SEQ.COND/TEST_PINS synonym.
;219	;   47 01-Jul-90 GMU	Add MCHK.PMF.CONFIG, SCB.PMF.BASE, ECR bit definitions.
;220	;   46 25-Jun-90 GMU	PCSCR turned out to be read/write after all, so back out
;221	;			edit 41.
;222	;   45 11-Jun-90 GMU	Renumber CPUSTATE registers in A and DST field to match
;223	;			implementation.
;224	;   44 11-Jun-90 GMU	Add MISC/INCR.PERF.COUNT decode.
;225	;   43 06-Jun-90 GMU	More of edit 42.
;226	;   42 05-Jun-90 GMU	Reorder SEQ.COND decodes for implementation.
;227	;   41 08-May-90 GMU	Remove PCSCR as a source in the A field (it is a write-
;228	;			only register).
;229	;   40 01-May-90 GMU	Note that last machine check code is included in ASTLVL.
;230	;   39 23-Apr-90 GMU	Remove artifact for an external vector unit interface.
;231	;   38 12-Apr-90 GMU	Add performance monitoring facility decodes.
;232	;   37 30-Mar-90 GMU	Add validity checks to restrict use of DST field
;233	;			for read-type MRQ commands.
;234	;   36 18-Mar-90 GMU	Rename JTAGCR to PCSCR.
;235	;   35 28-Feb-90 GMU	Remove FBOX.FAULT.CODE.
;236	;   34 23-Feb-90 GMU	Add new CONST.10 constants for MxPR rewrite, remove MXPR
;237	;			constant decodes on the A bus.
;238	;   33 20-Feb-90 GMU	Remove obsolete ALU, MISC, MISC1, and SEQ.COND decodes.
;239	;   32 12-Feb-90 GMU	Add MISC/SIM.IE.INTEXC directive for use in the behavioral
;240	;			model.
;241	;   31 19-Jan-90 GMU	Change definition of K.MXPR.0.31 definition to include
;242	;			bit for CPUID IPR.
;243	;   30 19-Jan-90 GMU	Add IPR.CEFSTS and CEFSTS.RDLK definitions.
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   14
;    DEFINE.MIC 	     Revision History									      /REV=
;
;244	;   29 19-Jan-90 GMU	Remove VMPSL, add CPUID to ASTLVL comment.
;245	;   28 18-Jan-90 GMU	Add SEQ.COND/FBOX.FAULT.CODE.
;246	;   27 16-Jan-90 DGM	Change SEQ.COND field queue decode.  Update comments.
;247	;   26 15-Jan-90 GMU	Add MISC/CLR.VECT.RDY decode.
;248	;   25 09-Jan-90 GMU	Add ISR bit definitions.
;249	;   24 02-Jan-90 GMU	Remove bogus vector opcode and status decodes.
;250	;   23 21-Dec-89 GMU	Add IPR.CACHE definition.
;251	;   22 06-Dec-89 GMU	Continue cleanup.
;252	;   21 01-Dec-89 GMU	Add IPR.ICCS to CONST.10 field.
;253	;   20 17-Nov-89 GMU	Cleanup comments, remove obsolte decodes, note those
;254	;			that should be removed in the future.
;255	;   19 16-Nov-89 GMU	Add ALU/A.MINUS.B.MINUS.1 and B/K.FFFF; remove
;256	;			A/TEMP and DST/TEMP.
;257	;   18 07-Nov-89 GMU	Add new machine check codes.
;258	;   17 03-Nov-89 GMU	Add PSL.TP constant.
;259	;   16 23-Oct-89 GMU	Add PTE.M constant.
;260	;   15 18-Oct-89 GMU	Include validity check in use of FLUSH.PAQ to require
;261	;			MRQ request.
;262	;   14 21-Sep-89 GMU	Add PSL.B0 to DST field.
;263	;   13 11-Sep-89 GMU	Add JTAGCR to A and DST fields; add PROBE.V.RCHK.NOFILL
;264	;			to MRQ field.
;265	;   12 31-Aug-89 GMU	Update Cbox IPR assignments.
;266	;   11 23-Aug-89 GMU	Combine Fbox operand valid decodes into one decode.
;267	;   10 22-Aug-89 GMU	Add TB.TAG.FILL and TB.PTE.FILL commands to MRQ field.
;268	;    9 16-Aug-89 GMU	Remove CLEAR.WRITE.BUFFERS and READ.INT.VECTOR from
;269	;			MRQ field.
;270	;    8 14-Aug-89 GMU	Add new K.MXPR.x constants, rename old ones.
;271	;    7 26-Jul-89 GMU	Change Ibox IPR constant definitions from Cx to Dx.
;272	;    6 19-Jul-89 GMU	Add ECR, ESR to DST, A fields.
;273	;    5 12-Jul-89 GMU	Updated IPR encodings.
;274	;    4 30-Jun-89 DGM	Added FBOX.DISABLED microbranch condition
;275	;    3 08-Feb-89 GMU	Remove C bit.
;276	;    2 22-Nov-88 DB	Add MISC3/F.DEST.CHECK
;277	;    1 23-Aug-88 GMU	Add PM hooks for CASEx.
;278	; (0)0 27-Aug-87 RMS	Trial microcode.
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   15
;    DEFINE.MIC 	     Defaults for Conditional Assembly Switches 					      /REV=
;
;279	.TOC	"	Defaults for Conditional Assembly Switches"
;280
				;281	.bin
				;282
				;283	;	The following assignments specify conditional assembly switches for the
				;284	;	microcode assembly.  They are specified as defaults here, and may be
				;285	;	redefined earlier in the assembly (in Exx.MIC) with explicit
				;286	;	.SET directives.
				;287
				;288	.DEFAULT/PERF.MODEL=	0	; 1 = include special hooks for the performance model
				;289					; 0 = exclude special hooks for the performance model
				;290
				;291	.DEFAULT/BEH.MODEL=	0	; 1 = include special hooks for the behavioral model
				;292					; 0 = exclude special hooks for the behavioral model
				;293
				;294	;	The following definitions post process those above and should never be
				;295	;	changed alone.
				;296
				;297	.SET/NOT.PERF.MODEL=<.NOT[ <PERF.MODEL>]> ; logical complement for use in validity checks
				;298	.SET/NOT.BEH.MODEL=<.NOT[ <BEH.MODEL>]>   ; logical complement for use in validity checks
				;299
;300	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   16
;    DEFINE.MIC 	     Introduction									      /REV=
;
;301	.TOC	"	Introduction"
;302
;303	;	The NVAX microword consists of 61 bits divided into two major sections.
;304	;	Bits <60:15> control the data path and are encoded into two formats.
;305	;	Bits <14:0> control the microsequencer and are encoded into two formats.
;306	;
;307	;	In addition to the bits in the real microword, there are additional
;308	;	bits defined which provide assembly-time validity checking for the
;309	;	microcode, plus support for data-dependent decisions in the performance
;310	;	model.	The additional bits are stripped out by the allocator during
;311	;	pass 3 of the allocation process.
;312	;
;313	;	The formats are defined in the Microinstruction Formats Chapter of the NVAX
;314	;	CPU Functional Specification.
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   17
;    DEFINE.MIC 	     Microword Formats									      /REV=
;
;315	.TOC	"	Microword Formats"
;316
;317	;	The microword formats on this page represent the final microword after
;318	;	post-processing by the allocator.
;319	;
;320	;	Data path control, standard format
;321	;
;322	;	 6|5 5 5 5|5 5 5 5|5 5 4 4|4 4 4 4|4 4 4 4|3 3 3 3|3 3 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1
;323	;	 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5
;324	;	+-+---------+---------+-+-----+-+---------+---------+-+-+-+-----------+-----------+---------+
;325	;	|0|   ALU   |	MRQ   |Q| SHF |0|   VAL   |    B    |L|W|V|    DST    |     A	  |  MISC   |
;326	;	+-+---------+---------+-+-----+-+---------+---------+-+-+-+-----------+-----------+---------+
;327	;				      |1|POS|	 CONST	    | MISC not equal CONST.10
;328	;				      +-+---+---------------+
;329	;				      |1|     CONST.10	    | MISC equal CONST.10
;330	;				      +-+-------------------+
;331	;
;332	;	Data path control, special format
;333	;
;334	;	 6|5 5 5 5|5 5 5 5|5 5 4 4|4 4 4 4|4 4 4 4|3 3 3 3|3 3 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1
;335	;	 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5
;336	;	+-+---------+---------+-------+-+-------+-+---------+-+-+-+-----------+-----------+---------+
;337	;	|1|   ALU   |	MRQ   | MISC1 |0| MISC2 |D|    B    |L|W|V|    DST    |     A	  |  MISC   |
;338	;	+-+---------+---------+-------+-+-------+-+---------+-+-+-+-----------+-----------+---------+
;339	;				      |1|POS|	 CONST	    | MISC not equal CONST.10
;340	;				      +-+---+---------------+
;341	;				      |1|     CONST.10	    | MISC equal CONST.10
;342	;				      +-+-------------------+
;343	;
;344	;	Microsequencer control, jump format
;345	;
;346	;	 1 1 1|1 1    |       |
;347	;	 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
;348	;	+-+-+---+---------------------+
;349	;	|0|S|MUX|	   J	      |
;350	;	+-+-+---+---------------------+
;351	;
;352	;	Microsequencer control, branch format
;353	;
;354	;	 1 1 1|1 1    |       |
;355	;	 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
;356	;	+-+-+---------+---------------+
;357	;	|1|S|SEQ.COND |    BR.OFF     |
;358	;	+-+-+---------+---------------+
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   18
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;359	.TOC	"	Standard Microinstruction Format"
;360
;361	;	The fields for the standard microinstruction are:
;362	;
;363	;	FORMAT/ 	STANDARD
;364	;	ALU/		ALU operation
;365	;	MRQ/		Mbox request
;366	;	Q/		Q latch update control
;367	;	SHF/		Shift operation
;368	;	LIT/		B operand control, as follows:
;369	;	    LIT/0:
;370	;		VAL/	Shift count value
;371	;		B/	B port select
;372	;	    LIT/1:
;373	;		POS/	Contant position	\ If MISC field does not
;374	;		CONST/	8-bit constant value	/ contain CONST.10.BIT
;375	;		CONST.10/ 10-bit constant value   If MISC field contains CONST.10.BIT
;376	;	L/		Length control
;377	;	W/		Wbus driver control
;378	;	V/		VA latch update control
;379	;	DST/		Wbus destination
;380	;	A/		ALU A port select
;381	;	MISC/		Miscellaneous
;382
;383	;	This field defines foramt of the current microinstruction.
;384
;385	FORMAT/=<60>,.DEFAULT=<FORMAT/STANDARD>
;386
;387		STANDARD		=  0	; select the standard format
;388		SPECIAL 		=  1	; select the special format
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   19
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;389
;390	;	Standard microinstruction format, continued.
;391
;392	;	This field defines the ALU operation.  Inputs to the ALU are selected by the A and B field decodes.
;393	;	The output of the ALU can drive the VA (based on V control) and/or the Wbus (based on W control).
;394	;	The ALU condition codes are length dependent (based on DL and L control) and can drive the PSL logic
;395	;	(based on W control).
;396
;397	ALU/=<59:55>,.DEFAULT=<ALU/0>
;398
;399	;		Function	  Val		Operation			  Comments and restrictions
;400	;	-----------------------  ----	---------------------------	----------------------------------------------------
;401		PASS.A			=  00	; A
;402		PASS.B			=  01	; B
;403	;				=  02
;404	;				=  03
;405	;				=  04
;406	;				=  05
;407	;				=  06
;408	;				=  07
;409		A.AND.B 		=  08	; A .AND. B
;410		A.AND.NOT.B		=  09	; A .AND. (.NOT. B)
;411		A.OR.B			=  0A	; A .OR. B
;412	;				=  0B
;413		A.XOR.B 		=  0C	; A .XOR. B
;414		NOT.A.AND.B		=  0D	; (.NOT. A) AND B
;415	;				=  0E
;416		A.MINUS.B.MINUS.1	=  0F	; A - B - 1			A + (.NOT. B)
;417
;418		A.PLUS.1		=  10	; A + 1
;419		A.PLUS.B		=  11	; A + B
;420		A.PLUS.B.PLUS.1 	=  12	; A + B + 1
;421	;				=  13
;422		B.MINUS.A		=  14	; B - A 			B + (.NOT. A) + 1
;423		A.MINUS.B		=  15	; A - B 			A + (.NOT. B) + 1
;424		A.MINUS.1		=  16	; A - 1
;425	;				=  17
;426		A.PLUS.4		=  18	; A + 4
;427		A.MINUS.4		=  19	; A - 4
;428		NEG.B			=  1A	; -B
;429		NOT.B			=  1B	; ~B
;430		SMUL.STEP		=  1C	; signed multiply step
;431		UDIV.STEP		=  1D	; unsigned divide step
;432	;				=  1E
;433	;				=  1F
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   20
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;434
;435	;	Standard microinstruction format, continued.
;436
;437	;	This field defines the memory request function.  The address source is either the VA register, or if VA
;438	;	is updated from the ALU output, the ALU.  On reads, the DST field supplies the destination (must be
;439	;	a working register or a general register).  On writes, the shifter supplies the write data.
;440
;441	MRQ/=<54:50>,.DEFAULT=<MRQ/NOP>
;442
;443	;	       Command		 Val	Validity checks 	Description		Type	Check	Mode
;444	;	-----------------------  --- -------------------------- -----------------------+-------+-------+---------
;445		NOP			= 00				; no op 		none	none	none
;446		SYNC.BDISP		= 01				; no op to Mbox 	none	none	none
;447									; S4: stall if branch queue entry not valid
;448		SYNC.BDISP.RETIRE	= 02,.VALIDITY=<MUX.LAST>	; no op to Mbox 	none	none	none
;449									; S4: stall if branch queue entry not valid
;450									; S5: retire branch queue entry
;451		SYNC.BDISP.TEST.PRED	= 03,.VALIDITY=<MUX.LAST>	; no op to Mbox 	none	none	none
;452									; S4: stall if branch queue entry not valid
;453									; S5: retire branch queue entry, evaluate branch
;454									;     prediction, trap if incorrect
;455		TB.INVALIDATE.SINGLE	= 04				; TB invalidate single
;456		TB.INVALIDATE.PROCESS	= 05				; TB invalidate process
;457		TB.INVALIDATE.ALL	= 06				; TB invalidate all
;458	;				= 07
;459
;460		SYNC.MBOX		= 08				; synchronize with previous M-box command
;461		LOAD.PC 		= 09				; Send new PC to Ibox via Mbox
;462		TB.TAG.FILL		= 0A				; Send new TB tag to Mbox
;463		TB.PTE.FILL		= 0B				; Send new TB PTE to Mbox
;464
;465	;				= 0C
;466	;				= 0D
;467	;				= 0E
;468	;				= 0F
;469
;470		READ.V.RCHK		= 10,.VALIDITY=<DST.WN.OR.RN>	; read			virt	read	current
;471		READ.V.WCHK		= 11,.VALIDITY=<DST.WN.OR.RN>	; read with write check virt	write	current
;472		READ.V.NOCHK		= 12,.VALIDITY=<DST.WN.OR.RN>	; read with no check	virt	none	none
;473		READ.V.LOCK		= 13,.VALIDITY=<DST.WN> 	; read lock		virt	write	current
;474		READ.P			= 14,.VALIDITY=<DST.WN.OR.RN>	; read physical 	phys	none	none
;475		READ.PR 		= 15,.VALIDITY=<DST.WN> 	; read PR		phys	none	none
;476		PROBE.V.RCHK.NOFILL	= 16,.VALIDITY=<DST.WN> 	; read probe no fill	virt	read	mode
;477		PROBE.V.RCHK		= 17,.VALIDITY=<DST.WN> 	; read probe byte	virt	read	mode
;478
;479		WCHK			= 18				; write check		virt	write	current
;480		WRITE.V.WCHK		= 19				; write 		virt	write	current
;481		WRITE.V.NOCHK		= 1A				; write with no check	virt	none	none
;482		WRITE.V.UNLOCK		= 1B				; write unlock		virt	write	current
;483		WRITE.P 		= 1C				; write physical	phys	none	none
;484		WRITE.PR		= 1D				; write PR		phys	none	none
;485	;				= 1E
;486		PROBE.V.WCHK		= 1F,.VALIDITY=<DST.WN.OR.RN>	; write probe byte	virt	write	mode
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   21
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;487
;488	;	Standard microinstruction format, continued.
;489	;
;490	;	These field defines the shift operation.  Inputs to the shifter are selected by the A and B field
;491	;	decodes.  If the B port selects a literal, the shift count is supplied by SC;  otherwise, it can
;492	;	be supplied either by SC or the count field.  The output of the shifter can drive the Wbus (based
;493	;	on W control); based on Q control, it is conditionally latched in the Q (shift output) register.
;494	;	The shifter condition codes are always longword and can drive the PSL logic (based on W control).
;495
;496	Q/=<49>,.DEFAULT=<Q/HOLD.Q>
;497
;498		HOLD.Q			=  0	; maintain current value of Q
;499		UPDATE.Q		=  1	; update Q from shifter output
;500
;501	SHF/=<48:46>,.DEFAULT=<SHF/NOP>
;502
;503	;		Function	  Val		Operation			  Comments and restrictions
;504	;	-----------------------  ----	---------------------------	----------------------------------------------------
;505		NOP			=  0	; none				SHIFT.SIGN is preserved
;506		PASS.A			=  1	; output = A
;507		PASS.B			=  2	; output = B
;508		PASS.Z			=  3	; output = 0
;509		LEFT.DOUBLE		=  4	; output = A'B lsh count
;510		LEFT.SINGLE		=  5	; output = A'0 lsh count
;511		RIGHT.DOUBLE		=  6	; output = A'B rsh count
;512		RIGHT.SINGLE		=  7	; output = 0'B rsh count
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   22
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;513
;514	;	Standard microinstruction format, continued.
;515
;516	;	This field specifies the B port select.  The B port select can either be a literal constant
;517	;	(in which case the shift count is always supplied by SC), or a register select (in which
;518	;	case the shift count can be supplied either by SC or by the shift value field).
;519
;520	LIT/=<45>,.DEFAULT=<LIT/BREG>
;521
;522		BREG			=  0	; B port select is a B field register
;523		LIT			=  1	; B port select is a literal constant
;524
;525	;	When LIT specifies a literal constant, this field, along with the MISC/CONST.10.BIT decode
;526	;	selects the position of the constant.  If the MISC field does not contain the MISC/CONST.10.BIT
;527	;	decode, the POS field selects the byte position within the longword of the 8-bit constant
;528	;	specified by the CONST field.  If the MISC field contains the MISC/CONST.10.BIT decode,
;529	;	the POS and CONST fields are concatenated to supply a 10-bit constant which is placed in
;530	;	bits <9:0> of the B bus.  In either case, all remaining bits of the longword are forced to zero.
;531
;532	POS/=<44:43>,.DEFAULT=<POS/0>
;533
;534	;	Selection		  Val	    Resulting constant
;535	;	---------		 ----	-------------------------
;536		BYTE0			=  00	; 000000cc  (bits <7:0>)
;537		BYTE1			=  01	; 0000cc00  (bits <15:8>)
;538		BYTE2			=  02	; 00cc0000  (bits <23:16>)
;539		BYTE3			=  03	; cc000000  (bits <31:24>)
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   23
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;540
;541	;	Standard microinstruction format, continued.
;542
;543	;	When LIT specifies a literal constant and the MISC field does not contain the
;544	;	MISC/CONST.10.BIT decode, this field supplies the 8-bit constant value.
;545
;546	CONST/=<42:35>,.DEFAULT=<CONST/0>
;547
;548	;	    Constant		  Val		Interpretation or use
;549	;	-----------------------  ----	-----------------------------------------------
;550	;	System ID.
;551
;552		NVAX.SID		= 19.	; system ID (byte 3)
;553
;554	;	Revision constants (here so that they appear in the .ULD/.ULA symbol table)
;555
;556		UCODE.REVISION		= <MICROCODE.REVISION> ; Microcode revision number
;557		UCODE.PATCH		= <MICROCODE.PATCH> ; Microcode patch number
;558		UCODE.NONSTANDARD	= <MICROCODE.NONSTANDARD> ; Microcode non-standard patch
;559
;560	;	SCB offsets.
;561
;562		SCB.MACHCHK		= 004	; SCB vector, machine check
;563		SCB.KSNV		= 008	; SCB vector, kernel stack not valid
;564		SCB.PWRFL		= 00C	; SCB vector, power fail
;565		SCB.RESPRIV		= 010	; SCB vector, reserved/priv instruction
;566		SCB.XFC 		= 014	; SCB vector, XFC instruction
;567		SCB.RESOP		= 018	; SCB vector, reserved operand
;568		SCB.RESADD		= 01C	; SCB vector, reserved addressing mode
;569		SCB.ACV 		= 020	; SCB vector, access control violation
;570		SCB.TNV 		= 024	; SCB vector, translation not valid
;571		SCB.TP			= 028	; SCB vector, trace pending
;572		SCB.BPT 		= 02C	; SCB vector, breakpoint trace
;573		SCB.ARITH		= 034	; SCB vector, arithmetic fault
;574		SCB.VM			= 038	; SCB vector, VM trap
;575		SCB.MODIFY		= 03C	; SCB vector, modify fault
;576		SCB.CHMK		= 040	; SCB vector, change mode to kernel
;577		SCB.CHME		= 044	; SCB vector, change mode to executive
;578		SCB.CHMS		= 048	; SCB vector, change mode to supervisor
;579		SCB.CHMU		= 04C	; SCB vector, change mode to user
;580		SCB.SERR		= 054	; SCB vector, soft error interrupt
;581		SCB.PMF.BASE		= 058	; SCB vector, physical address of performance monitoring facility block
;582		SCB.HERR		= 060	; SCB vector, hard error interrupt
;583		SCB.VECT.DISABLED	= 068	; SCB vector, vector unit disabled exception
;584		SCB.IPLSOFT		= 080	; SCB vector, software interrupts
;585		SCB.INTTIM		= 0C0	; SCB vector, interval timer interrupt
;586		SCB.EMULATE		= 0C8	; SCB vector, emulation
;587		SCB.EMULFPD		= 0CC	; SCB vector, emulation with FPD set
;588
;589	;	Arithmetic trap and fault codes.
;590
;591		ARITH.TRAP.INTOVF	=  01	; integer overflow
;592		ARITH.TRAP.INTDIV	=  02	; integer divide-by-zero
;593		ARITH.TRAP.SUBRNG	=  07	; subscript range
;594		ARITH.FAULT.FLTOVF	=  08	; floating overflow
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   24
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;595		ARITH.FAULT.FLTDIV	=  09	; floating divide-by-zero
;596		ARITH.FAULT.FLTUND	=  0A	; floating underflow
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   25
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;597
;598	;	Standard microinstruction format, continued.
;599	;	CONST field, continued.
;600
;601	;	    Constant		  Val		Interpretation or use
;602	;	-----------------------  ----	-----------------------------------------------
;603	;	Console halt codes.
;604
;605		ERR.HLTPIN		=  02	; HALT_L pin asserted
;606		ERR.PWRUP		=  03	; initial power up
;607		ERR.INTSTK		=  04	; interrupt stack not valid
;608		ERR.DOUBLE		=  05	; machine check during exception processing
;609		ERR.HLTINS		=  06	; HALT instruction in kernel mode
;610		ERR.ILLVEC		=  07	; illegal SCB vector (bits <1:0> = 11)
;611		ERR.WCSVEC		=  08	; WCS SCB vector (bits <1:0> = 10)
;612		ERR.CHMFI		=  0A	; CHMx on interrupt stack
;613		ERR.IE0 		=  10	; ACV/TNV during machine check processing
;614		ERR.IE1 		=  11	; ACV/TNV during kernel-stack-not-valid processing
;615		ERR.IE2 		=  12	; machine check during machine check processing
;616		ERR.IE3 		=  13	; machine check during kernel-stack-not-valid processing
;617		ERR.IE.PSL.26-24.101	=  19	; PSL<26:24> = 101 during interrupt or exception
;618		ERR.IE.PSL.26-24.110	=  1A	; PSL<26:24> = 110 during interrupt or exception
;619		ERR.IE.PSL.26-24.111	=  1B	; PSL<26:24> = 111 during interrupt or exception
;620		ERR.REI.PSL.26-24.101	=  1D	; PSL<26:24> = 101 during REI
;621		ERR.REI.PSL.26-24.110	=  1E	; PSL<26:24> = 110 during REI
;622		ERR.REI.PSL.26-24.111	=  1F	; PSL<26:24> = 111 during REI
;623
;624	;	Machine check codes.
;625
;626		MCHK.UNKNOWN.MSTATUS	=  01	; unknown memory management status
;627		MCHK.INT.ID.VALUE	=  02	; unknown interrupt id
;628		MCHK.CANT.GET.HERE	=  03	; unknown microcode dispatch
;629		MCHK.MOVC.STATUS	=  04	; unknown MOVCx status
;630		MCHK.ASYNC.ERROR	=  05	; async HW error microtrap
;631		MCHK.SYNC.ERROR 	=  06	; sync HW error microtrap
;632		MCHK.PMF.CONFIG 	=  07	; performance monitoring facility incorrectly configured
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   26
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;633
;634	;	Standard microinstruction format, continued.
;635	;	CONST field, continued.
;636
;637	;	    Constant		  Val		Interpretation or use
;638	;	-----------------------  ----	-----------------------------------------------
;639	;	PTE bits
;640
;641		PTE.M			=  04	; PTE<M> (byte 3)
;642
;643	;	PSL bits
;644
;645		PSL.TP			=  40	; PSL<TP> (byte 3)
;646
;647	;	ISR bit definitions
;648
;649		ISR.HALT		=  80	; ISR bit to clear HALT_L flop (byte 3)
;650		ISR.SERR		=  08	; ISR bit to clear SERR_L flop (byte 3)
;651		ISR.PMF 		=  10	; ISR bit to clear PMF flop (byte 3)
;652		ISR.INT_TIM		=  01	; ISR bit to clear INT_TIM_L flop (byte 3)
;653		ISR.CLEAR.ALL		=  0F9	; ISR mask to clear all interrupt requests and ICCS<6> (byte 3)
;654
;655	;	ECR bit definitions
;656
;657		ECR.ICCS.EXT		=  80	; ECR bit that indicates external ICCS (byte 0)
;658		ECR.PMF.ENABLE		=  01	; ECR bit that enables the PMF (byte 2)
;659		ECR.PMF.CLEAR		=  80	; virtual ECR bit that clears the PMF counters (byte 3)
;660
;661	;	PCSCR bit definitions
;662
;663		PCSCR.PCS.ENB		= 02	; PCSCR bit that indicates that PCS is enabled (byte 1)
;664
;665	;	CEFSTS bit definitions
;666
;667		CEFSTS.RDLK		=  01	; CEFSTS bit to clear RDLK error (byte 0)
;668
;669	;	PCCTL bit definitions
;670
;671		PCCTL.FORCE.HIT 	=  07	; Force hit+I enable+D enable (byte 0)
;672
;673	;	IPR mask bits and right-justified encodings
;674
;675		IPR.CACHE		=  01	; Bit in byte 3 which differentiates cache IPRs from normal IPRs.
;676		IPR.EBOX.BLOCK		=  78	; First of 8 special-cased Ebox IPRs
;677		IPR.VECTOR.BLOCK	=  90	; First of 8 special-cased vector IPRs
;678
;679	;	P1BR bias constant
;680
;681		P1BR.BIAS		=  80	; P1BR bias constant (byte 2)
;682		P1LR.BIAS.SHIFTED	=  40	; P1LR bias constant (byte 3 of shifted value)
;683		P1LR.BIAS.UNSHIFTED	=  20	; P1LR bias constant (byte 2 of unshifted value)
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   27
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;684
;685	;	Standard microinstruction format, continued.
;686	;	CONST.10 field
;687
;688	;	When LIT specifies a literal constant and the MISC field contains the
;689	;	MISC/CONST.10.BIT decode, this field supplies the 10-bit constant value.
;690	;	Note that this field overlaps the POS and CONST fields, and is only
;691	;	used when the MISC field contains the MISC/CONST.10.BIT decode.
;692
;693	CONST.10/=<44:35>
;694
;695	;	    Constant		  Val		Interpretation or use
;696	;	-----------------------  ----	-----------------------------------------------
;697	;	Internal processor registers.  These values are pre-shifted by 2 bits to
;698	;	position then into bits <9:2> rather than <7:0>.
;699
;700		IPR.ICCS		= <.SHIFT[<018>,2]> ; External ICCS register
;701
;702		IPR.IAK.BASE		= <.SHIFT[<.DIFF[<040>,<014>]>,2]>
;703							    ; interrupt IAK base (IPR.IAK.BASE+[IPL*4] = IPR.IAK1x)
;704		IPR.CWB 		= <.SHIFT[<044>,2]> ; Clear write buffers
;705
;706		IPR.CEFSTS		= <.SHIFT[<0AC>,2]> ; Cbox CEFSTS register address
;707
;708
;709		IPR.BPCR		= <.SHIFT[<0D4>,2]> ; Ibox branch prediction control register
;710		IPR.BPC 		= <.SHIFT[<0D6>,2]> ; Ibox backup PC
;711		IPR.BPC.UNWIND		= <.SHIFT[<0D7>,2]> ; Ibox backup PC with RLOG unwind
;712
;713		IPR.MP0BR		= <.SHIFT[<0E0>,2]> ; Mbox P0 base register
;714		IPR.MP0LR		= <.SHIFT[<0E1>,2]> ; Mbox P0 length register
;715		IPR.MP1BR		= <.SHIFT[<0E2>,2]> ; Mbox P1 base register
;716		IPR.MP1LR		= <.SHIFT[<0E3>,2]> ; Mbox P1 length register
;717		IPR.MSBR		= <.SHIFT[<0E4>,2]> ; Mbox system base register
;718		IPR.MSLR		= <.SHIFT[<0E5>,2]> ; Mbox system length register
;719		IPR.MMAPEN		= <.SHIFT[<0E6>,2]> ; Mbox memory management enable
;720		IPR.PAMODE		= <.SHIFT[<0E7>,2]> ; Mbox physical address mode
;721		IPR.MMEADR		= <.SHIFT[<0E8>,2]> ; Mbox MME address
;722		IPR.MMEPTE		= <.SHIFT[<0E9>,2]> ; Mbox MME PTE address
;723		IPR.MMESTS		= <.SHIFT[<0EA>,2]> ; Mbox MME status
;724		IPR.PCSTS		= <.SHIFT[<0F4>,2]> ; Mbox Pcache status
;725		IPR.PCCTL		= <.SHIFT[<0F8>,2]> ; Mbox Pcache control
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   28
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;726
;727	;	Standard microinstruction format, continued.
;728
;729	;	When the LIT field specifies a B register and shift value, the shift count is
;730	;	taken from this field.	A zero value specifies a shift by SC.
;731
;732	VAL/=<44:40>,.DEFAULT=<VAL/0>
;733
;734	;	When the LIT field specifies a B register and shift value, this field supplies the
;735	;	B port decode.
;736
;737	B/=<39:35>,.DEFAULT=<B/NONE>
;738
;739	;		Function	  Val		     Operation				    Comments
;740	;	-----------------------  ----	--------------------------------------- --------------------------------------------
;741		NONE			=  00	; No source
;742		W0			=  01	; working register 0
;743		W1			=  02	; working register 1
;744		W2			=  03	; working register 2
;745		W3			=  04	; working register 3
;746		W4			=  05	; working register 4
;747		W5			=  06	; working register 5
;748	;				=  07
;749
;750		S1			=  08	; top of specifier queue		advance specifier queue by 1 entry
;751		S2			=  09,.VALIDITY=<A.S1>
;752						; second entry in specifier queue	advance specifier queue by 2 entries
;753		Q			=  0A	; shifter output latch
;754	;				=  0B	;					VA in A field
;755	;				=  0C	;					PSL in A, DST fields
;756	;				=  0D	;
;757		K.FFFF			=  0E	; Constant 0000FFFF (hex)
;758		RN.MODE.OPCODE		=  0F	; Rn (bits <31:28>)'CUR_MOD (bits <25:24>)'opcode (bits <23:16>)'
;759						; VAX Restart bit (bit<7>), 0 (bits <27:26,15:8,6:0>)
;760
;761		R0			=  10	; R0
;762		R1			=  11	; R1
;763		R2			=  12	; R2
;764		R3			=  13	; R3
;765		R4			=  14	; R4
;766		R5			=  15	; R5
;767		R6			=  16	; R6
;768		R7			=  17	; R7
;769		R8			=  18	; R8
;770		R9			=  19	; R9
;771		R10			=  1A	; R10
;772		R11			=  1B	; R11
;773		R12			=  1C	; R12
;774			AP		=  1C	;  argument pointer
;775		R13			=  1D	; R13
;776			FP		=  1D	;  frame pointer
;777		SP			=  1E	; R14 = stack pointer
;778	;				=  1F
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   29
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;779
;780	;	Standard microinstruction format, continued.
;781
;782	;	This field controls whether the following are done as longwords or according to the
;783	;	prevailing data length:
;784	;		1. calculation of alu cc's
;785	;		2. zero extending of Wbus result
;786	;		3. size of memory operation
;787
;788	L/=<34>,.DEFAULT=<L/LONG>
;789
;790		LONG			=   0	; alu cc's, Wbus, memory operation are longword
;791		LEN(DL) 		=   1	; alu cc's, Wbus, memory operation are specified by DL
;792
;793	;	This field determines whether the ALU or the shifter drives the Wbus, and
;794	;	whether the ALU or shifter cc's are the input to the PSL condition code logic.
;795
;796	W/=<33>,.DEFAULT=<W/ALU>
;797
;798		ALU			=   0	; alu drives Wbus, alu cc's drive psl cc's
;799		SHF			=   1	; shifter drives Wbus, shifter cc's drive psl cc's
;800
;801	;	This field determines whether the VA register is updated from the ALU output.
;802
;803	V/=<32>,.DEFAULT=<V/HOLD.VA>
;804
;805		HOLD.VA 		=   0	; maintain current value of VA
;806		UPDATE.VA		=   1	; update VA from ALU output
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   30
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;807
;808	;	Standard microinstruction format, continued.
;809
;810	;	This field defines the destination control.
;811
;812	;	The order and numbering of the values in the DST and A fields are identical.  If you change these values check
;813	;	the other field for a corresponding change.
;814
;815	DST/=<31:26>,.DEFAULT=<DST/WBUS>
;816
;817	;		Function	  Val		     Operation				    Comments
;818	;	-----------------------  ----	--------------------------------------- --------------------------------------------
;819		NONE			=  00	; No destination			No W-bus request is made
;820		W0			=  01	; working register 0
;821		W1			=  02	; working register 1
;822		W2			=  03	; working register 2
;823		W3			=  04	; working register 3
;824		W4			=  05	; working register 4
;825		W5			=  06	; working register 5
;826	;				=  07
;827
;828		WBUS			=  08	; W-bus 				Drive W-bus, S1 in A, B fields
;829		DST			=  09,.VALIDITY=<MRQ.NOP>
;830						; top of destination specifier queue	S2 in A, B field
;831	;				=  0A	;					Q in A, B fields
;832	;				=  0B	;					VA in A field
;833		PSL			=  0C	; PSL					writable as long only
;834		PSL.B0			=  0D	; PSL<7:0>				FBOX.FAULT.CODE in B field
;835	;				=  0E
;836	;				=  0F	;					RN.MODE.OPCODE in B field
;837
;838		R0			=  10	; R0
;839		R1			=  11	; R1
;840		R2			=  12	; R2
;841		R3			=  13	; R3
;842		R4			=  14	; R4
;843		R5			=  15	; R5
;844		R6			=  16	; R6
;845		R7			=  17	; R7
;846		R8			=  18	; R8
;847		R9			=  19	; R9
;848		R10			=  1A	; R10
;849		R11			=  1B	; R11
;850		R12			=  1C	; R12
;851			AP		=  1C	;  argument pointer
;852		R13			=  1D	; R13
;853			FP		=  1D	;  frame pointer
;854		SP			=  1E	; R14 = stack pointer
;855	;				=  1F	;
;856
;857		KSP			=  20	; kernel stack pointer
;858		ESP			=  21	; executive stack pointer
;859		SSP			=  22	; supervisor stack pointer
;860		USP			=  23	; user stack pointer
;861		ISP			=  24	; interrupt stack pointer
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   31
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;862		ASTLVL			=  25	; ASTLVL value in bits <31:29>, machine check code in bits <23:16>,
;863						; CPUID in bits <7:0>
;864		SCBB			=  26	; system control block base register
;865		PCBB			=  27	; process control block base register
;866		SAVEPC			=  28	; console saved PC (also BPC after call to IE.CLEANUP.CPU)
;867		SAVEPSL 		=  29	; console saved PSL
;868	;				=  2A
;869	;				=  2B
;870	;				=  2C
;871	;				=  2D
;872	;				=  2E
;873	;				=  2F
;874
;875		INT.SYS 		=  30	; hw flops (bits <31:29,27,24>)'sisr<15:1> (bits<15:1>'iccs<6> (bit<0>)
;876	;				=  31	;					K0 in A field
;877	;				=  32	;					K1 in A field
;878	;				=  33	;
;879	;				=  34	;
;880		SC			=  35	; shift count
;881		MMGT.MODE		=  36	; mode for probing from <3:2>
;882	;				=  37	;					S+PSW_EX in A field
;883	;				=  38	;					POP.COUNT in A field
;884	;				=  39	;					SHIFT.SIGN in A field
;885		ECR			=  3A	; Ebox control register
;886	;				=  3B	;					PERF.COUNT in A field
;887		PCSCR			=  3C	; Patchable control store control register
;888	;				=  3D
;889	;				=  3E
;890	;				=  3F
;891	;				=  3F
;892	;				=  3F
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   32
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;893
;894	;	Standard microinstruction format, continued.
;895
;896	;	This field defines the A port select.
;897
;898	;	The order and numbering of the values in the DST and A fields are identical.  If you change these values check
;899	;	the other field for a corresponding change.
;900
;901	A/=<25:20>,.DEFAULT=<A/NONE>
;902
;903	;		Function	  Val		     Operation				    Comments
;904	;	-----------------------  ----	--------------------------------------- --------------------------------------------
;905		NONE			=  00
;906		W0			=  01	; working register 0
;907		W1			=  02	; working register 1
;908		W2			=  03	; working register 2
;909		W3			=  04	; working register 3
;910		W4			=  05	; working register 4
;911		W5			=  06	; working register 5
;912	;				=  07
;913
;914		S1			=  08	; top of source specifier queue 	advance specifier queue by 1 entry
;915		S2			=  09,.VALIDITY=<B.S1>
;916						; top of destination specifier queue	advance specifier queue by 2 entries
;917		Q			=  0A	; shift result latch
;918		VA			=  0B	; virtual address register
;919		PSL			=  0C	; PSL register
;920	;				=  0D	;					FBOX.FAULT.CODE in B field
;921	;				=  0E
;922	;				=  0F
;923
;924		R0			=  10	; R0
;925		R1			=  11	; R1
;926		R2			=  12	; R2
;927		R3			=  13	; R3
;928		R4			=  14	; R4
;929		R5			=  15	; R5
;930		R6			=  16	; R6
;931		R7			=  17	; R7
;932		R8			=  18	; R8
;933		R9			=  19	; R9
;934		R10			=  1A	; R10
;935		R11			=  1B	; R11
;936		R12			=  1C	; R12
;937			AP		=  1C	;  argument pointer
;938		R13			=  1D	; R13
;939			FP		=  1D	;  frame pointer
;940		SP			=  1E	; R14 = stack pointer
;941	;				=  1F	;
;942
;943		KSP			=  20	; kernel stack pointer
;944		ESP			=  21	; executive stack pointer
;945		SSP			=  22	; supervisor stack pointer
;946		USP			=  23	; user stack pointer
;947		ISP			=  24	; interrupt stack pointer
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   33
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;948		ASTLVL			=  25	; ASTLVL value in bits <31:29>, machine check code in bits <23:16>,
;949						; CPUID in bits <7:0>
;950		SCBB			=  26	; system control block base register
;951		PCBB			=  27	; process control block base register
;952		SAVEPC			=  28	; console saved PC
;953		SAVEPSL 		=  29	; console saved PSL
;954	;				=  2A
;955	;				=  2B
;956	;				=  2C
;957	;				=  2D
;958	;				=  2E
;959	;				=  2F
;960
;961		INT.SYS 		=  30	; 0 (bits<31:21>)'int.id (bits<20:16>)'sisr<15:1> (bits<15:1>'iccs<6> (bit<0>)
;962		K0			=  31	; constant 0
;963		K1			=  32	; constant 1
;964	;				=  33
;965	;				=  34
;966	;				=  35
;967	;				=  36
;968		S+PSW_EX		=  37	; opcode<0> in <29>'PSW<7:5> in <7:5>, else 0
;969		POP.COUNT		=  38	; mask bits set in mask processing unit
;970		SHIFT.SIGN		=  39	; shifter sign
;971		ECR			=  3A	; Ebox control register
;972		PERF.COUNT		=  3B	; Performance monitoring facility counters.  PMCTR0 in <31:16>,
;973						; PMCTR1 in <15:0>
;974		PCSCR			=  3C	; Patchable control store control register
;975	;				=  3D
;976	;				=  3E
;977	;				=  3F
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   34
;    DEFINE.MIC 	     Standard Microinstruction Format							      /REV=
;
;978
;979	;	Standard microinstruction format, continued.
;980
;981	;	This field is decoded to provide miscellaneous function control.
;982
;983	MISC/=<19:15>,.DEFAULT=<MISC/NOP>
;984
;985	;		Function	  Val		     Operation				    Comments
;986	;	-----------------------  ----	--------------------------------------- --------------------------------------------
;987		NOP			=  00	; no operation
;988		MULL			=  01	; Identifies an Fbox instruction as MULL
;989		CONST.10.BIT		=  02,.VALIDITY=<LIT.LIT>
;990						; Selects 10-bit B-bus constant from CONST.10 field
;991	;				=  03
;992		DL.BYTE 		=  04	; DL <-- byte				S3: change effects next microword
;993		DL.WORD 		=  05	; DL <-- word				S3: change effects next microword
;994		DL.LONG 		=  06	; DL <-- long				S3: change effects next microword
;995	;				=  07
;996		RESTART.IBOX		=  08	; restart I-box 			S5: prefetch and specifier processing
;997		RESTART.MBOX		=  09	; restart M-box 			S5: operand processing
;998	;				=  0A
;999	;				=  0B
;1000		RESET.CPU		=  0C	; reset I-box, M-box, F-box		S5: reset I-box and stop prefetch
;1001						;					S6: reset M-box and F-box,
;1002						;					    init register file valid bits
;1003	;				=  0D
;1004		CLR.PERF.COUNT		=  0E	; clear perf monitoring counters	S5: clear counters
;1005		INCR.PERF.COUNT 	=  0F	; increment perf monitoring counters	S5: increment counters
;1006
;1007		CLR.STATE.3-0		=  10	; clear flags<3:0>			S3: change effects next microword
;1008		SET.STATE.0		=  11	; set flag<0>				S3: change effects next microword
;1009		SET.STATE.1		=  12	; set flag<1>				S3: change effects next microword
;1010		SET.STATE.2		=  13	; set flag<2>				S3: change effects next microword
;1011		LOAD.SC.FROM.A		=  14	; SC <-- Abus
;1012		LOAD.MPU.FROM.B 	=  15	; MPU <-- Bbus<29:16>			S4: change effects microword+2
;1013	;				=  16
;1014	;				=  17
;1015		LOAD.PSL.CC.IIIP	=  18	; load PSL CCs with map IIIP		PSL.NZV  <--  WBUS.NZV
;1016						;					PSL.C	 <--  PSL.C (Unchanged)
;1017		LOAD.PSL.CC.JIZJ	=  19	; load PSL CCs with map JIZJ		PSL.N	 <--  WBUS.N XOR WBUS.V
;1018						;					PSL.Z	 <--  WBUS.Z
;1019						;					PSL.V	 <--  0
;1020						;					PSL.C	 <-- ~WBUS.C
;1021		LOAD.PSL.CC.IIII	=  1A	; load PSL CCs with map IIII		PSL.NZVC <--  WBUS.NZVC
;1022		LOAD.PSL.CC.IIIJ	=  1B	; load PSL CCs with map IIIJ		PSL.NZV  <--  WBUS.NZV
;1023						;					PSL.C	 <-- ~WBUS.C
;1024		LOAD.PSL.CC.IIIP.QUAD	= 1C	; load PSL CCs with map IIIP.quad	PSL.NV	 <--  WBUS.NV
;1025						;					PSL.Z	 <--  PSL.Z AND WBUS.Z
;1026						;					PSL.C	 <--  PSL.C (Unchanged)
;1027		LOAD.PSL.CC.PPJP	=  1D	; load PSL CCs with map PPJP		PSL.NZC  <--  PSL.NZC (unchanged)
;1028						;					PSL.V	 <--  not WBUS.Z
;1029			SIM.IE.INTEXC	=  1E	; IE.INTERRUPT/IE.EXCEPTION called	Simulator only; not in real hardware
;1030			SIM.HALT	=  1F	; stop simulator			Simulator only; not in real hardware
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   35
;    DEFINE.MIC 	     Special Microinstruction Format							      /REV=
;
;1031	.TOC	"	Special Microinstruction Format"
;1032
;1033	;	The fields for the special microinstruction are:
;1034	;
;1035	;	FORMAT/ 	SPECIAL
;1036	;	ALU/		ALU operation
;1037	;	MRQ/		Mbox request
;1038	;	MISC1/		Special miscellaneous 1
;1039	;	LIT/		B operand control, as follows:
;1040	;	    LIT/0:
;1041	;		MISC2/	Special miscellaneous 2
;1042	;		DISABLE.RETIRE/ Disable retire of instruction on LAST CYCLE
;1043	;		B/	B port select
;1044	;	    LIT/1:
;1045	;		POS/	Constant position	\ If MISC field does not
;1046	;		CONST/	8-bit constant value	/ contain CONST.10.BIT
;1047	;		CONST.10/ 10-bit constant value   If MISC field contains CONST.10.BIT
;1048	;	L/		Length control
;1049	;	W/		Wbus driver control
;1050	;	V/		VA latch update control
;1051	;	DST/		Wbus destination
;1052	;	A/		ALU A port select
;1053	;	MISC/		Miscellaneous
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   36
;    DEFINE.MIC 	     Special Microinstruction Format							      /REV=
;
;1054
;1055	;	Special microinstruction format, continued.
;1056
;1057	;	This field is the first miscellaneous function field.
;1058
;1059	MISC1/=<49:46>,.DEFAULT=<MISC1/NOP>
;1060
;1061	;		Function	  Val		     Operation				    Comments
;1062	;	-----------------------  ----	--------------------------------------- --------------------------------------------
;1063		NOP			=  00	; no operation
;1064		RETIRE.INSTRUCTION	=  01	; retire current instruction
;1065	;				=  02
;1066		FLUSH.VIC		=  03	; flush virtual instruction cache	S5: flush VIC.	REQUIRES A LOAD PC
;1067						;					BEFORE RESTARTING THE IBOX
;1068		FLUSH.BPC		=  04	; flush branch prediction table 	S5: flush branch prediction table
;1069		CLR.STATE.5-4		=  05	; state<5:4> <-- 0
;1070		SET.STATE.3		=  06	; state<3> <-- 1
;1071		SET.STATE.4		=  07	; state<4> <-- 1
;1072		SET.STATE.5		=  08	; state<5> <-- 1
;1073		FOP.VALID		=  09,.VALIDITY=<B.NOT.S1>
;1074						; F-box operand valid on FA/FB bus
;1075	;				=  09
;1076	;				=  0A
;1077	;				=  0B
;1078		FLUSH.PCQ		=  0C	; Flush Ibox PC queue
;1079	;				=  0D
;1080	;				=  0E
;1081	;				=  0F
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   37
;    DEFINE.MIC 	     Special Microinstruction Format							      /REV=
;
;1082
;1083	;	Special microinstruction format, continued.
;1084
;1085	;	This field is the second miscellaneous function field.
;1086
;1087	MISC2/=<44:41>,.DEFAULT=<MISC2/NOP>
;1088
;1089	;		Function	  Val		     Operation				    Comments
;1090	;	-----------------------  ----	--------------------------------------- --------------------------------------------
;1091		NOP			=  00	; no operation
;1092		F.DEST.CHECK		=  01	; Udate the Fbox scoreboard from the Dest list
;1093		FLUSH.PAQ		=  02,.VALIDITY=<MRQ.REQ>
;1094						; Flush Mbox PA queue			Must be done with MRQ field request
;1095	;				=  03
;1096	;				=  04
;1097	;				=  05
;1098	;				=  06
;1099	;				=  07
;1100	;				=  08
;1101	;				=  09
;1102	;				=  0A
;1103	;				=  0B
;1104	;				=  0C
;1105	;				=  0D
;1106	;				=  0E
;1107	;				=  0F
;1108
;1109
;1110	;	This bit disables the retire of an instruction when LAST.CYCLE
;1111	;	is decoded from the SEQ.MUX field.
;1112
;1113	DISABLE.RETIRE/=<40>,.DEFAULT=<DISABLE.RETIRE/NO>
;1114
;1115	;		Function	  Val		     Operation				    Comments
;1116	;	-----------------------  ----	--------------------------------------- --------------------------------------------
;1117		NO			=  0	; Do not diable retire of instruction (the normal thing)
;1118		YES			=  1	; Disable retire of instruction
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   38
;    DEFINE.MIC 	     Microsequencer Control Fields							      /REV=
;
;1119	.TOC	"	Microsequencer Control Fields"
;1120
;1121	;	The microsequencer control fields supply the information necessary for the microsequencer
;1122	;	to calculate the address of the next microinstruction.	The basic computation done by
;1123	;	the microsequencer involves selecting a base address from one of several sources, and then
;1124	;	optionally modifying 3 bits of the base address to get the final next address.
;1125
;1126	;	This field defines the format of the microsequencer control fields.  The microsequencer uses
;1127	;	this bit to block the latch which contains bits <10:8> of the next address.  This means that
;1128	;	the destination of a BRANCH format microinstruction must be in the same 256-location page
;1129	;	as the branch itself.
;1130
;1131	SEQ.FMT/=<14>,.DEFAULT=<SEQ.FMT/JUMP>
;1132
;1133		JUMP			=   0	; format is JUMP
;1134		BRANCH			=   1	; format is BRANCH
;1135
;1136	;	This field controls whether the current micro-PC is pushed on the microsubroutine stack.
;1137
;1138	SEQ.CALL/=<13>,.DEFAULT=<SEQ.CALL/NOP>
;1139
;1140		NOP			=   0	; don't call subroutine
;1141		CALL			=   1	; call subroutine
;1142
;1143	;	For the jump format, this field controls the next-address selection via the NA mux.
;1144
;1145	SEQ.MUX/=<12:11>,.DEFAULT=<SEQ.MUX/J>
;1146
;1147	;		Select		  Val		  Address Source				    Comments
;1148	;	-----------------------  ----	--------------------------------------- --------------------------------------------
;1149		J			=   0	; current microword			uword<10:0>
;1150		STACK			=   1	; microstack				pops top entry from microstack
;1151		LAST.CYCLE		=   2	; I-box 				new microflow
;1152		LAST.CYCLE.OVERFLOW	=   3	; I-box 				new microflow, enable int overflow trap
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   39
;    DEFINE.MIC 	     Microsequencer Control Fields							      /REV=
;
;1153
;1154	;	Microsequencer control fields, continued.
;1155
;1156	;	This field defines the microbranch condition used to modify base address bits <3:1> in a BRANCH format
;1157	;	microinstruction.  In the real microword format, this field occupies the bits specified by the SEQ.COND field.
;1158	;	In the fake microword format, this field is placed in the SEQ.COND.1 field so that a full 11-bit next-address
;1159	;	can be specified in all microwords, including BRANCH format microinstructions.	The SEQ.COND.1 field is moved
;1160	;	to the SEQ.COND field by the allocator to construct the final microword format.
;1161
;1162	SEQ.COND.1/=<65:61>,.DEFAULT=<SEQ.COND.1/0> ; 'Fake' microbranch condition
;1163
;1164	SEQ.COND/=<12:8>			; 'Real' microbranch condition
;1165
;1166	;	Note: AMUX tests on sign values (bits<31>, <15>, <7>) should affect the same NA bit.
;1167
;1168	;	       Select		  Val	Modifier bits for NA<3:1>			Comments
;1169	;	-----------------------  ----	--------------------------------------- --------------------------------------------
;1170		NOP			=  00	; No microbranch condition
;1171		ALU.NZV 		=  01	; alu<n>'alu<z>'alu<v>			set by microinstruction .-2
;1172		ALU.NZC 		=  02	; alu<n>'alu<z>'alu<c>			set by microinstruction .-2
;1173		B.2-0			=  03	; Bbus<2:0>				set by microinstruction .-1
;1174		B.5-3			=  04	; Bbus<5:3>				set by microinstruction .-1
;1175		A.7-5			=  05	; Abus<7:5>				set by microinstruction .-1
;1176		A.15-12 		=  06	; Abus<15>'Abus<14>'(Abus<13> OR Abus<12>) set by microinstruction .-1
;1177		A31.BQA.BNZ1		=  07	; Abus<31>'Bbus<2:0> = 0'(Bbus<15:8> NE 0) set by microinstruction .-1
;1178		MPU.0-6 		=  08	; mask proc unit output 		loaded by microinstruction .-2
;1179		MPU.7-13		=  09	; mask proc unit output 		loaded by microinstruction .-2
;1180		STATE.2-0		=  0A	; state<2:0>				set by microinstruction .-1
;1181		STATE.5-3		=  0B	; state<5:3>				set by microinstruction .-1
;1182		OPCODE.2-0		=  0C	; opcode<2:0>
;1183		PSL.26-24		=  0D	; PSL<26:24>
;1184		PSL.29.23-22		=  0E	; PSL<29,23:22>
;1185		SHF.NZ.INT		=  0F	; shf<n>'shf<z>'interrupt		set by microinstruction .-2
;1186
;1187		TEST.PINS		=  10	; vector present'test data'test strobe
;1188			VECTOR		=  10	; vector present'test data'test strobe
;1189		FBOX.CONDITION		=  11	; Priority encoded Fbox fault code<1:0>'Fbox disabled
;1190		FQ.VR			=  12	; 0'field queue not valid'field queue rmode
;1191						; 000 = valid,memory / 001 = valid,register
;1192						; 010 (not used)     / 011 = queue not valid
;1193	;				13..1F
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   40
;    DEFINE.MIC 	     Microsequencer Control Fields							      /REV=
;
;1194
;1195	;	Microsequencer control fields, continued.
;1196
;1197	;	This field gives the address of the next microinstruction if the current microinstruction is JUMP format.
;1198
;1199	J/=<10:0>,.NEXTADDRESS
;1200
;1201	;	This field gives the 8-bit page offset of the next microinstruction if the current microinstruction is BRANCH
;1202	;	format.  The remaining 3 bits of the 11-bit address are taken from the corresponding bits of the current microPC.
;1203	;	This field is never used by MICRO2.  The allocator selectively fills it in based on the format of the
;1204	;	microinstruction.
;1205
;1206	BR.OFF/=<7:0>
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   41
;    DEFINE.MIC 	     Simulation and Assembly Control Fields						      /REV=
;
;1207	.TOC	"	Simulation and Assembly Control Fields"
;1208
;1209	;	The following field definitions are used to provide necessary information to the performance model.
;1210	;	They are removed from the microword by the allocator when the microcode is built for the behavioral
;1211	;	model or the actual chip.  They are retained by the allocator when the microcode is built for the
;1212	;	performance model.
;1213
;1214	;	This field selects which field contains performance model commands.
;1215	;
;1216	;	NOTE: PEBOX.PAS HAS INTIMATE KNOWLEDGE OF THESE DEFINITIONS.
;1217
;1218	SIM.CTRL/=<78>,.DEFAULT=<SIM.CTRL/NONE>
;1219
;1220		CMD			=  0	; Command in the SIM.ADDR field (CMD.xxx)
;1221		NONE			=  1	; No performance model command
;1222	;
;1223	;	When the SIM.CTRL field contains CMD, the following overlapping field contains the command.
;1224	;	This field overlaps with the SIM.COND field.  Therefore if the SIM.CTRL field selects CMD then
;1225	;	the SIM.COND and SIM.COND.SEL fields do not contain valid values.
;1226	;
;1227	SIM.CMD/=<68:66>
;1228	;
;1229	;	      Command		 Val			   Interpretation
;1230	;	----------------------	 ---	---------------------------------------------------
;1231		SIM.ERROR		= 00	; Illegal microword
;1232		EXCEPTION		= 01	; Microcode exception handler reached
;1233		RSVD.OPCODE		= 02	; Reserved opcode handler reached
;1234		EMULATE 		= 03	; Emulated instruction handler reached
;1235		VECTOR.FAULT		= 04	; Vector fault handler reached
;1236	;				= 05	;
;1237	;				= 06	;
;1238	;				= 07	;
;1239	;				= 08	;
;1240	;				= 09	;
;1241	;				= 0A	;
;1242	;				= 0B	;
;1243	;				= 0C	;
;1244	;				= 0D	;
;1245	;				= 0E	;
;1246	;				= 0F	;
;1247
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   42
;    DEFINE.MIC 	     Simulation and Assembly Control Fields						      /REV=
;
;1248
;1249	;	Simulation and assembly control fields, continued.
;1250
;1251	;	This field determines if the SIM.ADDR field alone contains the address source or if that value
;1252	;	is offset +/- a constant.
;1253	;
;1254	;	NOTE: PEBOX.PAS HAS INTIMATE KNOWLEDGE OF THESE DEFINITIONS.
;1255
;1256	SIM.ADDR.SEL/=<77>,.DEFAULT=<SIM.ADDR.SEL/ADDR.K>
;1257
;1258		ADDR			=  0	; Compute address from SIM.ADDR
;1259		ADDR.K			=  1	; Compute address from SIM.ADDR +/- constant
;1260
;1261	;	This field selects the address source for a memory reference.  It does not contain a valid address source
;1262	;	if the field contains NONE, or if the SIM.CTRL field contains CMD (in the latter case, this field
;1263	;	contains a simulator command instead).
;1264
;1265	SIM.ADDR/=<76:72>,.DEFAULT=<SIM.ADDR/NONE>
;1266
;1267	;	   Address Select	 Val			   Interpretation
;1268	;	----------------------	 ---	---------------------------------------------------
;1269		NONE			= 00	; No valid adress
;1270
;1271		K			= 01	; Constant from microword
;1272		EA.1			= 02	; Address of first operand specifier
;1273		EA.2			= 03	; Address of second operand specifier
;1274		EA.3			= 04	; Address of third operand specifier
;1275		SP			= 05	; Stack pointer
;1276		SP.2			= 06	; Second stack pointer value in trace
;1277		SP.EXTENT		= 07	; Farthest stack extent for CALLx, RET, PUSHR, POPR
;1278		CASE			= 08	; Address of CASE displacement
;1279		FIELD			= 09	; Aligned address of bit field
;1280		QUEUE.1 		= 0A	; First queue reference
;1281		QUEUE.2 		= 0B	; Second queue instruction
;1282		QUEUE.HDR		= 0C	; Queue header address
;1283		PCB			= 0D	; Process control block base address
;1284		SCB			= 0E	; System control block base address
;1285		PROBE			= 0F	; Probe extent address
;1286
;1287	;				= 10	;
;1288	;				= 11	;
;1289	;				= 12	;
;1290	;				= 13	;
;1291	;				= 14	;
;1292	;				= 15	;
;1293	;				= 16	;
;1294	;				= 17	;
;1295	;				= 18	;
;1296	;				= 19	;
;1297	;				= 1A	;
;1298	;				= 1B	;
;1299	;				= 1C	;
;1300	;				= 1D	;
;1301	;				= 1E	;
;1302	;				= 1F	;
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   43
;    DEFINE.MIC 	     Simulation and Assembly Control Fields						      /REV=
;
;1303
;1304	;	Simulation and assembly control fields, continued.
;1305
;1306	;	This field selects the microbranch recipe to be used to generate the next microword address for
;1307	;	a conditional branch instruction.  This field only has a valid value if the SIM.COND.SEL field
;1308	;	contains SIM.COND.FNC and the SIM.CTRL field selects NONE.
;1309	;
;1310	;	NOTE: PEBOX.PAS HAS INTIMATE KNOWLEDGE OF THESE DEFINITIONS.
;1311
;1312	SIM.COND/=<70:66>,.DEFAULT=<SIM.COND/NONE>
;1313
;1314	;	   Condition Select	 Val	     General Use		S3 condition		       S4 condition
;1315	;	-----------------------  ---	----------------------- ------------------------------- -------------------------------
;1316		NONE			= 00	; None			None				None
;1317
;1318		S3.V.PS 		= 01	; Vfield		pos<=31'size=0'size<=32 	None
;1319		S3.V.A			= 02	; Vfield		0'0'pos+size<32 		None
;1320		S3.SV			= 03	; ASHx			shift count<7:5>		None
;1321		S3.CALLX		= 04	; CALLx 		mask<15>'mask<14>'0		None
;1322		S3.ACBX 		= 05	; ACBx			Operand sign'0'0		None
;1323		S34.MASK14		= 06	; PUSHR/POPR		0'mask<14>'0			0'mask<14:0>=0'0
;1324		S34.IPR 		= 07	; MxPR			0'0'0				0'1'0
;1325		S34.QUEUE		= 08	; Queue conditions	0'1'0				0'0'0
;1326		S34.000 		= 09	; Miscellaneous 	0'0'0				0'0'0
;1327		S4.QUEUE.EMPTY		= 0A	; Queue instructions	None				0'PSL<V>=1'0
;1328		S4.QUEUE.SINGLE 	= 0B	; Queue instructions	None				0'queue_addr [2]=0'0
;1329		S4.CHAR.MATCH		= 0C	; STRING		None				0'character match'0'
;1330		S4.CASEX		= 0D	; CASEx 		None				0'0'case out of range
;1331	;				= 0E	;
;1332	;				= 0F	;
;1333
;1334	;				= 10	;
;1335	;				= 11	;
;1336	;				= 12	;
;1337	;				= 13	;
;1338	;				= 14	;
;1339	;				= 15	;
;1340	;				= 16	;
;1341	;				= 17	;
;1342	;				= 18	;
;1343	;				= 19	;
;1344	;				= 1A	;
;1345	;				= 1B	;
;1346	;				= 1C	;
;1347	;				= 1D	;
;1348	;				= 1E	;
;1349	;				= 1F	;
;1350	;
;1351	;	This field is used to select whether the condition is a constant or a function defined by the SIM.COND field.
;1352	;	If the condtion is a constant, the value is in the overlapping field SIM.COND.K.
;1353	;	This field does not contain a valid value if the SIM.CTRL field selects CMD.
;1354
;1355	SIM.COND.SEL/=<71>,.DEFAULT=<SIM.COND.SEL/FNC>
;1356
;1357		FNC			=  0	; Condition in SIM.COND field
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   44
;    DEFINE.MIC 	     Simulation and Assembly Control Fields						      /REV=
;
;1358		CONST			=  1	; S3/S4 constant condition in SIM.COND.K
;1359
;1360	;	This overlapping field determines which E-box pipe segment the constant simulation condition is for.
;1361	;	The value of this bit is unpredictable if the SIM.COND.SEL field is selecting SIM.COND.FNC.
;1362
;1363	SIM.COND.S3.S4/=<70>
;1364		S3			= 0	; constant condition is for S3
;1365		S4			= 1	; constant condition is for S4
;1366
;1367	;	This overlapping field is used to supply a 3-bit constant when the SIM.COND.SEL field contains SIM.COND.K
;1368
;1369	SIM.COND.K/=<68:66>
;1370
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   45
;    DEFINE.MIC 	     Validity Checks									      /REV=
;
;1371	.TOC	"	Validity Checks"
;1372
;1373
;1374	;	A field must contain reference to S1.
;1375	.SET/A.S1=<.EQL[<A/>,<A/S1>]>
;1376
;1377	;	B field must contain reference to S1.
;1378	.SET/B.S1=<.EQL[<B/>,<B/S1>]>
;1379
;1380	;	B field must not contain reference to S1
;1381	.SET/B.NOT.S1=<.NEQ[<B/>,<B/S1>]>
;1382
;1383	;	SEQ.MUX field must contain LAST CYCLE or LAST CYCLE OVERFLOW.
;1384	.SET/MUX.LAST=<.OR[<.EQL[<SEQ.MUX/>,<SEQ.MUX/LAST.CYCLE>]>,
;1385			   <.EQL[<SEQ.MUX/>,<SEQ.MUX/LAST.CYCLE.OVERFLOW>]>]>
;1386
;1387	;	MRQ field must contain effective NOP
;1388	.SET/MRQ.NOP=<.OR[<.EQL[<MRQ/>,<MRQ/NOP>]>,
;1389			  <.EQL[<MRQ/>,<MRQ/SYNC.BDISP>]>,
;1390			  <.EQL[<MRQ/>,<MRQ/SYNC.BDISP.RETIRE>]>,
;1391			  <.EQL[<MRQ/>,<MRQ/SYNC.BDISP.TEST.PRED>]>]>
;1392
;1393	;	MRQ field must not contain effective NOP
;1394	.SET/MRQ.REQ=<.AND[<.NEQ[<MRQ/>,<MRQ/NOP>]>,
;1395			   <.NEQ[<MRQ/>,<MRQ/SYNC.BDISP>]>,
;1396			   <.NEQ[<MRQ/>,<MRQ/SYNC.BDISP.RETIRE>]>,
;1397			   <.NEQ[<MRQ/>,<MRQ/SYNC.BDISP.TEST.PRED>]>]>
;1398
;1399	;	LIT field must contain LIT decode
;1400	.SET/LIT.LIT=<.EQL[<LIT/>,<LIT/LIT>]>
;1401
;1402	;	DST field must contain a working register
;1403	.SET/DST.WN=<.AND[<.GEQ[<DST/>,<DST/W0>]>,<.LEQ[<DST/>,<DST/W5>]>]>
;1404
;1405	;	DST field must contain a GPR
;1406	.SET/DST.RN=<.AND[<.GEQ[<DST/>,<DST/R0>]>,<.LEQ[<DST/>,<DST/SP>]>]>
;1407
;1408	;	DST field must contain a working register or a GPR
;1409	.SET/DST.WN.OR.RN=<.OR[<DST.WN>,<DST.RN>]>
;1410
;1411	.cref
				;1412	.bin
				;1413	.ecode
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   46
;     MACRO.MIC 	     MACRO.MIC -- Macro Definitions							      /REV=
;
				;1414	.TOC	"MACRO.MIC -- Macro Definitions"
				;1415	.TOC	"Revision 1.1"
				;1416
				;1417	;	Bob Supnik
				;1418
;1419	.nobin
;1420	;****************************************************************************
;1421	;*									    *
;1422	;*  COPYRIGHT (c) 1987, 1988, 1989, 1990, 1991, 1992 BY 		    *
;1423	;*  DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASSACHUSETTS.		    *
;1424	;*  ALL RIGHTS RESERVED.						    *
;1425	;*									    *
;1426	;*  THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED   *
;1427	;*  ONLY IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE   *
;1428	;*  INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE OR ANY  OTHER   *
;1429	;*  COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY   *
;1430	;*  OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE IS  HEREBY   *
;1431	;*  TRANSFERRED.							    *
;1432	;*									    *
;1433	;*  THE INFORMATION IN THIS SOFTWARE IS  SUBJECT TO CHANGE WITHOUT NOTICE   *
;1434	;*  AND  SHOULD  NOT  BE  CONSTRUED AS	A COMMITMENT BY DIGITAL EQUIPMENT   *
;1435	;*  CORPORATION.							    *
;1436	;*									    *
;1437	;*  DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE  OR  RELIABILITY OF ITS   *
;1438	;*  SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.		    *
;1439	;*									    *
;1440	;****************************************************************************
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   47
;     MACRO.MIC 	     Revision History									      /REV=
;
;1441	.TOC	"	Revision History"
;1442
;1443	; Edit	  Date	 Who	     Description
;1444	; ---- --------- ---	---------------------
;1445	;    1 20-May-91 GMU	Symptom: No macro to invoke a console halt with
;1446	;				 no cleanup.
;1447	;			Cure:	 Add CONSOLE HALT NO CLEANUP []
;1448	; (1)0 17-Jul-90 GMU	Initial production microcode.
;1449	;
;1450	; Begin version 1.0 here
;1451	;   25 04-Jul-90 GMU	Add performance monitoring facility macros.
;1452	;   24 01-May-90 GMU	Change position of machine check code field in MACHINE CHECK
;1453	;			macro.
;1454	;   23 23-Feb-90 GMU	Add new macros for MxPr rewrite.
;1455	;   22 20-Feb-90 GMU	Remove macros that reference unused decodes.
;1456	;   21 12-Feb-90 GMU	Add sim ie.intexc macro.
;1457	;   20 19-JAN-90 GMU	FLUSH BRANCH PREDICTION CACHE -> FLUSH BRANCH PREDICTION TABLE.
;1458	;   19 12-Dec-89 GMU	Remove SYNC FBOX macro.
;1459	;   18 07-Dec-89 GMU	Move soon-to-be-obsolted macros to the end for easy
;1460	;			removal later.
;1461	;   17 06-Dec-89 GMU	Rename FLUSH BPC to FLUSH BRANCH PREDICTION CACHE.
;1462	;   16 30-Nov-89 GMU	Add [] - [] - 1 macro, remove ALU macros that use
;1463	;			PSL<C> carry-in.
;1464	;   15 17-Nov-89 GMU	Remove obsolete macros.
;1465	;   14 08-Nov-89 GMU	Remove edit 13.
;1466	;   13 04-Nov-89 GMU	Clear state<3:0> in CONSOLE HALT MACRO.
;1467	;   12 19-Oct-89 DGM	Add NODST macros for all ALU operations
;1468	;   11 18-OCT-89 GMU	Add PCB read/write macros.
;1469	;   10 28-Sep-89 GMU	Add new probe macro.
;1470	;    9 21-Sep-89 GMU	Add new macros.
;1471	;    8 20-Sep-89 GMU	Add macros for MRQ/TB.TAG.FILL and MRQ/TB.PTE.FILL.
;1472	;    7 11-Sep-89 GMU	Add .MODE to PROBE macros to emphasize mode is from register.
;1473	;    6 15-Aug-89 GMU	Turn CLEAR WRITE BUFFERS macro into MRQ/NOP for now.
;1474	;    5	2-Aug-89 DGM	Modified SMUL and UDIV macros to update Q
;1475	;    4 12-Jul-89 GMU	Added definitions to support CPU init on exception.
;1476	;    3 30-Jun-89 DGM	Added macros: SMUL ; NODST <-- PASSx ; MULL
;1477	;    2 28-Jun-89 GMU	Corrected error in retire branch queue macro.
;1478	;    1 22-Nov-88 DB	Add FBOX DEST CHECK
;1479	; (0)0 14-Sep-87 RMS	Trial microcode.
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   48
;     MACRO.MIC 	     ALU Macros 									      /REV=
;
;1480	.TOC	"	ALU Macros"
;1481
;1482	;	ALU macros with register operands that drive the Wbus.
;1483
;1484	[] <-- [] + []			"LIT/BREG,ALU/A.PLUS.B,DST/@1,A/@2,B/@3,W/ALU"
;1485	[] <-- [] + [] + 1		"LIT/BREG,ALU/A.PLUS.B.PLUS.1,DST/@1,A/@2,B/@3,W/ALU"
;1486	[] <-- [] - []			"LIT/BREG,ALU/A.MINUS.B,DST/@1,A/@2,B/@3,W/ALU"
;1487	[] <-- [] - [] - 1		"LIT/BREG,ALU/A.MINUS.B.MINUS.1,DST/@1,A/@2,B/@3,W/ALU"
;1488	[] <-- [] AND []		"LIT/BREG,ALU/A.AND.B,DST/@1,A/@2,B/@3,W/ALU"
;1489	[] <-- NOT [] AND []		"LIT/BREG,ALU/NOT.A.AND.B,DST/@1,A/@2,B/@3,W/ALU"
;1490	[] <-- [] ANDNOT []		"LIT/BREG,ALU/A.AND.NOT.B,DST/@1,A/@2,B/@3,W/ALU"
;1491	[] <-- [] OR [] 		"LIT/BREG,ALU/A.OR.B,DST/@1,A/@2,B/@3,W/ALU"
;1492	[] <-- [] XOR []		"LIT/BREG,ALU/A.XOR.B,DST/@1,A/@2,B/@3,W/ALU"
;1493	[] <-- (-[] + [])		"LIT/BREG,ALU/B.MINUS.A,DST/@1,A/@2,B/@3,W/ALU"
;1494	[] <-- [] UDIV []		"FORMAT/STANDARD,LIT/BREG,ALU/UDIV.STEP,SHF/NOP,DST/@1,A/@2,B/@3,W/ALU,Q/UPDATE.Q"
;1495	[] <-- [] SMUL []		"FORMAT/STANDARD,LIT/BREG,ALU/SMUL.STEP,SHF/NOP,DST/@1,A/@2,B/@3,W/ALU,Q/UPDATE.Q"
;1496
;1497	[] <-- []			"ALU/PASS.A,DST/@1,A/@2,W/ALU"
;1498	[] <-- [] + 1			"ALU/A.PLUS.1,DST/@1,A/@2,W/ALU"
;1499	[] <-- [] - 1			"ALU/A.MINUS.1,DST/@1,A/@2,W/ALU"
;1500	[] <-- [] + 4			"ALU/A.PLUS.4,DST/@1,A/@2,W/ALU"
;1501	[] <-- [] - 4			"ALU/A.MINUS.4,DST/@1,A/@2,W/ALU"
;1502	[] <-- -[]			"LIT/BREG,ALU/NEG.B,DST/@1,B/@2,W/ALU"
;1503	[] <-- NOT []			"LIT/BREG,ALU/NOT.B,DST/@1,B/@2,W/ALU"
;1504	[] <-- B []			"LIT/BREG,ALU/PASS.B,DST/@1,B/@2,W/ALU"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   49
;     MACRO.MIC 	     ALU Macros 									      /REV=
;
;1505
;1506	;	ALU macros, continued.
;1507
;1508	;	ALU macros with register operands that drive VA.
;1509
;1510	VA <-- [] + []			"LIT/BREG,ALU/A.PLUS.B,A/@1,B/@2,V/UPDATE.VA"
;1511	VA <-- [] + [] + 1		"LIT/BREG,ALU/A.PLUS.B.PLUS.1,A/@1,B/@2,V/UPDATE.VA"
;1512	VA <-- [] - []			"LIT/BREG,ALU/A.MINUS.B,A/@1,B/@2,V/UPDATE.VA"
;1513	VA <-- [] AND []		"LIT/BREG,ALU/A.AND.B,A/@1,B/@2,V/UPDATE.VA"
;1514	VA <-- NOT [] AND []		"LIT/BREG,ALU/NOT.A.AND.B,A/@1,B/@2,V/UPDATE.VA"
;1515	VA <-- [] ANDNOT []		"LIT/BREG,ALU/A.AND.NOT.B,A/@1,B/@2,V/UPDATE.VA"
;1516	VA <-- [] OR [] 		"LIT/BREG,ALU/A.OR.B,A/@1,B/@2,V/UPDATE.VA"
;1517	VA <-- [] XOR []		"LIT/BREG,ALU/A.XOR.B,A/@1,B/@2,V/UPDATE.VA"
;1518	VA <-- (-[] + [])		"LIT/BREG,ALU/B.MINUS.A,A/@1,B/@2,V/UPDATE.VA"
;1519
;1520	VA <-- []			"ALU/PASS.A,A/@1,V/UPDATE.VA"
;1521	VA <-- [] + 1			"ALU/A.PLUS.1,A/@1,V/UPDATE.VA"
;1522	VA <-- [] - 1			"ALU/A.MINUS.1,A/@1,V/UPDATE.VA"
;1523	VA <-- [] + 4			"ALU/A.PLUS.4,A/@1,V/UPDATE.VA"
;1524	VA <-- [] - 4			"ALU/A.MINUS.4,A/@1,V/UPDATE.VA"
;1525	VA <-- -[]			"LIT/BREG,ALU/NEG.B,B/@1,V/UPDATE.VA"
;1526	VA <-- NOT []			"LIT/BREG,ALU/NOT.B,B/@1,V/UPDATE.VA"
;1527	VA <-- B []			"LIT/BREG,ALU/PASS.B,B/@1,V/UPDATE.VA"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   50
;     MACRO.MIC 	     ALU Macros 									      /REV=
;
;1528
;1529	;	ALU macros, continued.
;1530
;1531	;	ALU macros with constant operand that drive the Wbus.
;1532
;1533	[] <-- [] + K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.PLUS.B,CONST.10/@3,DST/@1,A/@2,W/ALU"
;1534	[] <-- [] - K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.MINUS.B,CONST.10/@3,DST/@1,A/@2,W/ALU"
;1535	[] <-- K10.[] - []		"LIT/LIT,MISC/CONST.10.BIT,ALU/B.MINUS.A,CONST.10/@2,DST/@1,A/@3,W/ALU"
;1536	[] <-- [] AND K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.AND.B,CONST.10/@3,DST/@1,A/@2,W/ALU"
;1537	[] <-- [] OR K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.OR.B,CONST.10/@3,DST/@1,A/@2,W/ALU"
;1538	[] <-- [] ANDNOT K10.[] 	"LIT/LIT,MISC/CONST.10.BIT,ALU/A.AND.NOT.B,CONST.10/@3,DST/@1,A/@2,W/ALU"
;1539	[] <-- [] XOR K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.XOR.B,CONST.10/@3,DST/@1,A/@2,W/ALU"
;1540	[] <-- NOT K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/NOT.B,CONST.10/@2,DST/@1,W/ALU"
;1541	[] <-- -K10.[]			"LIT/LIT,MISC/CONST.10.BIT,ALU/NEG.B,CONST.10/@2,DST/@1,W/ALU"
;1542	[] <-- K10.[]			"LIT/LIT,MISC/CONST.10.BIT,ALU/PASS.B,CONST.10/@2,DST/@1,W/ALU"
;1543
;1544	[] <-- [] + 000000[]		"LIT/LIT,POS/BYTE0,ALU/A.PLUS.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1545	[] <-- [] - 000000[]		"LIT/LIT,POS/BYTE0,ALU/A.MINUS.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1546	[] <-- 000000[] - []		"LIT/LIT,POS/BYTE0,ALU/B.MINUS.A,CONST/@2,DST/@1,A/@3,W/ALU"
;1547	[] <-- [] AND 000000[]		"LIT/LIT,POS/BYTE0,ALU/A.AND.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1548	[] <-- [] OR 000000[]		"LIT/LIT,POS/BYTE0,ALU/A.OR.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1549	[] <-- [] ANDNOT 000000[]	"LIT/LIT,POS/BYTE0,ALU/A.AND.NOT.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1550	[] <-- [] XOR 000000[]		"LIT/LIT,POS/BYTE0,ALU/A.XOR.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1551	[] <-- NOT 000000[]		"LIT/LIT,POS/BYTE0,ALU/NOT.B,CONST/@2,DST/@1,W/ALU"
;1552	[] <-- -000000[]		"LIT/LIT,POS/BYTE0,ALU/NEG.B,CONST/@2,DST/@1,W/ALU"
;1553	[] <-- 000000[] 		"LIT/LIT,POS/BYTE0,ALU/PASS.B,CONST/@2,DST/@1,W/ALU"
;1554
;1555	[] <-- [] + 0000[]00		"LIT/LIT,POS/BYTE1,ALU/A.PLUS.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1556	[] <-- [] - 0000[]00		"LIT/LIT,POS/BYTE1,ALU/A.MINUS.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1557	[] <-- 0000[]00 - []		"LIT/LIT,POS/BYTE1,ALU/B.MINUS.A,CONST/@2,DST/@1,A/@3,W/ALU"
;1558	[] <-- [] AND 0000[]00		"LIT/LIT,POS/BYTE1,ALU/A.AND.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1559	[] <-- [] OR 0000[]00		"LIT/LIT,POS/BYTE1,ALU/A.OR.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1560	[] <-- [] ANDNOT 0000[]00	"LIT/LIT,POS/BYTE1,ALU/A.AND.NOT.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1561	[] <-- [] XOR 0000[]00		"LIT/LIT,POS/BYTE1,ALU/A.XOR.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1562	[] <-- NOT 0000[]00		"LIT/LIT,POS/BYTE1,ALU/NOT.B,CONST/@2,DST/@1,W/ALU"
;1563	[] <-- -0000[]00		"LIT/LIT,POS/BYTE1,ALU/NEG.B,CONST/@2,DST/@1,W/ALU"
;1564	[] <-- 0000[]00 		"LIT/LIT,POS/BYTE1,ALU/PASS.B,CONST/@2,DST/@1,W/ALU"
;1565
;1566	[] <-- [] + 00[]0000		"LIT/LIT,POS/BYTE2,ALU/A.PLUS.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1567	[] <-- [] - 00[]0000		"LIT/LIT,POS/BYTE2,ALU/A.MINUS.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1568	[] <-- 00[]0000 - []		"LIT/LIT,POS/BYTE2,ALU/B.MINUS.A,CONST/@2,DST/@1,A/@3,W/ALU"
;1569	[] <-- [] AND 00[]0000		"LIT/LIT,POS/BYTE2,ALU/A.AND.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1570	[] <-- [] OR 00[]0000		"LIT/LIT,POS/BYTE2,ALU/A.OR.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1571	[] <-- [] ANDNOT 00[]0000	"LIT/LIT,POS/BYTE2,ALU/A.AND.NOT.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1572	[] <-- [] XOR 00[]0000		"LIT/LIT,POS/BYTE2,ALU/A.XOR.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1573	[] <-- NOT 00[]0000		"LIT/LIT,POS/BYTE2,ALU/NOT.B,CONST/@2,DST/@1,W/ALU"
;1574	[] <-- -00[]0000		"LIT/LIT,POS/BYTE2,ALU/NEG.B,CONST/@2,DST/@1,W/ALU"
;1575	[] <-- 00[]0000 		"LIT/LIT,POS/BYTE2,ALU/PASS.B,CONST/@2,DST/@1,W/ALU"
;1576
;1577	[] <-- [] + []000000		"LIT/LIT,POS/BYTE3,ALU/A.PLUS.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1578	[] <-- [] - []000000		"LIT/LIT,POS/BYTE3,ALU/A.MINUS.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1579	[] <-- []000000 - []		"LIT/LIT,POS/BYTE3,ALU/B.MINUS.A,CONST/@2,DST/@1,A/@3,W/ALU"
;1580	[] <-- [] AND []000000		"LIT/LIT,POS/BYTE3,ALU/A.AND.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1581	[] <-- [] OR []000000		"LIT/LIT,POS/BYTE3,ALU/A.OR.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1582	[] <-- [] ANDNOT []000000	"LIT/LIT,POS/BYTE3,ALU/A.AND.NOT.B,CONST/@3,DST/@1,A/@2,W/ALU"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   51
;     MACRO.MIC 	     ALU Macros 									      /REV=
;
;1583	[] <-- [] XOR []000000		"LIT/LIT,POS/BYTE3,ALU/A.XOR.B,CONST/@3,DST/@1,A/@2,W/ALU"
;1584	[] <-- NOT []000000		"LIT/LIT,POS/BYTE3,ALU/NOT.B,CONST/@2,DST/@1,W/ALU"
;1585	[] <-- -[]000000		"LIT/LIT,POS/BYTE3,ALU/NEG.B,CONST/@2,DST/@1,W/ALU"
;1586	[] <-- []000000 		"LIT/LIT,POS/BYTE3,ALU/PASS.B,CONST/@2,DST/@1,W/ALU"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   52
;     MACRO.MIC 	     ALU Macros 									      /REV=
;
;1587
;1588	;	ALU macros, continued.
;1589
;1590	;	ALU macros with constant operand that drive VA.
;1591
;1592	VA <-- [] + K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.PLUS.B,CONST.10/@2,A/@1,V/UPDATE.VA"
;1593	VA <-- [] - K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.MINUS.B,CONST.10/@2,A/@1,V/UPDATE.VA"
;1594	VA <-- K10.[] - []		"LIT/LIT,MISC/CONST.10.BIT,ALU/B.MINUS.A,CONST.10/@1,A/@2,V/UPDATE.VA"
;1595	VA <-- [] AND K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.AND.B,CONST.10/@2,A/@1,V/UPDATE.VA"
;1596	VA <-- [] OR K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.OR.B,CONST.10/@2,A/@1,V/UPDATE.VA"
;1597	VA <-- [] ANDNOT K10.[] 	"LIT/LIT,MISC/CONST.10.BIT,ALU/A.AND.NOT.B,CONST.10/@2,A/@1,V/UPDATE.VA"
;1598	VA <-- [] XOR K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.XOR.B,CONST.10/@2,A/@1,V/UPDATE.VA"
;1599	VA <-- NOT K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/NOT.B,CONST.10/@1,V/UPDATE.VA"
;1600	VA <-- -K10.[]			"LIT/LIT,MISC/CONST.10.BIT,ALU/NEG.B,CONST.10/@1,V/UPDATE.VA"
;1601	VA <-- K10.[]			"LIT/LIT,MISC/CONST.10.BIT,ALU/PASS.B,CONST.10/@1,V/UPDATE.VA"
;1602
;1603	VA <-- [] + 000000[]		"LIT/LIT,POS/BYTE0,ALU/A.PLUS.B,CONST/@2,A/@1,V/UPDATE.VA"
;1604	VA <-- [] - 000000[]		"LIT/LIT,POS/BYTE0,ALU/A.MINUS.B,CONST/@2,A/@1,V/UPDATE.VA"
;1605	VA <-- 000000[] - []		"LIT/LIT,POS/BYTE0,ALU/B.MINUS.A,CONST/@1,A/@2,V/UPDATE.VA"
;1606	VA <-- [] AND 000000[]		"LIT/LIT,POS/BYTE0,ALU/A.AND.B,CONST/@2,A/@1,V/UPDATE.VA"
;1607	VA <-- [] OR 000000[]		"LIT/LIT,POS/BYTE0,ALU/A.OR.B,CONST/@2,A/@1,V/UPDATE.VA"
;1608	VA <-- [] ANDNOT 000000[]	"LIT/LIT,POS/BYTE0,ALU/A.AND.NOT.B,CONST/@2,A/@1,V/UPDATE.VA"
;1609	VA <-- [] XOR 000000[]		"LIT/LIT,POS/BYTE0,ALU/A.XOR.B,CONST/@2,A/@1,V/UPDATE.VA"
;1610	VA <-- NOT 000000[]		"LIT/LIT,POS/BYTE0,ALU/NOT.B,CONST/@1,V/UPDATE.VA"
;1611	VA <-- -000000[]		"LIT/LIT,POS/BYTE0,ALU/NEG.B,CONST/@1,V/UPDATE.VA"
;1612	VA <-- 000000[] 		"LIT/LIT,POS/BYTE0,ALU/PASS.B,CONST/@1,V/UPDATE.VA"
;1613
;1614	VA <-- [] + 0000[]00		"LIT/LIT,POS/BYTE1,ALU/A.PLUS.B,CONST/@2,A/@1,V/UPDATE.VA"
;1615	VA <-- [] - 0000[]00		"LIT/LIT,POS/BYTE1,ALU/A.MINUS.B,CONST/@2,A/@1,V/UPDATE.VA"
;1616	VA <-- 0000[]00 - []		"LIT/LIT,POS/BYTE1,ALU/B.MINUS.A,CONST/@1,A/@2,V/UPDATE.VA"
;1617	VA <-- [] AND 0000[]00		"LIT/LIT,POS/BYTE1,ALU/A.AND.B,CONST/@2,A/@1,V/UPDATE.VA"
;1618	VA <-- [] OR 0000[]00		"LIT/LIT,POS/BYTE1,ALU/A.OR.B,CONST/@2,A/@1,V/UPDATE.VA"
;1619	VA <-- [] ANDNOT 0000[]00	"LIT/LIT,POS/BYTE1,ALU/A.AND.NOT.B,CONST/@2,A/@1,V/UPDATE.VA"
;1620	VA <-- [] XOR 0000[]00		"LIT/LIT,POS/BYTE1,ALU/A.XOR.B,CONST/@2,A/@1,V/UPDATE.VA"
;1621	VA <-- NOT 0000[]00		"LIT/LIT,POS/BYTE1,ALU/NOT.B,CONST/@1,V/UPDATE.VA"
;1622	VA <-- -0000[]00		"LIT/LIT,POS/BYTE1,ALU/NEG.B,CONST/@1,V/UPDATE.VA"
;1623	VA <-- 0000[]00 		"LIT/LIT,POS/BYTE1,ALU/PASS.B,CONST/@1,V/UPDATE.VA"
;1624
;1625	VA <-- [] + 00[]0000		"LIT/LIT,POS/BYTE2,ALU/A.PLUS.B,CONST/@2,A/@1,V/UPDATE.VA"
;1626	VA <-- [] - 00[]0000		"LIT/LIT,POS/BYTE2,ALU/A.MINUS.B,CONST/@2,A/@1,V/UPDATE.VA"
;1627	VA <-- 00[]0000 - []		"LIT/LIT,POS/BYTE2,ALU/B.MINUS.A,CONST/@1,A/@2,V/UPDATE.VA"
;1628	VA <-- [] AND 00[]0000		"LIT/LIT,POS/BYTE2,ALU/A.AND.B,CONST/@2,A/@1,V/UPDATE.VA"
;1629	VA <-- [] OR 00[]0000		"LIT/LIT,POS/BYTE2,ALU/A.OR.B,CONST/@2,A/@1,V/UPDATE.VA"
;1630	VA <-- [] ANDNOT 00[]0000	"LIT/LIT,POS/BYTE2,ALU/A.AND.NOT.B,CONST/@2,A/@1,V/UPDATE.VA"
;1631	VA <-- [] XOR 00[]0000		"LIT/LIT,POS/BYTE2,ALU/A.XOR.B,CONST/@2,A/@1,V/UPDATE.VA"
;1632	VA <-- NOT 00[]0000		"LIT/LIT,POS/BYTE2,ALU/NOT.B,CONST/@1,V/UPDATE.VA"
;1633	VA <-- -00[]0000		"LIT/LIT,POS/BYTE2,ALU/NEG.B,CONST/@1,V/UPDATE.VA"
;1634	VA <-- 00[]0000 		"LIT/LIT,POS/BYTE2,ALU/PASS.B,CONST/@1,V/UPDATE.VA"
;1635
;1636	VA <-- [] + []000000		"LIT/LIT,POS/BYTE3,ALU/A.PLUS.B,CONST/@2,A/@1,V/UPDATE.VA"
;1637	VA <-- [] - []000000		"LIT/LIT,POS/BYTE3,ALU/A.MINUS.B,CONST/@2,A/@1,V/UPDATE.VA"
;1638	VA <-- []000000 - []		"LIT/LIT,POS/BYTE3,ALU/B.MINUS.A,CONST/@1,A/@2,V/UPDATE.VA"
;1639	VA <-- [] AND []000000		"LIT/LIT,POS/BYTE3,ALU/A.AND.B,CONST/@2,A/@1,V/UPDATE.VA"
;1640	VA <-- [] OR []000000		"LIT/LIT,POS/BYTE3,ALU/A.OR.B,CONST/@2,A/@1,V/UPDATE.VA"
;1641	VA <-- [] ANDNOT []000000	"LIT/LIT,POS/BYTE3,ALU/A.AND.NOT.B,CONST/@2,A/@1,V/UPDATE.VA"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   53
;     MACRO.MIC 	     ALU Macros 									      /REV=
;
;1642	VA <-- [] XOR []000000		"LIT/LIT,POS/BYTE3,ALU/A.XOR.B,CONST/@2,A/@1,V/UPDATE.VA"
;1643	VA <-- NOT []000000		"LIT/LIT,POS/BYTE3,ALU/NOT.B,CONST/@1,V/UPDATE.VA"
;1644	VA <-- -[]000000		"LIT/LIT,POS/BYTE3,ALU/NEG.B,CONST/@1,V/UPDATE.VA"
;1645	VA <-- []000000 		"LIT/LIT,POS/BYTE3,ALU/PASS.B,CONST/@1,V/UPDATE.VA"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   54
;     MACRO.MIC 	     ALU Macros 									      /REV=
;
;1646
;1647	;	ALU macros, continued.
;1648
;1649	;	ALU macros with register operands that have no destination.
;1650
;1651	NODST <-- [] + []		"LIT/BREG,ALU/A.PLUS.B,A/@1,B/@2"
;1652	NODST <-- [] + [] + 1		"LIT/BREG,ALU/A.PLUS.B.PLUS.1,A/@1,B/@2"
;1653	NODST <-- [] - []		"LIT/BREG,ALU/A.MINUS.B,A/@1,B/@2"
;1654	NODST <-- [] AND []		"LIT/BREG,ALU/A.AND.B,A/@1,B/@2"
;1655	NODST <-- NOT [] AND [] 	"LIT/BREG,ALU/NOT.A.AND.B,A/@1,B/@2"
;1656	NODST <-- [] ANDNOT []		"LIT/BREG,ALU/A.AND.NOT.B,A/@1,B/@2"
;1657	NODST <-- [] OR []		"LIT/BREG,ALU/A.OR.B,A/@1,B/@2"
;1658	NODST <-- [] XOR []		"LIT/BREG,ALU/A.XOR.B,A/@1,B/@2"
;1659	NODST <-- (-[] + [])		"LIT/BREG,ALU/B.MINUS.A,A/@1,B/@2"
;1660
;1661	NODST <-- []			"ALU/PASS.A,A/@1"
;1662	NODST <-- [] + 1		"ALU/A.PLUS.1,A/@1"
;1663	NODST <-- [] - 1		"ALU/A.MINUS.1,A/@1"
;1664	NODST <-- [] + 4		"ALU/A.PLUS.4,A/@1"
;1665	NODST <-- [] - 4		"ALU/A.MINUS.4,A/@1"
;1666	NODST <-- -[]			"LIT/BREG,ALU/NEG.B,B/@1"
;1667	NODST <-- NOT []		"LIT/BREG,ALU/NOT.B,B/@1"
;1668	NODST <-- B []			"LIT/BREG,ALU/PASS.B,B/@1"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   55
;     MACRO.MIC 	     ALU Macros 									      /REV=
;
;1669
;1670	;	ALU macros, continued.
;1671
;1672	;	ALU macros with constant operand that have no destination.
;1673
;1674	NODST <-- [] + K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.PLUS.B,CONST.10/@2,A/@1"
;1675	NODST <-- [] - K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.MINUS.B,CONST.10/@2,A/@1"
;1676	NODST <-- K10.[] - []		"LIT/LIT,MISC/CONST.10.BIT,ALU/B.MINUS.A,CONST.10/@1,A/@2"
;1677	NODST <-- [] AND K10.[] 	"LIT/LIT,MISC/CONST.10.BIT,ALU/A.AND.B,CONST.10/@2,A/@1"
;1678	NODST <-- [] OR K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/A.OR.B,CONST.10/@2,A/@1"
;1679	NODST <-- [] ANDNOT K10.[]	"LIT/LIT,MISC/CONST.10.BIT,ALU/A.AND.NOT.B,CONST.10/@2,A/@1"
;1680	NODST <-- [] XOR K10.[] 	"LIT/LIT,MISC/CONST.10.BIT,ALU/A.XOR.B,CONST.10/@2,A/@1"
;1681	NODST <-- NOT K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/NOT.B,CONST.10/@1"
;1682	NODST <-- -K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/NEG.B,CONST.10/@1"
;1683	NODST <-- K10.[]		"LIT/LIT,MISC/CONST.10.BIT,ALU/PASS.B,CONST.10/@1"
;1684
;1685	NODST <-- [] + 000000[] 	"LIT/LIT,POS/BYTE0,ALU/A.PLUS.B,CONST/@2,A/@1"
;1686	NODST <-- [] - 000000[] 	"LIT/LIT,POS/BYTE0,ALU/A.MINUS.B,CONST/@2,A/@1"
;1687	NODST <-- 000000[] - [] 	"LIT/LIT,POS/BYTE0,ALU/B.MINUS.A,CONST/@1,A/@2"
;1688	NODST <-- [] AND 000000[]	"LIT/LIT,POS/BYTE0,ALU/A.AND.B,CONST/@2,A/@1"
;1689	NODST <-- [] OR 000000[]	"LIT/LIT,POS/BYTE0,ALU/A.OR.B,CONST/@2,A/@1"
;1690	NODST <-- [] ANDNOT 000000[]	"LIT/LIT,POS/BYTE0,ALU/A.AND.NOT.B,CONST/@2,A/@1"
;1691	NODST <-- [] XOR 000000[]	"LIT/LIT,POS/BYTE0,ALU/A.XOR.B,CONST/@2,A/@1"
;1692	NODST <-- NOT 000000[]		"LIT/LIT,POS/BYTE0,ALU/NOT.B,CONST/@1"
;1693	NODST <-- -000000[]		"LIT/LIT,POS/BYTE0,ALU/NEG.B,CONST/@1"
;1694	NODST <-- 000000[]		"LIT/LIT,POS/BYTE0,ALU/PASS.B,CONST/@1"
;1695
;1696	NODST <-- [] + 0000[]00 	"LIT/LIT,POS/BYTE1,ALU/A.PLUS.B,CONST/@2,A/@1"
;1697	NODST <-- [] - 0000[]00 	"LIT/LIT,POS/BYTE1,ALU/A.MINUS.B,CONST/@2,A/@1"
;1698	NODST <-- 0000[]00 - [] 	"LIT/LIT,POS/BYTE1,ALU/B.MINUS.A,CONST/@1,A/@2"
;1699	NODST <-- [] AND 0000[]00	"LIT/LIT,POS/BYTE1,ALU/A.AND.B,CONST/@2,A/@1"
;1700	NODST <-- [] OR 0000[]00	"LIT/LIT,POS/BYTE1,ALU/A.OR.B,CONST/@2,A/@1"
;1701	NODST <-- [] ANDNOT 0000[]00	"LIT/LIT,POS/BYTE1,ALU/A.AND.NOT.B,CONST/@2,A/@1"
;1702	NODST <-- [] XOR 0000[]00	"LIT/LIT,POS/BYTE1,ALU/A.XOR.B,CONST/@2,A/@1"
;1703	NODST <-- NOT 0000[]00		"LIT/LIT,POS/BYTE1,ALU/NOT.B,CONST/@1"
;1704	NODST <-- -0000[]00		"LIT/LIT,POS/BYTE1,ALU/NEG.B,CONST/@1"
;1705	NODST <-- 0000[]00		"LIT/LIT,POS/BYTE1,ALU/PASS.B,CONST/@1"
;1706
;1707	NODST <-- [] + 00[]0000 	"LIT/LIT,POS/BYTE2,ALU/A.PLUS.B,CONST/@2,A/@1"
;1708	NODST <-- [] - 00[]0000 	"LIT/LIT,POS/BYTE2,ALU/A.MINUS.B,CONST/@2,A/@1"
;1709	NODST <-- 00[]0000 - [] 	"LIT/LIT,POS/BYTE2,ALU/B.MINUS.A,CONST/@1,A/@2"
;1710	NODST <-- [] AND 00[]0000	"LIT/LIT,POS/BYTE2,ALU/A.AND.B,CONST/@2,A/@1"
;1711	NODST <-- [] OR 00[]0000	"LIT/LIT,POS/BYTE2,ALU/A.OR.B,CONST/@2,A/@1"
;1712	NODST <-- [] ANDNOT 00[]0000	"LIT/LIT,POS/BYTE2,ALU/A.AND.NOT.B,CONST/@2,A/@1"
;1713	NODST <-- [] XOR 00[]0000	"LIT/LIT,POS/BYTE2,ALU/A.XOR.B,CONST/@2,A/@1"
;1714	NODST <-- NOT 00[]0000		"LIT/LIT,POS/BYTE2,ALU/NOT.B,CONST/@1"
;1715	NODST <-- -00[]0000		"LIT/LIT,POS/BYTE2,ALU/NEG.B,CONST/@1"
;1716	NODST <-- 00[]0000		"LIT/LIT,POS/BYTE2,ALU/PASS.B,CONST/@1"
;1717
;1718	NODST <-- [] + []000000 	"LIT/LIT,POS/BYTE3,ALU/A.PLUS.B,CONST/@2,A/@1"
;1719	NODST <-- [] - []000000 	"LIT/LIT,POS/BYTE3,ALU/A.MINUS.B,CONST/@2,A/@1"
;1720	NODST <-- []000000 - [] 	"LIT/LIT,POS/BYTE3,ALU/B.MINUS.A,CONST/@1,A/@2"
;1721	NODST <-- [] AND []000000	"LIT/LIT,POS/BYTE3,ALU/A.AND.B,CONST/@2,A/@1"
;1722	NODST <-- [] OR []000000	"LIT/LIT,POS/BYTE3,ALU/A.OR.B,CONST/@2,A/@1"
;1723	NODST <-- [] ANDNOT []000000	"LIT/LIT,POS/BYTE3,ALU/A.AND.NOT.B,CONST/@2,A/@1"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   56
;     MACRO.MIC 	     ALU Macros 									      /REV=
;
;1724	NODST <-- [] XOR []000000	"LIT/LIT,POS/BYTE3,ALU/A.XOR.B,CONST/@2,A/@1"
;1725	NODST <-- NOT []000000		"LIT/LIT,POS/BYTE3,ALU/NOT.B,CONST/@1"
;1726	NODST <-- -[]000000		"LIT/LIT,POS/BYTE3,ALU/NEG.B,CONST/@1"
;1727	NODST <-- []000000		"LIT/LIT,POS/BYTE3,ALU/PASS.B,CONST/@1"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   57
;     MACRO.MIC 	     ALU Macros 									      /REV=
;
;1728
;1729	;	ALU macros, continued.
;1730
;1731	;	Special ALU macros.
;1732
;1733	NOP				"[WBUS] <-- [NONE],LONG"
;1734	NOP NODEST			"[NONE] <-- [NONE],LONG"
;1735	SET PSL(V)			"[WBUS] <-- 000000[01],LONG,SET PSL CC.PPJP"
;1736	CLEAR PSL(V)			"[WBUS] <-- 000000[00],LONG,SET PSL CC.PPJP"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   58
;     MACRO.MIC 	     MEMREQ Macros									      /REV=
;
;1737	.TOC	"	MEMREQ Macros"
;1738
;1739	[] <-- MEM (VA) 		"MRQ/READ.V.RCHK,DST/@1"
;1740	[] <-- MEM.PR (VA)		"MRQ/READ.PR,DST/@1"
;1741	[] <-- MEM.LOCK (VA)		"MRQ/READ.V.LOCK,DST/@1"
;1742	[] <-- MEM.SCB (VA)		"MRQ/READ.P,DST/@1"
;1743	[] <-- MEM.PCB (VA)		"MRQ/READ.P,DST/@1"
;1744	[] <-- MEM.PHYS (VA)		"MRQ/READ.P,DST/@1"
;1745	[] <-- MEM.WCHK (VA)		"MRQ/READ.V.WCHK,DST/@1"
;1746	[] <-- MEM.NOCHK (VA)		"MRQ/READ.V.NOCHK,DST/@1"
;1747	[] <-- PROBE.R.MODE (VA)	"MRQ/PROBE.V.RCHK,DST/@1"
;1748	[] <-- PROBE.W.MODE (VA)	"MRQ/PROBE.V.WCHK,DST/@1"
;1749	[] <-- PROBE.R.MODE.NOFILL (VA) "MRQ/PROBE.V.RCHK.NOFILL,DST/@1"
;1750
;1751	MEM (VA)&			"MRQ/WRITE.V.WCHK"
;1752	MEM.PR (VA)&			"MRQ/WRITE.PR"
;1753	MEM.UNLOCK (VA)&		"MRQ/WRITE.V.UNLOCK"
;1754	MEM.NOCHK (VA)& 		"MRQ/WRITE.V.NOCHK"
;1755	MEM.PHYS (VA)&			"MRQ/WRITE.P"
;1756	MEM.PCB (VA)&			"MRQ/WRITE.P"
;1757	WCHK (VA)&			"MRQ/WCHK"
;1758
;1759	SYNCHRONIZE MBOX		"MRQ/SYNC.MBOX"
;1760	TB INVALIDATE SINGLE		"MRQ/TB.INVALIDATE.SINGLE"
;1761	TB INVALIDATE PROCESS		"MRQ/TB.INVALIDATE.PROCESS"
;1762	TB INVALIDATE ALL		"MRQ/TB.INVALIDATE.ALL"
;1763	TB TAG FILL			"MRQ/TB.TAG.FILL"
;1764	TB PTE FILL			"MRQ/TB.PTE.FILL"
;1765	LOAD PC 			"MRQ/LOAD.PC"
;1766
;1767	WAIT BDISP VALID		"MRQ/SYNC.BDISP"
;1768	RETIRE UNCOND BQ ENTRY		"MRQ/SYNC.BDISP.RETIRE"
;1769	RETIRE COND BQ ENTRY		"MRQ/SYNC.BDISP.TEST.PRED"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   59
;     MACRO.MIC 	     SHIFT Macros									      /REV=
;
;1770	.TOC	"	SHIFT Macros"
;1771
;1772	;	Shift macros with register operands that drive the Wbus.
;1773
;1774	[] <-- [] LROT []		"FORMAT/STANDARD,LIT/BREG,VAL/@3,DST/@1,B/@2,A/@2,SHF/LEFT.DOUBLE,W/SHF"
;1775	[] <-- [] LROT (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,DST/@1,B/@2,A/@2,SHF/LEFT.DOUBLE,W/SHF"
;1776	[] <-- [] RROT []		"FORMAT/STANDARD,LIT/BREG,VAL/@3,DST/@1,B/@2,A/@2,SHF/RIGHT.DOUBLE,W/SHF"
;1777	[] <-- [] RROT (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,DST/@1,B/@2,A/@2,SHF/RIGHT.DOUBLE,W/SHF"
;1778	[] <-- [] RROT (32-SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,DST/@1,B/@2,A/@2,SHF/LEFT.DOUBLE,W/SHF"
;1779	[] <-- []!![] LSH []		"FORMAT/STANDARD,LIT/BREG,VAL/@4,DST/@1,B/@3,A/@2,SHF/LEFT.DOUBLE,W/SHF"
;1780	[] <-- []!![] LSH (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,DST/@1,B/@3,A/@2,SHF/LEFT.DOUBLE,W/SHF"
;1781	[] <-- []!![] RSH []		"FORMAT/STANDARD,LIT/BREG,VAL/@4,DST/@1,B/@3,A/@2,SHF/RIGHT.DOUBLE,W/SHF"
;1782	[] <-- []!![] RSH (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,DST/@1,B/@3,A/@2,SHF/RIGHT.DOUBLE,W/SHF"
;1783	[] <-- []!![] RSH (32-SC)	"FORMAT/STANDARD,LIT/BREG,VAL/0,DST/@1,B/@3,A/@2,SHF/LEFT.DOUBLE,W/SHF"
;1784	[] <-- SEXT [] RSH []		"FORMAT/STANDARD,LIT/BREG,VAL/@3,DST/@1,B/@2,A/SHIFT.SIGN,SHF/RIGHT.DOUBLE,W/SHF"
;1785	[] <-- SEXT [] RSH (SC) 	"FORMAT/STANDARD,LIT/BREG,VAL/0,DST/@1,B/@2,A/SHIFT.SIGN,SHF/RIGHT.DOUBLE,W/SHF"
;1786	[] <-- SEXT [] RSH (32-SC)	"FORMAT/STANDARD,LIT/BREG,VAL/0,DST/@1,B/@2,A/SHIFT.SIGN,SHF/LEFT.DOUBLE,W/SHF"
;1787
;1788	[] <-- PASSA [] 		"FORMAT/STANDARD,DST/@1,A/@2,SHF/PASS.A,W/SHF"
;1789	[] <-- PASSB [] 		"FORMAT/STANDARD,LIT/BREG,DST/@1,B/@2,SHF/PASS.B,W/SHF"
;1790	[] <-- 0			"FORMAT/STANDARD,DST/@1,SHF/PASS.Z,W/SHF"
;1791	[] <-- [] LSH []		"FORMAT/STANDARD,LIT/BREG,VAL/@3,DST/@1,A/@2,SHF/LEFT.SINGLE,W/SHF"
;1792	[] <-- [] LSH (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,DST/@1,A/@2,SHF/LEFT.SINGLE,W/SHF"
;1793	[] <-- ZEXT [] RSH []		"FORMAT/STANDARD,LIT/BREG,VAL/@3,DST/@1,B/@2,SHF/RIGHT.SINGLE,W/SHF"
;1794	[] <-- ZEXT [] RSH (SC) 	"FORMAT/STANDARD,LIT/BREG,VAL/0,DST/@1,B/@2,SHF/RIGHT.SINGLE,W/SHF"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   60
;     MACRO.MIC 	     SHIFT Macros									      /REV=
;
;1795
;1796	;	Shift macros, continued.
;1797
;1798	;	Shift macros with register operands that drive the shift latch.
;1799
;1800	Q <-- [] LROT []		"FORMAT/STANDARD,LIT/BREG,VAL/@2,B/@1,A/@1,SHF/LEFT.DOUBLE,Q/UPDATE.Q"
;1801	Q <-- [] LROT (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@1,A/@1,SHF/LEFT.DOUBLE,Q/UPDATE.Q"
;1802	Q <-- [] RROT []		"FORMAT/STANDARD,LIT/BREG,VAL/@2,B/@1,A/@1,SHF/RIGHT.DOUBLE,Q/UPDATE.Q"
;1803	Q <-- [] RROT (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@1,A/@1,SHF/RIGHT.DOUBLE,Q/UPDATE.Q"
;1804	Q <-- []!![] LSH []		"FORMAT/STANDARD,LIT/BREG,VAL/@3,B/@2,A/@1,SHF/LEFT.DOUBLE,Q/UPDATE.Q"
;1805	Q <-- []!![] LSH (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@2,A/@1,SHF/LEFT.DOUBLE,Q/UPDATE.Q"
;1806	Q <-- []!![] RSH []		"FORMAT/STANDARD,LIT/BREG,VAL/@3,B/@2,A/@1,SHF/RIGHT.DOUBLE,Q/UPDATE.Q"
;1807	Q <-- []!![] RSH (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@2,A/@1,SHF/RIGHT.DOUBLE,Q/UPDATE.Q"
;1808	Q <-- []!![] RSH (32-SC)	"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@2,A/@1,SHF/LEFT.DOUBLE,Q/UPDATE.Q"
;1809	Q <-- SEXT [] RSH []		"FORMAT/STANDARD,LIT/BREG,VAL/@2,B/@1,A/SHIFT.SIGN,SHF/RIGHT.DOUBLE,Q/UPDATE.Q"
;1810	Q <-- SEXT [] RSH (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@1,A/SHIFT.SIGN,SHF/RIGHT.DOUBLE,Q/UPDATE.Q"
;1811	Q <-- SEXT [] RSH (32-SC)	"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@1,A/SHIFT.SIGN,SHF/LEFT.DOUBLE,Q/UPDATE.Q"
;1812
;1813	Q <-- PASSA []			"FORMAT/STANDARD,A/@1,SHF/PASS.A,Q/UPDATE.Q"
;1814	Q <-- PASSB []			"FORMAT/STANDARD,LIT/BREG,B/@1,SHF/PASS.B,Q/UPDATE.Q"
;1815	Q <-- 0 			"FORMAT/STANDARD,SHF/PASS.Z,Q/UPDATE.Q"
;1816	Q <-- [] LSH [] 		"FORMAT/STANDARD,LIT/BREG,VAL/@2,A/@1,SHF/LEFT.SINGLE,Q/UPDATE.Q"
;1817	Q <-- [] LSH (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,A/@1,SHF/LEFT.SINGLE,Q/UPDATE.Q"
;1818	Q <-- ZEXT [] RSH []		"FORMAT/STANDARD,LIT/BREG,VAL/@2,B/@1,SHF/RIGHT.SINGLE,Q/UPDATE.Q"
;1819	Q <-- ZEXT [] RSH (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@1,SHF/RIGHT.SINGLE,Q/UPDATE.Q"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   61
;     MACRO.MIC 	     SHIFT Macros									      /REV=
;
;1820
;1821	;	Shift macros, continued.
;1822
;1823	;	Shift macros with constant operand that drive the Wbus.
;1824
;1825	[] <-- PASSB K10.[]		"FORMAT/STANDARD,LIT/LIT,MISC/CONST.10.BIT,DST/@1,CONST.10/@2,SHF/PASS.B,W/SHF"
;1826	[] <-- PASSB 000000[]		"FORMAT/STANDARD,LIT/LIT,POS/BYTE0,DST/@1,CONST/@2,SHF/PASS.B,W/SHF"
;1827	[] <-- PASSB 0000[]00		"FORMAT/STANDARD,LIT/LIT,POS/BYTE1,DST/@1,CONST/@2,SHF/PASS.B,W/SHF"
;1828	[] <-- PASSB 00[]0000		"FORMAT/STANDARD,LIT/LIT,POS/BYTE2,DST/@1,CONST/@2,SHF/PASS.B,W/SHF"
;1829	[] <-- PASSB []000000		"FORMAT/STANDARD,LIT/LIT,POS/BYTE3,DST/@1,CONST/@2,SHF/PASS.B,W/SHF"
;1830
;1831	;	Shift macros with constant operand that drive the shift latch.
;1832
;1833	Q <-- PASSB K10.[]		"FORMAT/STANDARD,LIT/LIT,MISC/CONST.10.BIT,CONST.10/@1,SHF/PASS.B,Q/UPDATE.Q"
;1834	Q <-- PASSB 000000[]		"FORMAT/STANDARD,LIT/LIT,POS/BYTE0,CONST/@1,SHF/PASS.B,Q/UPDATE.Q"
;1835	Q <-- PASSB 0000[]00		"FORMAT/STANDARD,LIT/LIT,POS/BYTE1,CONST/@1,SHF/PASS.B,Q/UPDATE.Q"
;1836	Q <-- PASSB 00[]0000		"FORMAT/STANDARD,LIT/LIT,POS/BYTE2,CONST/@1,SHF/PASS.B,Q/UPDATE.Q"
;1837	Q <-- PASSB []000000		"FORMAT/STANDARD,LIT/LIT,POS/BYTE3,CONST/@1,SHF/PASS.B,Q/UPDATE.Q"
;1838
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   62
;     MACRO.MIC 	     SHIFT Macros									      /REV=
;
;1839
;1840	;	Shift macros, continued.
;1841
;1842	;	Shift macros with register operands with no destination.
;1843
;1844	NODST <-- [] LROT []		"FORMAT/STANDARD,LIT/BREG,VAL/@2,B/@1,A/@1,SHF/LEFT.DOUBLE"
;1845	NODST <-- [] LROT (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@1,A/@1,SHF/LEFT.DOUBLE"
;1846	NODST <-- [] RROT []		"FORMAT/STANDARD,LIT/BREG,VAL/@2,B/@1,A/@1,SHF/RIGHT.DOUBLE"
;1847	NODST <-- [] RROT (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@1,A/@1,SHF/RIGHT.DOUBLE"
;1848	NODST <-- []!![] LSH [] 	"FORMAT/STANDARD,LIT/BREG,VAL/@3,B/@2,A/@1,SHF/LEFT.DOUBLE"
;1849	NODST <-- []!![] LSH (SC)	"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@2,A/@1,SHF/LEFT.DOUBLE"
;1850	NODST <-- []!![] RSH [] 	"FORMAT/STANDARD,LIT/BREG,VAL/@3,B/@2,A/@1,SHF/RIGHT.DOUBLE"
;1851	NODST <-- []!![] RSH (SC)	"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@2,A/@1,SHF/RIGHT.DOUBLE"
;1852	NODST <-- []!![] RSH (32-SC)	"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@2,A/@1,SHF/LEFT.DOUBLE"
;1853	NODST <-- SEXT [] RSH []	"FORMAT/STANDARD,LIT/BREG,VAL/@2,B/@1,A/SHIFT.SIGN,SHF/RIGHT.DOUBLE"
;1854	NODST <-- SEXT [] RSH (SC)	"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@1,A/SHIFT.SIGN,SHF/RIGHT.DOUBLE"
;1855	NODST <-- SEXT [] RSH (32-SC)	"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@1,A/SHIFT.SIGN,SHF/LEFT.DOUBLE"
;1856
;1857	NODST <-- PASSA []		"FORMAT/STANDARD,A/@1,SHF/PASS.A"
;1858	NODST <-- PASSB []		"FORMAT/STANDARD,LIT/BREG,B/@1,SHF/PASS.B"
;1859	NODST <-- 0			"FORMAT/STANDARD,SHF/PASS.Z"
;1860	NODST <-- [] LSH []		"FORMAT/STANDARD,LIT/BREG,VAL/@2,A/@1,SHF/LEFT.SINGLE"
;1861	NODST <-- [] LSH (SC)		"FORMAT/STANDARD,LIT/BREG,VAL/0,A/@1,SHF/LEFT.SINGLE"
;1862	NODST <-- ZEXT [] RSH []	"FORMAT/STANDARD,LIT/BREG,VAL/@2,B/@1,SHF/RIGHT.SINGLE"
;1863	NODST <-- ZEXT [] RSH (SC)	"FORMAT/STANDARD,LIT/BREG,VAL/0,B/@1,SHF/RIGHT.SINGLE"
;1864
;1865	;	Shift macros with constant operand with no destination.
;1866
;1867	NODST <-- PASSB K10.[]		"FORMAT/STANDARD,LIT/LIT,MISC/CONST.10.BIT,CONST.10/@1,SHF/PASS.B"
;1868	NODST <-- PASSB 000000[]	"FORMAT/STANDARD,LIT/LIT,POS/BYTE0,CONST/@1,SHF/PASS.B"
;1869	NODST <-- PASSB 0000[]00	"FORMAT/STANDARD,LIT/LIT,POS/BYTE1,CONST/@1,SHF/PASS.B"
;1870	NODST <-- PASSB 00[]0000	"FORMAT/STANDARD,LIT/LIT,POS/BYTE2,CONST/@1,SHF/PASS.B"
;1871	NODST <-- PASSB []000000	"FORMAT/STANDARD,LIT/LIT,POS/BYTE3,CONST/@1,SHF/PASS.B"
;1872
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   63
;     MACRO.MIC 	     SPECIAL Macros									      /REV=
;
;1873	.TOC	"	SPECIAL Macros"
;1874
;1875	FBOX OPERAND A[]		"FORMAT/SPECIAL,MISC1/FOP.VALID,DST/NONE,A/@1"
;1876	FBOX OPERAND A[] B[]		"FORMAT/SPECIAL,MISC1/FOP.VALID,DST/NONE,A/@1,LIT/BREG,B/@2"
;1877
;1878	RETIRE INSTRUCTION		"FORMAT/SPECIAL,MISC1/RETIRE.INSTRUCTION"
;1879	FLUSH VIC			"FORMAT/SPECIAL,MISC1/FLUSH.VIC"
;1880	FLUSH BRANCH PREDICTION TABLE	"FORMAT/SPECIAL,MISC1/FLUSH.BPC"
;1881	FLUSH PC QUEUE			"FORMAT/SPECIAL,MISC1/FLUSH.PCQ"
;1882
;1883	STATE.5-4 <-- 0 		"FORMAT/SPECIAL,MISC1/CLR.STATE.5-4"
;1884	STATE.3 <-- 1			"FORMAT/SPECIAL,MISC1/SET.STATE.3"
;1885	STATE.4 <-- 1			"FORMAT/SPECIAL,MISC1/SET.STATE.4"
;1886	STATE.5 <-- 1			"FORMAT/SPECIAL,MISC1/SET.STATE.5"
;1887
;1888	FBOX DEST CHECK 		"FORMAT/SPECIAL,LIT/BREG,MISC2/F.DEST.CHECK"
;1889	FLUSH PA QUEUE			"FORMAT/SPECIAL,LIT/BREG,MISC2/FLUSH.PAQ"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   64
;     MACRO.MIC 	     Q, L, V Field Macros								      /REV=
;
;1890	.TOC	"	Q, L, V Field Macros"
;1891
;1892	Q&				"Q/UPDATE.Q"
;1893
;1894	LEN(DL) 			"L/LEN(DL)"
;1895	LONG				"L/LONG"
;1896
;1897	VA&				"V/UPDATE.VA"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   65
;     MACRO.MIC 	     MISC Field Macros									      /REV=
;
;1898	.TOC	"	MISC Field Macros"
;1899
;1900	DL <-- BYTE			"MISC/DL.BYTE"
;1901	DL <-- WORD			"MISC/DL.WORD"
;1902	DL <-- LONG			"MISC/DL.LONG"
;1903	RESTART IBOX			"MISC/RESTART.IBOX"
;1904	RESTART MBOX			"MISC/RESTART.MBOX"
;1905	RESET CPU			"MISC/RESET.CPU"
;1906	STATE.3-0 <-- 0 		"MISC/CLR.STATE.3-0"
;1907	STATE.0 <-- 1			"MISC/SET.STATE.0"
;1908	STATE.1 <-- 1			"MISC/SET.STATE.1"
;1909	STATE.2 <-- 1			"MISC/SET.STATE.2"
;1910	SC <-- A []			"MISC/LOAD.SC.FROM.A,A/@1"
;1911	MPU <-- B.29..16 []		"MISC/LOAD.MPU.FROM.B,LIT/BREG,B/@1"
;1912	MULL				"MISC/MULL"
;1913	SET PSL CC.IIIP 		"MISC/LOAD.PSL.CC.IIIP"
;1914	SET PSL CC.IIII 		"MISC/LOAD.PSL.CC.IIII"
;1915	SET PSL CC.JIZJ 		"MISC/LOAD.PSL.CC.JIZJ"
;1916	SET PSL CC.IIIJ 		"MISC/LOAD.PSL.CC.IIIJ"
;1917	SET PSL CC.IIIP.QUAD		"MISC/LOAD.PSL.CC.IIIP.QUAD"
;1918	SET PSL CC.PPJP 		"MISC/LOAD.PSL.CC.PPJP"
;1919	CLEAR PMF COUNTERS		"MISC/CLR.PERF.COUNT"
;1920	INCREMENT PMF COUNTER		"MISC/INCR.PERF.COUNT"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   66
;     MACRO.MIC 	     Microsequencer Control Macros							      /REV=
;
;1921	.TOC	"	Microsequencer Control Macros"
;1922
;1923	CALL CASE [] AT []		"SEQ.FMT/BRANCH,SEQ.CALL/CALL,SEQ.COND.1/<SEQ.COND/@1>,J/@2"
;1924	CASE [] AT []			"SEQ.FMT/BRANCH,SEQ.CALL/NOP,SEQ.COND.1/<SEQ.COND/@1>,J/@2"
;1925
;1926	RETURN				"SEQ.FMT/JUMP,SEQ.CALL/NOP,SEQ.MUX/STACK,J/0"
;1927
;1928	CALL [] 			"SEQ.FMT/JUMP,SEQ.CALL/CALL,SEQ.MUX/J,J/@1"
;1929	GOTO [] 			"SEQ.FMT/JUMP,SEQ.CALL/NOP,SEQ.MUX/J,J/@1"
;1930
;1931	LAST CYCLE			"SEQ.FMT/JUMP,SEQ.CALL/NOP,SEQ.MUX/LAST.CYCLE,J/0"
;1932	LAST CYCLE CHECK OVERFLOW	"SEQ.FMT/JUMP,SEQ.CALL/NOP,SEQ.MUX/LAST.CYCLE.OVERFLOW,J/0"
;1933	LAST CYCLE NO RETIRE		"FORMAT/SPECIAL,LIT/BREG,DISABLE.RETIRE/YES,SEQ.FMT/JUMP,SEQ.CALL/NOP,SEQ.MUX/LAST.CYCLE,J/0"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   67
;     MACRO.MIC 	     A/B Select Macros									      /REV=
;
;1934	.TOC	"	A/B Select Macros"
;1935
;1936	;	The A/B Select macros provide a way to explicitly specify an A or B port select.
;1937
;1938	ACCESS A []			"A/@1"
;1939	ACCESS B []			"LIT/BREG,B/@1"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   68
;     MACRO.MIC 	     Error Macros									      /REV=
;
;1940	.TOC	"	Error Macros"
;1941
;1942	;	These macros provide standard entries to microcode error routines.
;1943
;1944	CONSOLE HALT [] 		"[SAVEPSL] <-- [PSL] OR 0000[@1]00,LONG,GOTO [IE.CONSOLE.HALT..]"
;1945	CONSOLE HALT NO CLEANUP []	"[SAVEPSL] <-- [PSL] OR 0000[@1]00,LONG,GOTO [IE.CONSOLE.HALT.NO.CLEANUP..]"
;1946	MACHINE CHECK []		"[SAVEPSL] <-- 00[@1]0000,LONG,GOTO [IE.MACHINE.CHECK..]"
;1947	RESERVED OPERAND FAULT		"GOTO [IE.RSVD.OPERAND..]"
;1948	RESERVED INSTRUCTION FAULT	"GOTO [RSVD.OPCODE..]"
;1949	RESERVED ADDRESSING MODE	"GOTO [IE.RSVD.ADDRESS..]"
;1950	INTERRUPT FAULT 		"GOTO [IE.INT.FAULT..]"
;1951	UNIMPLEMENTED MTPR REGISTER []	"[W2] <-- [@1] LSH [2.],LONG,GOTO [MTPR.IPR.NORMAL]"
;1952	UNIMPLEMENTED MFPR REGISTER []	"[W2] <-- [@1] LSH [2.],LONG,GOTO [MFPR.IPR.NORMAL]"
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   69
;     MACRO.MIC 	     Simulator Control Macros								      /REV=
;
;1953	.TOC	"	Simulator Control Macros"
;1954
;1955	;	These macros control simulator features that do not exist in the real hardware
;1956
;1957	;	Address selection macros.
;1958
;1959	sim addr []			"SIM.ADDR.SEL/ADDR,SIM.ADDR/@1"
;1960	sim addr [] - k 		"SIM.ADDR.SEL/ADDR.K,SIM.ADDR/@1"
;1961	sim addr [] + k 		"SIM.ADDR.SEL/ADDR.K,SIM.ADDR/@1"
;1962
;1963	;	Microbranch condition selection macros.
;1964
;1965	sim cond k s3.[]		"SIM.COND.SEL/CONST,SIM.COND.S3.S4/S3,SIM.COND.K/@1"
;1966	sim cond k s4.[]		"SIM.COND.SEL/CONST,SIM.COND.S3.S4/S4,SIM.COND.K/@1"
;1967	sim cond []			"SIM.COND.SEL/FNC,SIM.COND/@1"
;1968
;1969	;	Simulator control macros.
;1970
;1971	sim halt			"MISC/SIM.HALT"
;1972	sim ie.intexc			"MISC/SIM.IE.INTEXC"
;1973	sim exception			"SIM.CTRL/CMD,SIM.CMD/EXCEPTION"
;1974	sim rsvd opcode 		"SIM.CTRL/CMD,SIM.CMD/RSVD.OPCODE"
;1975	sim emulate			"SIM.CTRL/CMD,SIM.CMD/EMULATE"
;1976	sim vector fault		"SIM.CTRL/CMD,SIM.CMD/VECTOR.FAULT"
				;1977	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   70
;     ALIGN.MIC 	     ALIGN.MIC -- Hardware Entry Point Assignments					      /REV=
;
				;1978	.TOC	"ALIGN.MIC -- Hardware Entry Point Assignments"
				;1979	.TOC	"Revision 1.0"
				;1980
				;1981	;	Mike Uhler, Bob Supnik
				;1982
;1983	.nobin
;1984	;****************************************************************************
;1985	;*									    *
;1986	;*  COPYRIGHT (c) 1988, 1989, 1990, 1991, 1992 BY			    *
;1987	;*  DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASSACHUSETTS.		    *
;1988	;*  ALL RIGHTS RESERVED.						    *
;1989	;*									    *
;1990	;*  THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED   *
;1991	;*  ONLY IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE   *
;1992	;*  INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE OR ANY  OTHER   *
;1993	;*  COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY   *
;1994	;*  OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE IS  HEREBY   *
;1995	;*  TRANSFERRED.							    *
;1996	;*									    *
;1997	;*  THE INFORMATION IN THIS SOFTWARE IS  SUBJECT TO CHANGE WITHOUT NOTICE   *
;1998	;*  AND  SHOULD  NOT  BE  CONSTRUED AS	A COMMITMENT BY DIGITAL EQUIPMENT   *
;1999	;*  CORPORATION.							    *
;2000	;*									    *
;2001	;*  DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE  OR  RELIABILITY OF ITS   *
;2002	;*  SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.		    *
;2003	;*									    *
;2004	;****************************************************************************
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   71
;     ALIGN.MIC 	     Revision History									      /REV=
;
;2005	.TOC	"	Revision History"
;2006
;2007	; Edit	  Date	 Who	     Description
;2008	; ---- --------- ---	---------------------
;2009	; (1)0 01-Aug-90 GMU	Initial production microcode.
;2010	;
;2011	; Begin version 1.0 here
;2012	;   16 31-JUL-90 GMU	Add constraints for NVAX+ vector entry points.
;2013	;   15 20-Jun-90 DGM	Fix FQ alignment constraints
;2014	;   14 26-Apr-90 GMU	Convert '*' fill constraints to 'x' constraints.
;2015	;   13 13-Mar-90 GMU	With the cancellation of SVS, remove the PROBEVMX..
;2016	;			entry point.
;2017	;   12 05-Mar-90 GMU	Duplicate individual field queue constraints to keep
;2018	;			ARCS from complaining about the use of the middle of
;2019	;			an ALIGNLIST as a branch target.
;2020	;   11 16-Jan-90 DGM	Change field queue alignments.
;2021	;   10 05-Jan-90 GMU	Remove vector issue microtrap constraint, collapse other
;2022	;			entry point addresses.
;2023	;    9 06-Dec-89 GMU	Continue comment update.
;2024	;    8 30-Nov-89 GMU	Combine ADWC, SBWC entry points, move EDIV.
;2025	;    7 28-Nov-89 GMU	Update microtrap addresses to reflect new hardware priority.
;2026	;    6 27-Sep-89 DGM	Modify alignment constraints on EDIV.  (remove .R & .M)
;2027	;    5 17-Aug-89 GMU	Update to reflect new field queue entry points.
;2028	;    4 24-Jul-89 GMU	Add new exception entry points.
;2029	;    3 07-Dec-88 DB	Redo floating point entry points, add FBOX.4.SL.ND..
;2030	;    2 06-Dec-88 DB	Redo floating point entry points
;2031	;    1 22-Nov-88 DB	Add new floating point entry points
;2032	; (0)0 16-Feb-88 RMS	Trial microcode.
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   72
;     ALIGN.MIC 	     Revision History									      /REV=
;
;2033
;2034	;				ALLOCATION NOTE
;2035	;
;2036	;	Unlike previous instances of microcode allocators, the NVAX allocator
;2037	;	responds to four types of constraints:
;2038	;
;2039	;		0	Address bit is constrained to a 0.
;2040	;		1	Address bit is constrained to a 1.
;2041	;		*	Address bit is logically unconstrained,
;2042	;			but is forced to be constrained to a 1.
;2043	;		x	Address bit is unconstrained.
;2044	;
;2045	;	The addition of the 'x' constraint and the redefinition of the '*'
;2046	;	constraint was done to lessen the chance that the microcoder has
;2047	;	misanalyzed the constraint requirements by forcing the constraint
;2048	;	to a '1'.  Unfortunately, this causes congestion in addresses whose
;2049	;	lower address bits are a 1 to such an extent that the microcode
;2050	;	will not allocate entirely within the range 0..1599.  As such,
;2051	;	all ALIGNLISTs have been categorized into "safe" and "unsafe"
;2052	;	constraints.  "Safe" constraints are those that are judged to be
;2053	;	unlikely to be wrong (an opcode case is considered a "safe"
;2054	;	constraint).  "Unsafe" constraints are those where the logic is
;2055	;	complex enough that there is a non-zero chance that the constraint
;2056	;	could be wrong.  "Safe" constraints have been changed from '*'
;2057	;	constraints to 'x' constraints, while "unsafe" constraints remain
;2058	;	'*' constraints.
;2059
				;2060	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   73
;     ALIGN.MIC 	     Exception Dispatches								      /REV=
;
				;2061	.TOC	"	Exception Dispatches"
				;2062
				;2063	;	Exception dispatches are placed in page 0 of the
				;2064	;	Control Store, as follows:
				;2065	;
				;2066	;		 10  9	8  7  6  5  4  3  2  1	0
				;2067	;		+--+--+--+--+--+--+--+--+--+--+--+
				;2068	;		|0  0  0 |    dispatch	   |0  0 |
				;2069	;		+--+--+--+--+--+--+--+--+--+--+--+
				;2070	;
				;2071	;	where
				;2072	;
				;2073	;		dispatch =	dispatch address from the trap hardware
				;2074	;
				;2075	;	Note: The following entry points are spaced 4 locations apart to
				;2076	;	allow more than one CALL at each entry point.  Entry points starting
				;2077	;	with IE.CONSOLE.HALT.. are not constrained by hardware requirement,
				;2078	;	but are constrained such that exception handler addresses are
				;2079	;	constant for all microcode assemblies.
				;2080
				;2081	;= AT 0
				;2082	;= ALIGNLIST 00000xx	(
				;2083	;= IE.POWERUP..,	IE.ASYNC.HW.ERROR..,
				;2084	;= IE.INT.OVERFLOW..,	IE.BRANCH..,
				;2085	;= IE.RSVD.OPCODE.TRAP..,IE.SYNC.HW.ERROR..,
				;2086	;= IE.MEMMGT.., 	IE.RSVD.ADDRESS..,
				;2087	;= IE.FLT.FAULT..,	IE.INT..,
				;2088	;= IE.TRACE.TRAP..,	IE.FPD..,
				;2089	;= IE.STALL..,		IE.CONSOLE.HALT..,
				;2090	;= IE.MACHINE.CHECK..,	IE.RSVD.OPERAND..,
				;2091	;= IE.INT.FAULT..,	IE.SUBSCRIPT.ERROR..,
				;2092	;= IE.DIVIDE.ERROR..,		 )
				;2093
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   74
;     ALIGN.MIC 	     Instruction Dispatches								      /REV=
;
				;2094	.TOC	"	Instruction Dispatches"
				;2095
				;2096	;	Instruction dispatches are placed in pages 1, 2, and 3 of the
				;2097	;	Control Store, as follows:
				;2098	;
				;2099	;		 10  9	8  7  6  5  4  3  2  1	0
				;2100	;		+--+--+--+--+--+--+--+--+--+--+--+
				;2101	;		|  page  |	 dispatch     |0 |
				;2102	;		+--+--+--+--+--+--+--+--+--+--+--+
				;2103	;
				;2104	;	where
				;2105	;
				;2106	;		page	=	001: instructions with no first cycle constraints
				;2107	;			=	010: instructions with mild first cycle constraints
				;2108	;			=	011: MxPR
				;2109	;		dispatch =	dispatch address from the IPLA
				;2110	;
				;2111	;	Note: The following entry points are spaced 2 locations apart to
				;2112	;	allow a CALL at each entry point.  Changes to these entry points
				;2113	;	require a reassembly of the IROM.
				;2114	;
				;2115	;	Page 1 - instructions with no first cycle constraints.
				;2116
				;2117	;= AT 100
				;2118	;= ALIGNLIST 000000x	(
				;2119	;= RSVD.OPCODE..,TSTX..,	BITX.., 	CMPI..,
				;2120	;= MOVX..,	MOVQ.., 	CLRX.., 	CLRQ..,
				;2121	;= MOVZBX..,	MOVZWL..,	MCOMX..,	MNEGX..,
				;2122	;= ADDIN..,	SUBIN..,	ADWC.SBWC..,		,
				;2123	;= INCX..,	DECX.., 		,		,
				;2124	;= BISXN..,	BICXN..,	XORXN..,		,
				;2125	;= CVTBI..,	CVTWL..,	CVTLW..,	CVTXB..,
				;2126	;= ROTL..,	ASHL.., 	ASHQ.., 		,
				;2127	;= SOBGXX..,	AOBLXX..,		,		,
				;2128	;= ACBB..,	ACBW.., 	ACBL.., 		,
				;2129	;= BSBX..,	JSB..,		RSB..,		CASEX..,
				;2130	;= BRX..,	BXX..,		BLBX.., 	JMP..,
				;2131	;= MULBN..,	MULWN..,	MULLN..,	EMUL..,
				;2132	;= DIVBN..,	DIVWN..,	DIVLN..,	EDIV..,
				;2133	;= CALLX..,	RET..,			,		,
				;2134	;=	,		,		,		)
				;2135
				;2136	;= AT 180
				;2137	;= ALIGNLIST 000000x	(
				;2138	;= NOP..,	HALT.., 	BPT..,		XFC..,
				;2139	;= INDEX..,	MOVPSL..,	PUSHR..,	POPR..,
				;2140	;= INSQUE..,	REMQUE..,	INSQXI..,		,
				;2141	;= REI..,		,		,		,
				;2142	;= LOCC.SKPC.., SCANC.SPANC..,		,		,
				;2143	;= FBOX.1.SL.., FBOX.2.SL..,	FBOX.4.SL..,		,
				;2144	;= FBOX.1.SL.ND..,FBOX.2.SL.ND..,FBOX.4.SL.ND..,	,
				;2145	;= EMULATE.4.., EMULATE.5..,	EMULATE.6..,		,
				;2146	;= VLDX..,		,	VSTX.., 		,
				;2147	;= VGATHX..,		,	VSCATX..,		,
				;2148	;= MFVP..,		,	MTVP.., 		,
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   75
;     ALIGN.MIC 	     Instruction Dispatches								      /REV=
;
				;2149	;= VSYNC..,		,	IOTA.., 		,
				;2150	;= VVOPX..,		,	VVCMPX..,		,
				;2151	;= VSOPL..,		,	VSCMPL..,		,
				;2152	;= VSOPQ..,		,	VSCMPQ..,		,
				;2153	;=	,		,		,		)
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   76
;     ALIGN.MIC 	     Instruction Dispatches								      /REV=
;
				;2154
				;2155	;	Page 2 - instructions with mild first cycle constraints.
				;2156
				;2157	;	The alignments for CVTPL.., BBX.., BBXS.., BBXC..,
				;2158	;	REMQXI.., ADAWI.., FIELD.., and INSV.. reflect the restrictions
				;2159	;	imposed by the field queue case constraints.  These alignments
				;2160	;	must not be changed relative to the coresponding .M and .R
				;2161	;	labels.
				;2162
				;2163	;= AT 200
				;2164	;= ALIGNLIST 000000x	(
				;2165	;= BIXPSW..,	MOVCX..,	CMPCX..,		,
				;2166	;= LDPCTX..,	SVPCTX..,	PROBEX..,		,
				;2167	;= CHMK..,	CHME.., 	CHMS.., 	CHMU..,
				;2168	;=	,		,		,		,
				;2169	;=	,		,		,		,
				;2170	;=	,		,		,		,
				;2171	;=	,		,		,		,
				;2172	;=	,		,		,		)
				;2173
				;2174	;	The following ALIGNLISTS must be separate from the above ALIGNLIST
				;2175	;	because the microcode analyzer ARCS does not like to see case targets
				;2176	;	in the middle of an ALIGNLIST nor as the beginning of a large
				;2177	;	ALIGNLIST.  Logically, this group of ALIGNLISTs belongs at the
				;2178	;	end of the large ALIGNLIST above.
				;2179
				;2180	;= AT 240
				;2181	;= ALIGNLIST 00x (ADAWI.M,	ADAWI.R,		,	ADAWI..,)
				;2182	;= AT 248
				;2183	;= ALIGNLIST 00x (BBX.M,	BBX.R,			,	BBX..)
				;2184	;= AT 250
				;2185	;= ALIGNLIST 00x (BBXS.M,	BBXS.R, 		,	BBXS..)
				;2186	;= AT 258
				;2187	;= ALIGNLIST 00x (BBXC.M,	BBXC.R, 		,	BBXC..)
				;2188	;= AT 260
				;2189	;= ALIGNLIST 00x (FIELD.M,	FIELD.R,		,	FIELD..)
				;2190	;= AT 268
				;2191	;= ALIGNLIST 00x (INSV.M,	INSV.R, 		,	INSV..)
				;2192	;= AT 270
				;2193	;= ALIGNLIST 00x (REMQXI.M,	REMQXI.R,		,	REMQXI..)
				;2194	;= AT 278
				;2195	;= ALIGNLIST 00x (EMULATE.3.CVTPL.M..,	CVTPL.R,	,	CVTPL..)
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   77
;     ALIGN.MIC 	     Instruction Dispatches								      /REV=
;
				;2196
				;2197	;	Page 3 - MxPR.
				;2198
				;2199	;= AT 300
				;2200	;= ALIGNLIST 0x (MTPR..,	MFPR..)
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   78
;   POWERUP.MIC 	     POWERUP.MIC -- Powerup Initialization						      /REV=
;
				;2201	.TOC	"POWERUP.MIC -- Powerup Initialization"
				;2202	.TOC	"Revision 1.5"
				;2203
				;2204	;	Mike Uhler, Bob Supnik, John Brown
				;2205
;2206	.nobin
;2207	;****************************************************************************
;2208	;*									    *
;2209	;*  COPYRIGHT (c) 1987, 1988, 1989, 1990, 1991, 1992 BY 		    *
;2210	;*  DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASSACHUSETTS.		    *
;2211	;*  ALL RIGHTS RESERVED.						    *
;2212	;*									    *
;2213	;*  THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED   *
;2214	;*  ONLY IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE   *
;2215	;*  INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE OR ANY  OTHER   *
;2216	;*  COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY   *
;2217	;*  OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE IS  HEREBY   *
;2218	;*  TRANSFERRED.							    *
;2219	;*									    *
;2220	;*  THE INFORMATION IN THIS SOFTWARE IS  SUBJECT TO CHANGE WITHOUT NOTICE   *
;2221	;*  AND  SHOULD  NOT  BE  CONSTRUED AS	A COMMITMENT BY DIGITAL EQUIPMENT   *
;2222	;*  CORPORATION.							    *
;2223	;*									    *
;2224	;*  DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE  OR  RELIABILITY OF ITS   *
;2225	;*  SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.		    *
;2226	;*									    *
;2227	;****************************************************************************
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   79
;   POWERUP.MIC 	     Revision History									      /REV=
;
;2228	.TOC	"	Revision History"
;2229
;2230	; Edit	  Date	 Who	     Description
;2231	; ---- --------- ---	---------------------
;2232	;    5 09-Jan-92 JFB	Symptom: additional microword for edit 4 causes
;2233	;				 undesired reallocation for the mini-pass.
;2234	;			Cure:	 change order and tie down the single instruction
;2235	;				 that clears the PCSTS lock bit.
;2236	;    4 24-Jul-91 JFB	Symptom: In the burnin flow, the Pcache is enabled
;2237	;				 without clearing the lock bit in the PCSTS.
;2238	;				 This disables the Pcache regardless of the
;2239	;				 state of PCCTL.
;2240	;			Cure:	 Write a 1 to PCSTS to clear the lock bit
;2241	;				 before enabling the Pcache via PCCTL.
;2242	;    3 14-Jun-91 GMU	Symptom: When MAPEN is cleared in the console halt
;2243	;				 flow, the VIC can still have valid data
;2244	;				 corresponding to virtual addresses that
;2245	;				 matched the physical addresses in which
;2246	;				 the console is running (with the S1 space
;2247	;				 ECO, E0040000 is a valid S0 space virtual
;2248	;				 address).  This could cause the CPU to
;2249	;				 start executing bogus instructions rather
;2250	;				 than the console code.
;2251	;			Cure:	 Flush the VIC after turning off MAPEN in
;2252	;				 the console halt flow and before restarting
;2253	;				 prefetch.
;2254	;    2 20-May-91 GMU	Symptom: Certain console halts may be invoked from
;2255	;				 flows in which a RESET CPU and call to
;2256	;				 IE.CLEANUP.CPU have been performed.  If
;2257	;				 this call packs up the state for a string
;2258	;				 instruction, a second RESET CPU and call
;2259	;				 to IE.CLEANUP leaves SAVEPSL with FPD
;2260	;				 set and SAVEPC pointing at the instruction
;2261	;				 following the string instruction rather than
;2262	;				 at the string instruction.
;2263	;			Cure:	 Add an alternate console halt entry point,
;2264	;				 IE.CONSOLE.HALT.NO.CLEANUP.., to be reached
;2265	;				 using the CONSOLE HALT NO CLEANUP macro.
;2266	;				 Entry at this label causes the RESET CPU
;2267	;				 and call to IE.CLEANPU.CPU to be avoiding,
;2268	;				 leaving SAVEPC correct.
;2269	;    1 06-Aug-90 JFB	For safety, remove a special microinstruction from the
;2270	;			console.burn.in code that uses the Q register.
;2271	; (1)0 31-Jul-90 GMU	Initial production microcode.
;2272	;
;2273	; Begin version 1.0 here
;2274	;   20 31-Jul-90 JFB	Split out powerup flow for burn-in Pcache load path.
;2275	;   19 25-Jul-90 GMU	Change initial BPCR value from FECA to ECC8.
;2276	;   18 04-Jul-90 GMU	Clear the performance monitoring facility counters at powerup.
;2277	;   17 01-May-90 GMU	Uncomment references to CWB IPR.
;2278	;   16 30-Apr-90 GMU	Sync with Mbox after LOAD PC.
;2279	;   15 26-Apr-90 GMU	Convert '*' fill constraints to 'x' constraints.
;2280	;   14 12-Feb-90 GMU	Account for 9-bit shift required when referencing
;2281	;			IPR.MMAPEN.
;2282	;   13 19-Jan-90 GMU	FLUSH BRANCH PREDICTION CACHE -> FLUSH BRANCH PREDICTION TABLE.
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   80
;   POWERUP.MIC 	     Revision History									      /REV=
;
;2283	;   12 09-Jan-90 GMU	Update INT.SYS initialization to reflect new interrupt
;2284	;			section design.
;2285	;   11 13-Dec-89 GMU	Add SYNCHRONIZE MBOX between Ibox BPCR write and LOAD PC
;2286	;			in halt flow to guarantee that the Ibox has processed
;2287	;			the IPR write before it sees the LOAD PC (which is another
;2288	;			IPR write from its point of view).
;2289	;   10 06-Dec-89 GMU	Continue comment update.
;2290	;    9 06-Dec-89 GMU	Add FLUSH BRANCH PREDICTION CACHE to console halt flow.
;2291	;    8 09-Nov-89 GMU	Revert to normal powerup start address at E0040000.
;2292	;    7 07-Nov-89 GMU	Complete RESET CPU interface.
;2293	;    6 30-Oct-89 GMU	Move REINITIALIZE.CPU routine to INTEXC.
;2294	;    5 26-Oct-89 DB	Move sim halt in IE.CONSOLE.HALT
;2295	;    4 09-Oct-89 GMU	Step on W1 rather than W0 in REINITIALIZE.CPU.
;2296	;    3 02-Aug-89 GMU	Add initialization of BPCR branch prediction history
;2297	;			algorithm.
;2298	;    2 19-Jul-89 GMU	Add one more cycle between RESET CPU and Mbox req.
;2299	;    1 10-Jul-89 GMU	Update to reflect current design.
;2300	; (0)0 18-Sep-87 RMS	Trial microcode.
;2301
				;2302	.bin
				;2303	;= BEGIN POWERUP
;2304	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   81
;   POWERUP.MIC 	     Powerup Initialization								      /REV=
;															    POWERUP
;2305	.TOC	"	Powerup Initialization"
;2306
;2307	;	This module contains the power up initialization code.
;2308
;2309	;	On chip reset (either power up or explicit reset), the hardware
;2310	;	and microcode conspire to initialize the CPU to a known state.
;2311	;	Hardware reset does the following:
;2312	;
;2313	;	      o The VIC, Pcache, and Bcache are disabled.
;2314	;	      o The RLOG is cleared.
;2315	;	      o The Fbox and vector unit are disabled.
;2316	;	      o The microstack is cleared.
;2317	;	      o The Mbox and Cbox are reset, and all previous operations are
;2318	;		flushed.
;2319	;	      o The Fbox is reset.
;2320	;	      o The Ibox is stopped, waiting for a LOAD PC.
;2321	;	      o All instruction and operand queues are flushed.
;2322	;	      o All MD valid bits are cleared, and all Wn valid bits are set.
;2323	;	      o A powerup microtrap is initiated which starts the Ebox at
;2324	;		the label IE.POWERUP..
;2325	;
;2326	;	Microcode at IE.POWERUP.. then does the following:
;2327	;
;2328	;	      o Hardware interrupt requests are cleared.
;2329	;	      o ICCS<6> is set to 0.
;2330	;	      o SISR<15:1> is set to 0.
;2331	;	      o ASTLVL is set to 4.
;2332	;	      o CPUID is set to 0.
;2333	;	      o The performance monitoring counters are cleared.
;2334	;	      o The Mbox is reset to 30-bit physical address mode.
;2335	;	      o The BPCR branch history algorithm is reset to the
;2336	;		default value.
;2337	;	      o A console halt is initiated with code ERR.PWRUP.
;2338	;	      o The performance monitoring facility counters are cleared.
;2339	;
;2340	;	The common console halt handler at IE.CONSOLE.HALT.. is used for
;2341	;	both power up halts and for all other halts initiated by the
;2342	;	microcode.  In addition, an alternate entry point IE.CONSOLE.HALT.NO.CLEANUP..
;2343	;	is provided for the exclusive use of those routines which
;2344	;	are known to have already done a RESET CPU/call to IE.CLEANUP.CPU
;2345	;	with the possibility of packing up state for a string instruction.
;2346	;
;2347	;	The console halt flow re-initializes the CPU and starts
;2348	;	execution in the boot ROM, by doing the following:
;2349
;2350	;	      o The Mbox and Cbox are reset, and all previous read operations
;2351	;		operations are flushed.
;2352	;	      o The Fbox is reset.
;2353	;	      o The Ibox is stopped, waiting for a LOAD PC.
;2354	;	      o All instruction and operand queues are flushed.
;2355	;	      o All MD valid bits are cleared, and all Wn valid bits are set.
;2356	;	      o The RLOG is unwound and backup PC is retrieved from the Ibox
;2357	;		and saved in the SAVPC processor register.
;2358	;	      o The current PSL, halt code, and value of MAPEN<0> are saved in
;2359	;		the SAVPSL processor register.
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   82
;   POWERUP.MIC 	     Powerup Initialization								      /REV=
;															    POWERUP
;2360	;	      o MAPEN is cleared (memory management is disabled).
;2361	;	      o SP is saved in the current mode stack pointer register.  ISP
;2362	;		is then loaded into SP.
;2363	;	      o All state flags are cleared.
;2364	;	      o PSL is loaded with 041F0000.
;2365	;	      o PC is loaded with E0040000.
;2366
;2367	;	The powerup microcode provides a means for the burn-in and life-test programs
;2368	;	to load the Pcache with asynchronous, bit-serial instruction stream data. If
;2369	;	p%test_strobe_h, which is normally held high by an on-chip pull-up, is held
;2370	;	low during this flow, control is diverted from normal power-up routine to the
;2371	;	burn-in flow. The burn-in flow loads the Pcache by doing the following:
;2372	;
;2373	;	      o Set force Pcache hit, enable I and D
;2374	;	      o VA = 0
;2375	;	      o Assert p%machine_check to signify start of burn-in flow.
;2376	;	loop: o Wait for p%test_strobe_h assertion.
;2377	;	      o Append value of p%test_data_h onto Istream data.
;2378	;	      o If Istream data = 32 bits, then write into Pcache, VA = VA + 4.
;2379	;	      o If Istream data = 32K bits, then go to exit:
;2380	;	      o Wait for p%test_strobe_h de-assertion.
;2381	;	      o Go to loop:
;2382	;	exit: o De-assert p%machine_check to signify end of burn-in flow.
;2383	;	      o Load PC at 00004000, last cycle.
;2384
				;2385	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   83
;   POWERUP.MIC 	     Powerup Entry Point								      /REV=
;															    POWERUP
				;2386	.TOC	"	Powerup Entry Point"
				;2387
				;2388	;	Power up sequence.
				;2389
				;2390	IE.POWERUP..:
				;2391		;********** Hardware dispatch **********;
				;2392		VA <-- [0EC]000000, LONG,		; start building default BP algorithm
E 000  0080,3F61,2007,0001 J 001;2393		CLEAR PMF COUNTERS			; clear both PMF counters
				;2394
				;2395	;= AT IE.POWERUP..+1				; to allow ucode to be reloaded in beh model
				;2396		;---------------------------------------;
E 001  0500,3640,04B0,004B J 04B;2397		[W0] <-- [VA] OR 00[0C8]0000, LONG	; complete BP algorithm
				;2398
				;2399		;---------------------------------------;
				;2400		VA <-- K10.[IPR.PAMODE],		; load VA with PA mode IPR address
				;2401		MEM.PR (VA)&, [WBUS] <-- PASSA [K0],	; force Mbox to 30-bit mode
				;2402		LONG,					;
E 04B  00F4,7CE3,2311,0063 J 063;2403			sim addr [k]
				;2404
				;2405
				;2406		;---------------------------------------;
				;2407		VA <-- K10.[IPR.BPCR],			; load VA with BPCR IPR address
				;2408		MEM.PR (VA)&, [WBUS] <-- PASSA [W0],	; Load new prediction algorithm
				;2409		LONG,					;
E 063  00F4,7A83,2011,006F J 06F;2410			sim addr [k]
				;2411
				;2412	;	Note: INT.SYS must be cleared at least three cycles after the PMF
				;2413	;	counters are cleared to guarantee that the interrupt request is
				;2414	;	actually cleared.
				;2415
				;2416		;---------------------------------------;
E 06F  0080,3FC8,C000,0073 J 073;2417		[INT.SYS] <-- [ISR.CLEAR.ALL]000000, LONG ; clear interrupt latches
				;2418							; >> int.sys change, no decode in next
				;2419							; >> 3 cycles
				;2420
				;2421		;---------------------------------------;
E 073  0080,3C00,9400,00B1 J 0B1;2422		[ASTLVL] <-- [80]000000, LONG		; set ASTLVL = 4 (in bits <31:29>),
				;2423							;     CPUID = 0 (in bits <7:0>)
				;2424
				;2425		;---------------------------------------;
				;2426		SYNCHRONIZE MBOX,			; synchronize Ibox IPR write with
			    p.84;2427							; subsequent LOAD PC
E 0B1  0520,2818,A4C0,0034 J 034;2428		CONSOLE HALT [ERR.PWRUP]		; power up, invoke console
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   84
;   POWERUP.MIC 	     Console Halt Entry Point								      /REV=
;															    POWERUP
				;2429	.TOC	"	Console Halt Entry Point"
				;2430
				;2431	;	Console halt entry point.
				;2432
				;2433	;	Control arrives here as the result of the CONSOLE HALT macro.
				;2434	;	The CPU is in an indeterminate state and must be reset before
				;2435	;	proceeding.
				;2436	;
				;2437	;	Note: The IE.CONSOLE.HALT.NO.CLEANUP.. entry point is used by
				;2438	;	the CONSOLE HALT NO CLEANUP macro to avoid a call to IE.CLEANUP.NO.PACKUP.
				;2439	;
				;2440	;	At this point,
				;2441	;		SAVEPSL<31:16,7:0> =	PSL<31:16,7:0>
				;2442	;		SAVEPSL<15:14>	=	0
				;2443	;		SAVEPSL<13:8>	=	console halt code (from CONSOLE HALT macro)
				;2444
				;2445	IE.CONSOLE.HALT..:
				;2446		;---------------------------------------;
				;2447		Q <-- 0,				; no PSL bits to clear
				;2448		RESET CPU,				; abort current operations
				;2449		CALL [IE.CLEANUP.CPU.NO.PACKUP],	; cleanup CPU state, state<3:0> = 0
				;2450							; PSL<TP> unchanged, SAVEPC = BPC
			    p159;2451							; >> Fbox sync via DST <> NONE
E 034  0002,C000,2006,22D5 S 2D5;2452			sim exception
				;2453
				;2454	IE.CONSOLE.HALT.NO.CLEANUP..:			; from CONSOLE HALT NO CLEANUP macro only
				;2455		;---------------------------------------;
				;2456		VA <-- K10.[IPR.MMAPEN],		; read memory management enable
				;2457		[W1] <-- MEM.PR (VA), LONG,		; into E-box
				;2458		FLUSH BRANCH PREDICTION TABLE,		; flush branch prediction table
E 035  10D5,3CC1,0801,00B3 J 0B3;2459			sim addr [k]
				;2460
				;2461		;---------------------------------------;
				;2462		MEM.PR (VA)&, [WBUS] <-- [W1] XOR [W1], ; clear memory management enable
				;2463		LONG,					; mapen<0> returns in W1<9>,
E 0B3  0677,4610,2020,00D2 J 0D2;2464		Q <-- [W1] LSH [6.]			; position mapen<0> to bit <15>
				;2465
				;2466
				;2467		;---------------------------------------;
				;2468		[SAVEPSL] <-- [SAVEPSL] OR [Q], LONG,	; include MAPEN<0> in SAVEPSL<15>
E 0D2  1500,C050,A690,00E3 J 0E3;2469		FLUSH VIC				; clear stale mappings from VIC
				;2470							; >> FLUSH VIC: LOAD PC required
				;2471
				;2472		;---------------------------------------;
				;2473		Q <-- PASSB [04]000000, LONG,		; start building new PSL
				;2474		[W0] <-- [K1],				; load W0 with 1 for burn-in flow
E 0E3  0002,B820,072F,80EB J 0EB;2475			sim halt
				;2476
			    p.85;2477		;---------------------------------------;
E 0EB  0500,30F8,30A0,0410 J 410;2478		[PSL] <-- [Q] OR 00[1F]0000, LONG	; new PSL = 041F0000
				;2479							; >> PSL change, no decode for 3 cycles
				;2480
				;2481		;---------------------------------------;
				;2482		VA <-- K10.[IPR.CWB],			; push writes out of the chip
				;2483		MEM.PR (VA)&, [WBUS] <-- PASSA [K0], LONG, ; during halt process
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   85
;   POWERUP.MIC 	     Console Halt Entry Point								      /REV=
;															    POWERUP
			    p.86;2484		CASE [PSL.26-24] AT [CONSOLE.PSL.000],	; case on current PSL<26:24>
E 410  A0F4,6883,2311,4D61 B 461;2485			sim addr [k]
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   86
;   POWERUP.MIC 	     Console Halt Entry Point								      /REV=
;															    POWERUP
				;2486
				;2487	;	Console halt, continued.
				;2488	;	PC, PSL, MAPEN saved, MAPEN off, new PSL set.
				;2489	;	Save current stack.
				;2490	;
				;2491	;	At this point,
				;2492	;		W0	=	1
				;2493
				;2494	;= ALIGNLIST 000x	(CONSOLE.PSL.000,	CONSOLE.PSL.001,
				;2495	;=			 CONSOLE.PSL.010,	CONSOLE.PSL.011,
				;2496	;=			 CONSOLE.PSL.100,	CONSOLE.PSL.101,
				;2497	;=			 CONSOLE.PSL.110,	CONSOLE.PSL.111)
				;2498
				;2499	CONSOLE.PSL.000:
				;2500		;---------------------------------------; psl<26:24> = 000:
				;2501		[KSP] <-- [SP], LONG,			; save SP in KSP
			    p.88;2502		STATE.5-4 <-- 0,			; clear all permanent state flags
E 461  1001,4000,81E0,0339 J 339;2503		GOTO [CONSOLE.LOAD.PC]			; go load ISP
				;2504
				;2505	CONSOLE.PSL.001:
				;2506		;---------------------------------------; psl<26:24> = 001:
				;2507		[ESP] <-- [SP], LONG,			; save SP in ESP
			    p.88;2508		STATE.5-4 <-- 0,			; clear all permanent state flags
E 463  1001,4000,85E0,0339 J 339;2509		GOTO [CONSOLE.LOAD.PC]			; go load ISP
				;2510
				;2511	CONSOLE.PSL.010:
				;2512		;---------------------------------------; psl<26:24> = 010:
				;2513		[SSP] <-- [SP], LONG,			; save SP in SSP
			    p.88;2514		STATE.5-4 <-- 0,			; clear all permanent state flags
E 465  1001,4000,89E0,0339 J 339;2515		GOTO [CONSOLE.LOAD.PC]			; go load ISP
				;2516
				;2517	CONSOLE.PSL.011:
				;2518		;---------------------------------------; psl<26:24> = 011:
				;2519		[USP] <-- [SP], LONG,			; save SP in USP
			    p.88;2520		STATE.5-4 <-- 0,			; clear all permanent state flags
E 467  1001,4000,8DE0,0339 J 339;2521		GOTO [CONSOLE.LOAD.PC]			; go load ISP
				;2522
				;2523	CONSOLE.PSL.100:
				;2524		;---------------------------------------; psl<26:24> = 100:
				;2525		[ISP] <-- [SP], LONG,			; save SP in ISP
			    p.88;2526		STATE.5-4 <-- 0,			; clear all permanent state flags
E 469  1001,4000,91E0,0339 J 339;2527		GOTO [CONSOLE.LOAD.PC]			; go load ISP
				;2528
				;2529	CONSOLE.PSL.101:
				;2530		;---------------------------------------; psl<26:24> = 101:
				;2531		[SAVEPSL] <-- [SAVEPSL] OR 0000[40]00,	; mark corrupted PSL, set SAVEPSL<14>
				;2532		LONG,					;
			    p.88;2533		STATE.5-4 <-- 0,			; clear all permanent state flags
E 46B  1501,6A00,A690,0339 J 339;2534		GOTO [CONSOLE.LOAD.PC]			; go load ISP
				;2535
				;2536	CONSOLE.PSL.110:
				;2537		;---------------------------------------; psl<26:24> = 110:
				;2538		[SAVEPSL] <-- [SAVEPSL] OR 0000[40]00,	; mark corrupted PSL, set SAVEPSL<14>
				;2539		LONG,					;
				;2540		STATE.5-4 <-- 0,			; clear all permanent state flags
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   87
;   POWERUP.MIC 	     Console Halt Entry Point								      /REV=
;			    p.88											    POWERUP
E 46D  1501,6A00,A690,0339 J 339;2541		GOTO [CONSOLE.LOAD.PC]			; go load ISP
				;2542
				;2543	CONSOLE.PSL.111:
				;2544		;---------------------------------------; psl<26:24> = 111:
				;2545		[SAVEPSL] <-- [SAVEPSL] OR 0000[40]00,	; mark corrupted PSL, set SAVEPSL<14>
				;2546		LONG,					;
			    p.88;2547		STATE.5-4 <-- 0,			; clear all permanent state flags
E 46F  1501,6A00,A690,0339 J 339;2548		GOTO [CONSOLE.LOAD.PC]			; go load ISP
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   88
;   POWERUP.MIC 	     Console Halt Entry Point								      /REV=
;															    POWERUP
				;2549
				;2550	;	Console halt, continued.
				;2551	;	PC, PSL, MAPEN saved, MAPEN off, new PSL set, current SP saved.
				;2552	;	Load new SP and PC, start machine.
				;2553	;
				;2554	;	At this point,
				;2555	;		W0	=	1
				;2556
				;2557	CONSOLE.LOAD.PC:
				;2558		;---------------------------------------;
				;2559		[SP] <-- [ISP], LONG,			; load ISP into SP
			    p.89;2560		Q <-- PASSB [0E0]000000,		; start building powerup address<31:24>
E 339  0002,BF00,7A40,50ED B 3ED;2561		CASE [TEST.PINS] AT [CONSOLE.BURN.IN]	; split here for burn-in flow
				;2562
				;2563	;= ALIGNLIST 110x	(CONSOLE.BURN.IN,	CONSOLE.LOAD.PC.CONT)
				;2564
				;2565	;	Here from above, or on completion of the burn-in flow, to start execution.
				;2566	;
				;2567	;	At this point,
				;2568	;		Q	=	base of boot address
				;2569
				;2570	CONSOLE.LOAD.PC.CONT:
				;2571		;---------------------------------------; alu.z = 1 or strobe = 1::
				;2572		[WBUS] <-- [Q] OR 00[04]0000, LONG,	; normal powerup address = E004000
				;2573		LOAD PC,				; burn-in powerup address = 0004000
				;2574							; load new PC, start prefetching
				;2575							; >> LOAD PC: sync required before exit
			    p144;2576		STATE.5-4 <-- 0,			; clear permanent flags again for burn-in exit
E 3EF  1525,7020,20A0,0271 J 271;2577		GOTO [SYNC.RESTART.IBOX.NO.RETIRE]	; restart Ibox and decode next instruction
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   89
;   POWERUP.MIC 	     Console Halt Entry Point								      /REV=
;															    POWERUP
				;2578
				;2579	;	Burn-in power-up flow.
				;2580	;	PC, PSL, MAPEN saved, MAPEN off, new PSL set, current SP saved, new SP loaded.
				;2581	;
				;2582	;	At this point,
				;2583	;		W0	=	1 (bit counter)
				;2584
				;2585	CONSOLE.BURN.IN:
				;2586		;---------------------------------------; strobe = 0:
				;2587		[W1] <-- 000000[PCCTL.FORCE.HIT],	; data for Pcache control:
				;2588							; force hit+I enable+D enable
E 3ED  1082,2038,0800,05D2 J 5D2;2589		STATE.5 <-- 1				; set MCHK pin at start of burn-in flow.
				;2590
				;2591	;= AT 5D2
				;2592		;---------------------------------------; write Pcache status register to
				;2593		VA <-- K10.[IPR.PCSTS], LONG,		;   clear lock bit.
E 5D2  00F4,7E83,2321,0181 J 181;2594		MEM.PR (VA)&, [WBUS] <-- PASSA [K1]	;
				;2595
				;2596		;---------------------------------------; write Pcache control register.
				;2597		VA <-- K10.[IPR.PCCTL], LONG,		; left bank enabled, parity check disabled
E 181  00F4,7F03,2021,0343 J 343;2598		MEM.PR (VA)&, [WBUS] <-- PASSA [W1]
				;2599
				;2600		;---------------------------------------;
				;2601		VA&, [WBUS] <-- [K0],			; starting pcache load address = 0.
				;2602		Q <-- 0,				; Q holds the start of the boot address
E 343  0002,C001,2310,50E8 B 3E8;2603		CASE [TEST.PINS] AT [CONSOLE.DATA.0.STROBE.0] ; wait for first test_strobe assertion.
				;2604
				;2605	;= ALIGNLIST 100x	(CONSOLE.DATA.0.STROBE.0, CONSOLE.DATA.0.STROBE.1,
				;2606	;=			 CONSOLE.DATA.1.STROBE.0, CONSOLE.DATA.1.STROBE.1)
				;2607
				;2608	; Pin timing on p%test_strobe_h and p%test_data_h must guarrantee
				;2609	; that there are two cases at this point on each pass through the flow.
				;2610
				;2611	CONSOLE.DATA.0.STROBE.0:
				;2612		;---------------------------------------; data = 0, strobe = 0:
				;2613		[WBUS] <-- [W0] AND 000000[1F], LONG,	; [L1W] test bit count, alu.z=1 if 32
				;2614							;	bits accumulated
E 3E8  0400,20F8,2010,50E8 B 3E8;2615		CASE [TEST.PINS] AT [CONSOLE.DATA.0.STROBE.0] ; wait for strobe assertion
				;2616
				;2617	CONSOLE.DATA.1.STROBE.0:
				;2618		;---------------------------------------; data = 1, strobe = 0:
				;2619		[WBUS] <-- [W0] AND 000000[1F], LONG,	; [L1W] test bit count, alu.z=1 if 32
				;2620							;	bits accumulated
E 3EC  0400,20F8,2010,50E8 B 3E8;2621		CASE [TEST.PINS] AT [CONSOLE.DATA.0.STROBE.0] ; wait for strobe assertion
				;2622
				;2623	CONSOLE.DATA.0.STROBE.1:
				;2624		;---------------------------------------; data = 0, strobe = 1:
			    p.90;2625		[W1] <-- [K0]!![W1] RSH [1], LONG,	; [L1D] shift in a 1 bit
E 3EA  0001,8112,0B10,0341 J 341;2626		GOTO [CONSOLE.DATA.MERGE]		; merge with common code
				;2627
				;2628	CONSOLE.DATA.1.STROBE.1:
				;2629		;---------------------------------------; data = 1, strobe = 1:
			    p.90;2630		[W1] <-- [K1]!![W1] RSH [1], LONG,	; [L1D] shift in a 0 bit
E 3EE  0001,8112,0B20,0341 J 341;2631		GOTO [CONSOLE.DATA.MERGE]		; merge with common code
				;2632
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   90
;   POWERUP.MIC 	     Console Halt Entry Point								      /REV=
;															    POWERUP
				;2633	CONSOLE.DATA.MERGE:
				;2634		;---------------------------------------;
				;2635		[WBUS] <-- [W0] ANDNOT 0000[80]00, LONG, ; [L2] test bit count, alu.z=1 if
			    p.91;2636							; 32K bits accumulated
E 341  2480,2C00,2010,41FA B 3FA;2637		CASE [ALU.NZV] AT [CONSOLE.GET.NEXT.BIT] ; case on full longword from [L1W]
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   91
;   POWERUP.MIC 	     Console Halt Entry Point								      /REV=
;															    POWERUP
				;2638
				;2639	;	Burn-in power-up flow.
				;2640	;	test_data has been strobed and added to current longword.
				;2641	;
				;2642	;	At this point:
				;2643	;		W0	=	running bit count
				;2644	;		VA	=	Pcache address
				;2645	;		Q	=	0 (boot address)
				;2646	;		W1	=	32 bits of accumulated data
				;2647	;		alu.z	=	1 if 32K bits accumulated (valid in cycle L4)
				;2648	;
				;2649	;= ALIGNLIST *0*x	(CONSOLE.GET.NEXT.BIT,	CONSOLE.WRITE.LW)
				;2650	;  ALU.NZVC set by LONGWORD AND with mask<31> = 0  --> N = V = 0
				;2651
				;2652	CONSOLE.GET.NEXT.BIT:
				;2653		;---------------------------------------; alu.z = 0:
E 3FA  0000,0000,2000,50FD B 3FD;2654		CASE [TEST.PINS] AT [CONSOLE.STROBE.0]	; [L3] wait for strobe deassertion
				;2655
				;2656	CONSOLE.WRITE.LW:
				;2657		;---------------------------------------; alu.z = 1:
E 3FE  0064,8012,2000,033B J 33B;2658		MEM (VA)&, [WBUS] <-- PASSB [W1], LONG	; [L3] write longword to Pcache
				;2659
				;2660		;---------------------------------------;
				;2661		VA <-- [VA] + 4,			; [L4] increment VA to next longword
E 33B  2C00,0001,20B0,41EB B 3EB;2662		CASE [ALU.NZV] AT [CONSOLE.WRITE.CONT] ; case on 32K bits accumulated from [L2]
				;2663
				;2664	;= ALIGNLIST 10*x	(CONSOLE.WRITE.CONT,	CONSOLE.LOAD.PC.CONT)
				;2665	;  ALU.NZVC set by AND --> V = 0
				;2666
				;2667	CONSOLE.WRITE.CONT:
				;2668		;---------------------------------------; alu.z = 0:
E 3EB  0000,0000,2000,50FD B 3FD;2669		CASE [TEST.PINS] AT [CONSOLE.STROBE.0]	; [L3] wait for strobe deassertion
				;2670
				;2671	;= ALIGNLIST 110x	(CONSOLE.STROBE.0,	CONSOLE.STROBE.1)
				;2672
				;2673	CONSOLE.STROBE.0:
				;2674		;---------------------------------------; strobe = 0:
			    p.89;2675		[W0] <-- [W0] + 1, LONG,		; increment running bit count
E 3FD  0800,0000,0410,50E8 B 3E8;2676		CASE [TEST.PINS] AT [CONSOLE.DATA.0.STROBE.0]	; strobe deasserted, get next bit
				;2677
				;2678	CONSOLE.STROBE.1:
				;2679		;---------------------------------------; strobe = 1 or alu.n = 1:
E 3FF  0000,0000,2000,50FD B 3FD;2680		CASE [TEST.PINS] AT [CONSOLE.STROBE.0] ; strobe asserted, wait
				;2681
				;2682	;= END POWERUP
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   92
;    INTEXC.MIC 	     INTEXC.MIC -- Interrupts and Exceptions						      /REV=
;
				;2683	.TOC	"INTEXC.MIC -- Interrupts and Exceptions"
				;2684	.TOC	"Revision 1.6"
				;2685
				;2686	;	Mike Uhler, Bob Supnik
				;2687
;2688	.nobin
;2689	;****************************************************************************
;2690	;*									    *
;2691	;*  COPYRIGHT (c) 1987, 1988, 1989, 1990, 1991, 1992 BY 		    *
;2692	;*  DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASSACHUSETTS.		    *
;2693	;*  ALL RIGHTS RESERVED.						    *
;2694	;*									    *
;2695	;*  THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED   *
;2696	;*  ONLY IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE   *
;2697	;*  INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE OR ANY  OTHER   *
;2698	;*  COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY   *
;2699	;*  OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE IS  HEREBY   *
;2700	;*  TRANSFERRED.							    *
;2701	;*									    *
;2702	;*  THE INFORMATION IN THIS SOFTWARE IS  SUBJECT TO CHANGE WITHOUT NOTICE   *
;2703	;*  AND  SHOULD  NOT  BE  CONSTRUED AS	A COMMITMENT BY DIGITAL EQUIPMENT   *
;2704	;*  CORPORATION.							    *
;2705	;*									    *
;2706	;*  DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE  OR  RELIABILITY OF ITS   *
;2707	;*  SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.		    *
;2708	;*									    *
;2709	;****************************************************************************
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   93
;    INTEXC.MIC 	     Revision History									      /REV=
;
;2710	.TOC	"	Revision History"
;2711
;2712	; Edit	  Date	 Who	     Description
;2713	; ---- --------- ---	---------------------
;2714	;    6 01-Aug-91 GMU	Symptom: FPD opcode filter too long and too slow.
;2715	;			Cure:	 Rewrite the FPD filter algorithm to be
;2716	;				 more space and time efficient.
;2717	;    5 22-May-91 GMU	Symptom: When the instruction emulator for POLYx
;2718	;				 detects a fault in the instruction execution,
;2719	;				 it packs up state in the GPRs, sets PSL<FPD>,
;2720	;				 and dispatches to the appropriate handler.
;2721	;				 When the handler fixes the problem and REIs
;2722	;				 to restart the POLYx, a reserved instruction
;2723	;				 fault is supposed to be taken with PSL<FPD>
;2724	;				 set.  The NVAX implementation prioritizes
;2725	;				 PSL<FPD> above reserved instruction fault,
;2726	;				 so an emulated FPD fault is generated instead
;2727	;				 and the emulator faults out the unexpected
;2728	;				 opcode.  This same discussion applies to all
;2729	;				 other unimplemented opcodes, but an analysis
;2730	;				 of the emulator suggests that only the emulation
;2731	;				 of POLYx currently makes use of PSL<FPD>.
;2732	;			Cure:	 An opcode filter has been added to the FPD
;2733	;				 flow to check for all emulated instructions and
;2734	;				 dispatch them to the emulate FPD handler.  All
;2735	;				 remaining instructions are then dispatched to the
;2736	;				 reserved instruction fault handler.  The filter
;2737	;				 freely uses don't care opcode bits in such a way
;2738	;				 that some legal opcodes are dispatched to the
;2739	;				 emulate FPD handler.
;2740	;    4 20-May-91 GMU	Symptom: Certain console halts may be invoked from
;2741	;				 flows in which a RESET CPU and call to IE.CLEANUP.CPU
;2742	;				 have been performed (e.g., halt interrupt,
;2743	;				 interrupt stack not valid, illegal SCB vector).
;2744	;				 If this call packs up the state for a string
;2745	;				 instruction, a second RESET CPU and call to IE.CLEANUP.CPU
;2746	;				 leaves SAVEPSL with FPD set and SAVEPC pointing
;2747	;				 at the instruction following the string instruction
;2748	;				 rather than at the string instruction.
;2749	;			Cure:	 For those non-error related halts in which
;2750	;				 string state may have been packed up, change
;2751	;				 to use the CONSOLE HALT NO CLEANUP macro,
;2752	;				 which avoids the second RESET CPU and call to
;2753	;				 IE.CLEANUP.CPU.  Console halts that are due to
;2754	;				 errors in any form are not changed to guarantee
;2755	;				 that a RESET CPU is performed.
;2756	;    3 09-Apr-91 GMU	Symptom: The Mbox PA queue state isn't cleared after
;2757	;				 a FLUSH PA QUEUE until the Mbox is free
;2758	;				 to drive an S5 transaction from the EM latch.
;2759	;				 If the Mbox is servicing Cbox requests, the
;2760	;				 PA queue status bits don't change in time to
;2761	;				 prevent a store from advancing incorrectly
;2762	;				 from Ebox S4 into the EM latch.
;2763	;			Cure:	 Insert a second SYNCHRONIZE MBOX at IE.BRANCH..
;2764	;				 to force the Ebox to stall until the first
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   94
;    INTEXC.MIC 	     Revision History									      /REV=
;
;2765	;				 SYNCHRONIZE MBOX is serviced by the Mbox.
;2766	;				 This allows time for the PA queue state to change.
;2767	;    2 15-Oct-90 GMU	Symptom: If an S3 stall timeout was caused by a spec
;2768	;				 queue request that didn't finish for some
;2769	;				 reason, the Mbox would retry the request because
;2770	;				 it wasn't receiving E%FLUSH_MBOX_H before
;2771	;				 the special reset signal was deasserted.  As
;2772	;				 it turns out, the RESET CPU is REQUIRED before
;2773	;				 the special reset is deasserted.
;2774	;			Cure:	 Add a RESET CPU to the IE.ASYNC.HW.ERROR..
;2775	;				 entry point.  Note that this assumes that the
;2776	;				 special reset signal is at least 5 cycles
;2777	;				 in length.
;2778	;    1 25-Sep-90 GMU	Symptom: One of the effects of S3 stall timeout is
;2779	;				 the assertion of a special reset signal
;2780	;				 to the Mbox and Cbox.	This signal was previously
;2781	;				 asserted for 6 cycles, but a recent design
;2782	;				 change made it 18 cycles.  During the assertion
;2783	;				 of this signal, no Mbox or Cbox request may
;2784	;				 be made by the microcode, and the Mbox
;2785	;				 designers weren't clear about whether RESET CPU
;2786	;				 could be asserted during the assertion of
;2787	;				 the reset signal.
;2788	;			Cure:	 Add 3 microwords just above WAIT.TWO.CYCLES
;2789	;				 to implement a 23 cycle delay.  This routine
;2790	;				 is then called from IE.ASYNC.HW.ERROR.. before
;2791	;				 the machine check routine is entered.	With
;2792	;				 pipe latency from the start of the microtrap,
;2793	;				 this implements a 28-cycle delay before the
;2794	;				 RESET CPU and a 37-cycle delay before the first
;2795	;				 Mbox request.	This is overkill relative to
;2796	;				 the desired 18-cycle delay, but adds enough
;2797	;				 delay to allow additional small changes to the
;2798	;				 signal length with no additional microcode
;2799	;				 changes.
;2800	; (1)0 17-Jul-90 GMU	Initial production microcode.
;2801	;
;2802	; Begin version 1.0 here
;2803	;   31 16-Jul-90 GMU	Add delay at the start of the asynchronous hardware
;2804	;			error microtrap sequence that is required by the
;2805	;			Mbox/Cbox pseudo reset generated by S3 stall timeout.
;2806	;   30 01-Jul-90 GMU	Add support for performance monitoring facility.
;2807	;   29 05-Jun-90 GMU	Update SEQ.COND names to match implementation.
;2808	;   28 03-May-90 GMU	Reverse order of duplicate labels so that the one
;2809	;			included in an ALIGNLIST is last.
;2810	;   27 03-May-90 GMU	Fix bug in edit 26 that caused SP to be trashed at
;2811	;			the exit from an exception flow.
;2812	;   26 01-May-90 GMU	Read VAX restart bit before call to IE.EXCEPTION so
;2813	;			that it is not cleared by the stack writes.
;2814	;   25 01-May-90 GMU	Uncomment references to CWB IPR.
;2815	;   24 01-May-90 GMU	Save original value of SAVEPC in machine check stack
;2816	;			frame to allow software to find the correct PC for
;2817	;			a machine check due to a PTE read error in an interruptable
;2818	;			instruction.  This causes a change to the machine check
;2819	;			frame format.
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   95
;    INTEXC.MIC 	     Revision History									      /REV=
;
;2820	;   23 30-Apr-90 GMU	Sync with Mbox after LOAD PC.
;2821	;   22 26-Apr-90 GMU	Convert '*' fill constraints to 'x' constraints.
;2822	;   21 26-Mar-90 GMU	Clear state<3> in queue packup routine before first
;2823	;			memory reference.
;2824	;   20 28-Feb-90 GMU	Convert Fbox exception handler to obtain condition
;2825	;			from the FBOX.CONDITION decode rather than from
;2826	;			FBOX.FAULT.CODE.
;2827	;   19 12-Feb-90 GMU	Remove FLUSH VIC from machine check flow.
;2828	;   18 19-Jan-90 GMU	Add code to clear CEFSTS RDLK bit in machine check.
;2829	;			This code is currently commented out until the model
;2830	;			catches up.
;2831	;   17 19-Jan-90 GMU	FLUSH BRANCH PREDICTION CACHE -> FLUSH BRANCH PREDICTION TABLE.
;2832	;   16 19-Jan-90 GMU	Add CPUID to machine check stack frame description.
;2833	;   15 09-Jan-90 GMU	Modify interrupt routine to reflect new hardware design
;2834	;			of interrupt section.
;2835	;   14 05-Jan-90 GMU	Remove IE.VECT.ISSUE.. routine.
;2836	;   13 07-Dec-89 GMU	Continue comment update, remove use of ZEXTWL ALU function.
;2837	;   12 06-Dec-89 GMU	Remove FLUSH BPC from cleanup routine.
;2838	;   11 17-Nov-89 GMU	Convert CLEAR WRITE BUFFER macro to use IPR write.
;2839	;   10 07-Nov-89 GMU	Convert all flows to use new RESET CPU interface.
;2840	;    9 25-Oct-89 GMU	Clean up string pack/unpack interface.
;2841	;    8 24-Oct-89 GMU	Don't clear state<5:4> until after all stack writes have
;2842	;			cleared memory management checks.  Also, clear both
;2843	;			bits after KSNV.
;2844	;    7 23-Oct-89 GMU	Clean up interface between CHMx and PROBEx faults and
;2845	;			IE.MEMMGT.
;2846	;    6 09-Oct-89 GMU	Change to reflect backup PC returned in SAVEPC from
;2847	;			call to REINITIALIZE.CPU.
;2848	;    5 01-Oct-89 GMU	Patch vector fault handler until the hardware drives
;2849	;			the correct value on the microtest bus.
;2850	;    4 29-Sep-89 GMU	Fix FPD entry point restart of instructions.
;2851	;    3 18-Aug-89 GMU	Rewrite ACV/TNV/M=0 routine.
;2852	;    2 16-Aug-89 GMU	Add termporary sim halt in exception handler.
;2853	;    1 19-Jul-89 GMU	Update to latest design.
;2854	; (0)0 16-Sep-87 RMS	Trial microcode.
;2855
				;2856	.bin
				;2857	;= BEGIN INTEXC
;2858	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   96
;    INTEXC.MIC 	     Revision History									      /REV=
;															     INTEXC
;2859
;2860	;	Interrupts and exceptions fall into three basic classes:  traps, faults, and aborts.
;2861	;	In each case the PC and the PSL are pushed onto the stack.  In certain cases, parameters
;2862	;	are also pushed.  Traps occur at the end of the instruction that caused the exception.
;2863	;	Faults occur during an instruction but leave the registers and memory such that elimination
;2864	;	of the fault condition and restarting the instruction will give correct results.  Aborts
;2865	;	occur during an instruction but leave the registers and memory such that the instruction
;2866	;	cannot necessarily be restarted.
;2867
;2868	;	Hardware dispatches:
;2869	;
;2870	;	Entry Point		From			Comments
;2871	;	-----------		----			--------
;2872	;	IE.POWERUP..		microtrap		powerup microtrap (in POWERUP.MIC)
;2873	;	IE.ASYNC.HW.ERROR..	microtrap		asynchronous hardware error
;2874	;	IE.RSVD.OPCODE.TRAP..	microtrap		reserved instruction fault (generated for floating point
;2875	;							instructions when the Fbox is disabled)
;2876	;	IE.SYNC.HW.ERROR..	mirotrap		synchronous hardware error
;2877	;	IE.MEMMGT..		microtrap		memory management exception
;2878	;	IE.INT.OVERFLOW..	microtrap		integer overflow trap
;2879	;	IE.BRANCH..		microtrap		branch mispredict trap
;2880	;	IE.RSVD.ADDRESS..	microtrap		reserved addressing mode
;2881	;	IE.FLT.FAULT..		microtrap		floating point fault
;2882	;	IE.INT..		exception dispatch	interrupt pending
;2883	;	IE.TRACE.TRAP.. 	exception dispatch	trace fault
;2884	;	IE.FPD..		execution dispatch	PSL<FPD> set at instruction dispatch
;2885	;	IE.STALL..		execution dispatch	instruction queue empty at instruction dispatch
;2886	;	RSVD.OPCODE..		execution or microcode	reserved instruction fault
;2887	;				dispatch
;2888	;
;2889	;	Microcode dispatches:
;2890	;
;2891	;	Entry Point		From			Comments
;2892	;	-----------		----			--------
;2893	;	IE.CONSOLE.HALT..	various 		console restart (in POWERUP.MIC)
;2894	;	IE.MACHINE.CHECK..	various 		machine check fault
;2895	;	IE.RSVD.OPERAND..	various 		reserved operand fault
;2896	;	IE.INT.FAULT..		CSTRING.MIC		interrupt in mid instruction (treated as a fault)
;2897	;	IE.SUBSCRIPT.ERROR..	MISC.MIC		subscript range trap
;2898	;	IE.DIVIDE.ERROR..	MULDIV.MIC		integer divide-by-zero trap
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   97
;    INTEXC.MIC 	     Revision History									      /REV=
;															     INTEXC
;2899
;2900	;	Design considerations in this module:
;2901	;
;2902	;	CPU CLEANUP REQUIREMENTS ON ENTRY
;2903	;
;2904	;	In many instances, this module is entered via microtrap or via
;2905	;	direct dispatch from the execution flows.  As a result, there
;2906	;	may be an unspecified number of outstanding reads to arbitrary
;2907	;	working registers.  Therefore, no working register may be either
;2908	;	read or written until other activity has been aborted.
;2909	;
;2910	;	With a few rare exceptions which are clearly documented in
;2911	;	the code, all entry points into this module must issue RESET CPU
;2912	;	and then perform the operations required to clean up the Ibox
;2913	;	and Mbox state.  In most instances, this is accomplished by
;2914	;	calling either IE.CLEANUP.CPU or IE.CLEANUP.CPU.NO.PACKUP from
;2915	;	the entry point.  These routines correctly clean up CPU state
;2916	;	and are written to conform to the requirements that are imposed
;2917	;	on this process.
;2918	;
;2919	;	Due to specific requirements in the routines, two routines
;2920	;	(IE.MEMMGT.. and IE.MACHINE.CHECK..) do not call IE.CLEANUP.CPU
;2921	;	in the microinstruction at the entry point of the routine.  In
;2922	;	these instances, the code following the entry point must be
;2923	;	aware that there are two fundamental restrictions on the
;2924	;	two microinstructions following the one in which the RESET CPU
;2925	;	is issued:
;2926	;
;2927	;		1. There must not be any read or write to a working
;2928	;		   register in either microinstruction.
;2929	;		2. There must not be any Mbox request via the MRQ or
;2930	;		   DST fields in either microinstruction.
;2931	;
;2932	;	These restrictions are imposed by the timing of RESET CPU.
;2933	;	Failure to observe these restriction results in UNDEFINED
;2934	;	behavior, including the possibility of hanging the CPU.
;2935	;	Both of these restrictions are met by calls to IE.CLEANUP.CPU
;2936	;	and IE.CLEANUP.CPU.NO.PACKUP from the microinstruction that
;2937	;	issues RESET CPU.
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   98
;    INTEXC.MIC 	     Revision History									      /REV=
;															     INTEXC
;2938
;2939	;	STATE FLAG USAGE AND OPERATION
;2940	;
;2941	;	There are six state flags, state<5:0>, provided by Ebox hardware.
;2942	;	Three of them, state<2:0>, are provided for the arbitrary use
;2943	;	of instruction flows.  Some of these flags are also used within
;2944	;	the IE.EXCEPTION and IE.INTERRUPT routines, after they are
;2945	;	explicitly cleared.
;2946	;
;2947	;	One state flag, state<3>, is used to communicate information from
;2948	;	an instruction flow to an exception flow in this module.  state<3>
;2949	;	is set by an instruction flow when it wants to perform some special
;2950	;	cleanup action in the event that an exception or interrupt occurs during
;2951	;	instruction execution.	At present, this feature is used only by
;2952	;	the interlocked queue and the string instructions.  When
;2953	;	IE.CLEANUP.CPU is called, it checks the value of state<3> and
;2954	;	dispatches to the appropriate routine if the bit is set.  For
;2955	;	the interlocked queue instructions, the secondary interlock
;2956	;	in the queue header is released.  For the string instructions,
;2957	;	state is packed into the GPRs, and PSL<FPD> is set.
;2958	;
;2959	;	state<3:0> are automatically cleared by the hardware on
;2960	;	instruction and FPD dispatches.  These bits are explicitly not
;2961	;	cleared for other microtrap or non-instruction dispatches.
;2962	;	IE.CLEANUP.CPU.NO.PACKUP may be called in those instances where
;2963	;	it is known by context that state<3> has no meaning to force
;2964	;	state<3:0> to 0 before continuing with the cleanup process.
;2965	;
;2966	;	Two state flags, state<5:4>, are the so-called permanent state
;2967	;	flags, and are used exclusively by this module to encode the
;2968	;	current state of exception processing, as follows:
;2969	;
;2970	;		state<5:4>	Meaning
;2971	;		----------	-------
;2972	;		    00		Not in any of the following flows.
;2973	;		    01		Processing interrupt or exception
;2974	;		    10		Processing machine check
;2975	;		    11		Processing kernel stack not valid
;2976	;
;2977	;	The appropriate combination of these flags is set before any
;2978	;	stack writes are attempted.  If the memory management exception
;2979	;	or machine check routine is entered with state<5:4> having
;2980	;	a value other than 00, a console halt sequence is initiated.
;2981	;	In this manner, recursive failures are detected.
;2982	;
;2983	;	Flows other than machine check clear both state flags after
;2984	;	all stack writes are complete, but before dispatching the
;2985	;	event to the operating system.	The machine check flow
;2986	;	explicitly does not clear state<5> on exit.  Instead, the
;2987	;	operating system is required to acknowledge the machine check
;2988	;	via a write to the MCESR processor register, which clears
;2989	;	state<5:4> at that point.  In this manner, recursion is
;2990	;	detected all the way to the software machine check handler.
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page   99
;    INTEXC.MIC 	     Revision History									      /REV=
;															     INTEXC
;2991
;2992	;	WORKING REGISTER USAGE
;2993	;
;2994	;	Working register usage within this module is governed by several
;2995	;	constraints.  The special packup routines for the interlocked
;2996	;	queue and the string instructions assume that certain state
;2997	;	has not changed relative to the instruction flow that caused
;2998	;	the original fault.  For this reason, W0 and W3 must not be
;2999	;	destroyed before the call to IE.CLEANUP.CPU, if state<3> is
;3000	;	set.
;3001	;
;3002	;
;3003	;	Specific usage of each working register in this module is
;3004	;	shown below:
;3005	;
;3006	;	W0:	Available after the call to IE.CLEANUP.CPU.  Used as
;3007	;		general temporary and trashed by IE.EXCEPTION/IE.INTERRUPT.
;3008	;
;3009	;	W1:	Trashed by IE.CLEANUP.CPU.  SCB offset as input to,
;3010	;		and SCB vector as output from IE.EXCEPTION/IE.INTERRUPT.
;3011	;
;3012	;	W2:	Exception PSL as input to and output from IE.EXCEPTION/IE.INTERRUPT
;3013	;
;3014	;	W3:	Available after the call to IE.CLEANUP.CPU.  Masked IPL
;3015	;		as input to IE.INTERRUPT.  Used as a general temporary and
;3016	;		trashed by IE.EXCEPTION/IE.INTERRUPT.
;3017	;
;3018	;	W4:	Available to flows.  Preserved by IE.EXCEPTION/IE.INTERRUPT.
;3019	;
;3020	;	W5:	Available to flows.  Preserved by IE.EXCEPTION/IE.INTERRUPT.
;3021	;
;3022	;	In addition to W4 and W5, both SAVEPSL and Q are preserved by
;3023	;	IE.EXCEPTION/IE.INTERRUPT, and may be used to save values across the
;3024	;	call to these routines.
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  100
;    INTEXC.MIC 	     Revision History									      /REV=
;															     INTEXC
;3025
;3026	;	Implementation dependent decisions in INTEXC:
;3027	;
;3028	;	    1.	Vector<1:0> = 0 during machine check or ksnv is treated like
;3029	;		a normal exception, i.e., the exception is processed on the
;3030	;		kernel stack, and the IPL is not changed.
;3031	;
;3032	;	    2.	Vector<1:0> neq 0 during CHMx is IGNORED.
;3033	;
;3034	;	    3.	Vector<1:0> = 2 during any interrupt or other exception
;3035	;		causes a console restart (code = ERR.WCSVEC).
;3036	;
;3037	;	    4.	Vector<1:0> = 3 during any interrupt or other exception
;3038	;		causes a console restart (code = ERR.ILLVEC).
;3039	;
;3040	;	    5.	ACV/TNV during kernel stack not valid or
;3041	;		machine check causes a console restart.
;3042	;
;3043	;	    6.	Machine check during any exception causes
;3044	;		a console restart.
;3045	;
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  101
;    INTEXC.MIC 	     Revision History									      /REV=
;															     INTEXC
;3046
;3047	;	This is a list of machine checks in the microcode:
;3048	;
;3049	;	Mnemonic	   Dispatched From		Condition
;3050	;	--------	   ---------------	--------------------------------------
;3051	;	MCHK.UNKNOWN.MSTATUS	INTEXC		Unknown memory management status
;3052	;	MCHK.INT.ID.VALUE	INTEXC		Unknown interrupt ID
;3053	;	MCHK.CANT.GET.HERE	CALLRET 	Unknown microcode dispatch
;3054	;	MCHK.MOVC.STATUS	CSTRING 	Unknown MOVCx status
;3055	;	MCHK.ASYNC.ERROR	INTEXC		Asynchronous hardware error microtrap
;3056	;	MCHK.SYNC.ERROR 	INTEXC		Synchronous hardware error microctrap
;3057	;	MCHK.PMF.CONFIG 	OPSYS		Illegal PMF SCB vector
;3058	;
;3059	;	This is a list of console restarts in the microcode:
;3060	;
;3061	;	Mnemonic	   Dispatched From			Condition
;3062	;	--------	   ---------------	----------------------------------------------
;3063	;	ERR.HLTPIN		INTEXC		HALT pin asserted
;3064	;	ERR.PWRUP		POWERUP 	power up
;3065	;	ERR.INTSTK		INTEXC		interrupt stack not valid
;3066	;	ERR.DOUBLE		INTEXC		double fatal error
;3067	;	ERR.HLTINS		MISC		HALT instruction
;3068	;	ERR.ILLVEC		INTEXC		illegal vector
;3069	;	ERR.WCSVEC		INTEXC		vector to WCS
;3070	;	ERR.CHMFI		OPSYS		CHMx on interrupt stack
;3071	;	ERR.IE0 		INTEXC		ACV/TNV during machine check exception
;3072	;	ERR.IE1 		INTEXC		ACV/TNV during kernel stack not valid exception
;3073	;	ERR.IE2 		INTEXC		machine check during machine check exception
;3074	;	ERR.IE3 		INTEXC		machine check during kernel stack not valid exception
;3075	;	ERR.IE.PSL.26-24.101	INTEXC		PSL<26:24> = 101 during interrupt or exception
;3076	;	ERR.IE.PSL.26-24.110	INTEXC		PSL<26:24> = 110 during interrupt or exception
;3077	;	ERR.IE.PSL.26-24.111	INTEXC		PSL<26:24> = 111 during interrupt or exception
;3078	;	ERR.REI.PSL.26-24.101	OPSYS		PSL<26:24> = 101 during REI
;3079	;	ERR.REI.PSL.26-24.110	OPSYS		PSL<26:24> = 110 during REI
;3080	;	ERR.REI.PSL.26-24.111	OPSYS		PSL<26:24> = 111 during REI
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  102
;    INTEXC.MIC 	     Instruction Dispatch Stall 							      /REV=
;															     INTEXC
;3081	.TOC	"	Instruction Dispatch Stall"
;3082
;3083	;	This routine is dispatched by the microsequencer if the
;3084	;	instruction queue is empty at the last cycle of the
;3085	;	previous flow.
;3086	;
;3087	;	Entry conditions:
;3088	;		none
;3089	;
;3090	;	Exit conditions:
;3091	;		try to decode next instruction
;3092	;
				;3093	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  103
;    INTEXC.MIC 	     Instruction Dispatch Stall 							      /REV=
;															     INTEXC
				;3094
				;3095	;	Instruction dispatch stall.
				;3096
				;3097	;	Entered by microsequencer dispatch.  Machine state should
				;3098	;	not be disturbed as this is a temporary condition that will be
				;3099	;	resolved when the Ibox delivers either a new instruction or an
				;3100	;	exception dispatch.
				;3101	;
				;3102	;	Note: A NOP NODEST macro must be used here to prevent
				;3103	;	an RM stall if the next instruction to be retired is
				;3104	;	from the F-box.
				;3105
				;3106	IE.STALL..:
				;3107		;********** Hardware dispatch **********;
				;3108		NOP NODEST,				; No destination for instruction
E 030  1000,0100,0000,1000 L	;3109		LAST CYCLE NO RETIRE			; decode next instruction
				;3110
;3111	.nobin
;3112
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  104
;    INTEXC.MIC 	     Branch Mispredict Microtrap							      /REV=
;															     INTEXC
;3113	.TOC	"	Branch Mispredict Microtrap"
;3114
;3115	;	This routine is entered from a microtrap if the Ebox branch
;3116	;	direction does not match that predicted by the Ibox.
;3117	;
;3118	;	Entry conditions:
;3119	;		none
;3120	;
;3121	;	Exit conditions:
;3122	;		synchronize with previous EM latch store.
;3123	;		flush PA queue and restart Mbox
;3124	;		try to decode next instruction.
;3125	;
				;3126	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  105
;    INTEXC.MIC 	     Branch Mispredict Microtrap							      /REV=
;															     INTEXC
				;3127
				;3128	;	Branch mispredict.
				;3129	;
				;3130	;	Entered by microtrap.  The microtrap itself flushes most of the
				;3131	;	Ebox, Fbox, and Mbox state, and redirects the Ibox to the
				;3132	;	alternate instruction stream.  Because there may be a store
				;3133	;	pending in the EM latch that requires one or more PA queue entries,
				;3134	;	the PA queue is not flushed as a byproduct of the branch mispredict
				;3135	;	microtrap.  Instead, the microcode must synchronize with the completion
				;3136	;	of any possible store, and then explicitly flush the PA queue and
				;3137	;	restart the Mbox before starting the next instruction.
				;3138
				;3139	IE.BRANCH..:
				;3140		;********** Hardware dispatch **********;
				;3141		SYNCHRONIZE MBOX,			; sync with possible store,
				;3142		FLUSH PA QUEUE, 			; then flush the PA queue,
E 00C  1020,0400,2004,8183 J 183;3143		RESTART MBOX				; and restart the Mbox
				;3144
				;3145	;	Note: the following microinstruction contains a SYNCHRONIZE MBOX,
				;3146	;	which forces an EM latch stall at this point until the Mbox drives
				;3147	;	the previous microinstruction into S5.	This is required to allow
				;3148	;	the Mbox time to reset the PA queue status from non-empty to empty.
				;3149	;	Without this second SYNCHRONIZE MBOX, the Ebox may incorrectly
				;3150	;	drive a store into the EM latch even though the PA queue has no
				;3151	;	valid entries.
				;3152
				;3153		;---------------------------------------;
				;3154		SYNCHRONIZE MBOX,			; force stall until PA queue status changes
E 183  1020,0100,2000,1000 L	;3155		LAST CYCLE NO RETIRE			; decode next instruction
;3156	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  106
;    INTEXC.MIC 	     FPD -- PSL<fpd> Set								      /REV=
;															     INTEXC
;3157	.TOC	"	FPD -- PSL<fpd> Set"
;3158
;3159	;	This routine is dispatched by the microsequencer when the
;3160	;	instruction queue contains a vaild dispatch and PSL<FPD> is
;3161	;	set.  The Ibox has parsed only the instruction opcode.
;3162	;
;3163	;	Entry conditions:
;3164	;		RN.MODE.OPCODE	=	instruction opcode
;3165	;		Ibox state	=	stopped, waiting for LOAD PC
;3166	;
;3167	;	Exit conditions:
;3168	;		Dispatch to instruction specific restart routine.
;3169	;
;3170	;	Note: This routine is fairly complex because there are four classes
;3171	;	of instructions that must be separated:
;3172	;
;3173	;		1. The 8 string instructions which are implemented by the
;3174	;		   microcode, and for which the microcode directly manipulates
;3175	;		   PSL<FPD>: MOVC3 (28), MOVC5 (2C), CMPC3 (29), CMPC5 (2D),
;3176	;		   LOCC (3A), SKPC (3B), SCANC (2A), SPANC (2B).  These instructions
;3177	;		   are dispatched directly to the string uppack code in
;3178	;		   CSTRING.MIC.
;3179	;
;3180	;		2. The 21 emulated instructions which are processed by the
;3181	;		   VAX instruction emulator thru the emulated instruction
;3182	;		   interface: CVTPS (08), CVTSP (09), CRC (0B), ADDP4 (20),
;3183	;		   ADDP6 (21), SUBP4 (22), SUBP6 (23), CVTPT (24), MULP (25),
;3184	;		   CVTTP (26), DIVP (27), MOVTC (2E), MOVTUC (2F), MOVP (34),
;3185	;		   CMPP3 (35), CVTPL (36), CMPP4 (37), EDITPC (38), MATCHC (39),
;3186	;		   ASHP (F8), CVTLP (F9).  These instructions are dispatched
;3187	;		   to the emulate FPD code in EMULATE.MIC.
;3188	;
;3189	;		3. The 41 unimplemented instructions which may be processed
;3190	;		   by the VAX instruction emulator thru the reserved instruction
;3191	;		   fault interface:
;3192	;		   ACBF (4F), EMODF (54), POLYF (55), ACBD (6F), EMODD (74),
;3193	;		   POLYD (75), CVTDH (FD32), ACBG (FD4F), EMODG (FD54),
;3194	;		   POLYG (FD55), CVTGH (FD56), ADDH2 (FD60), ADDH3 (FD61), SUBH2 (FD62),
;3195	;		   SUBH3 (FD63), MULH2 (FD64), MULH3 (FD65), DIVH2 (FD66), DIVH3 (FD67),
;3196	;		   CVTHB (FD68), CVTHW (FD69), CVTHL (FD6A), CVTRHL (FD6B), CVTBH (FD6C),
;3197	;		   CVTWH (FD6D), CVTLH (FD6E), ACBH (FD6F), MOVH (FD70), CMPH (FD71),
;3198	;		   MNEGH (FD72), TSTH (FD73), EMODH (FD74), POLYH (FD75), CVTHG (FD76),
;3199	;		   CLRO (FD7C), MOVO (FD7D), MOVAO (FD7E), PUSHAO (FD7F), CVTFH (FD98),
;3200	;		   CVTHF (FDF6), CVTHD (FDF7).
;3201	;		   These instructions are dispatched to the reserved instruction
;3202	;		   fault handler.
;3203	;
;3204	;		4. All other instructions, for which setting PSL<FPD> results
;3205	;		   in UNPREDICTABLE operations as defined in the SRM.  These
;3206	;		   instructions may be dispatched to either the emulate FPD
;3207	;		   handler or to the reserved instruction fault handler.
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  107
;    INTEXC.MIC 	     FPD -- PSL<fpd> Set								      /REV=
;															     INTEXC
;3208
;3209	;	Note that both single-byte and FD opcodes map together when opcode
;3210	;	tests are done in the code flow below because the opcode value returned
;3211	;	by the hardware for FD opcodes is the second opcode byte, not the value FD.
;3212	;	The opcodes are first separated into 4 categories based on bits <7:6>
;3213	;	of the opcode, as follows:
;3214	;
;3215	;	      Opcode Range			Action Taken
;3216	;	      ------------	------------------------------------------------
;3217	;		00 .. 3F	8 class 1 (string), 19 class 2 (emulated), 1
;3218	;				class 3 (unimplemented) instructions in this
;3219	;				category.  Classes are separated and dispatched
;3220	;				to the appropriate handler.
;3221	;
;3222	;		40 .. 7F	37 class 3 (unimplemented) instructions in
;3223	;				this category.	All instructions are dispatched
;3224	;				to reserved instruction fault handler.
;3225	;
;3226	;		80 .. BF	1 class 3 (unimplemented) instructions in this
;3227	;				category.  All instructions are dispatched to
;3228	;				reserved instruction fault handler.
;3229	;
;3230	;		C0 .. FF	2 class 2 (emulated), 2 class 3 (unimplemented)
;3231	;				instructions in this category.	Classes are
;3232	;				separated and dispatched to the appropriate
;3233	;				handler.
;3234
				;3235	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  108
;    INTEXC.MIC 	     FPD -- PSL<fpd> Set								      /REV=
;															     INTEXC
				;3236
				;3237	;	FPD processor.
				;3238
				;3239	;	Note: RESET CPU is not performed here so that the string
				;3240	;	unpack routine can restore the state of the CPU to that
				;3241	;	provided by the initial string instruction dispatch.  A
				;3242	;	RESET CPU is done in the emulated instruction restart routine
				;3243	;	and in the reserved instruction fault routine.
				;3244	;
				;3245	;	Because this is a microsequencer dispatch, all working
				;3246	;	registers are available without a RESET CPU.
				;3247	;
				;3248	;	Note: state<3:0> are cleared by the hardware on this entry point.
				;3249	;
				;3250
				;3251	IE.FPD..:
				;3252		;********** Hardware dispatch **********;
E 02C  0001,D07A,0800,0189 J 189;3253		[W1] <-- ZEXT [RN.MODE.OPCODE] RSH [16.] ; [1] position opcode to <7:0>
				;3254
				;3255		;---------------------------------------;
E 189  0400,27D0,0C20,0414 J 414;3256		[W2] <-- [W1] AND 000000[0FA], LONG	; [2] mask opcode to bits<7:3,1>,
				;3257							; test opcode on Abus
				;3258
				;3259		;---------------------------------------;
			    p109;3260		[WBUS] <-- [W2] XOR 000000[28], LONG,	; [3] test for MOVCx,CMPCx
E 414  A600,2140,2030,4583 B 483;3261		CASE [A.7-5] AT [IE.FPD.00..3F] 	; break out into opcode ranges
				;3262
				;3263	;= ALIGNLIST	001x	(IE.FPD.00..3F, 	IE.FPD.40..7F,
				;3264	;=			 IE.FPD.80..BF, 	IE.FPD.C0..FF)
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  109
;    INTEXC.MIC 	     FPD -- PSL<fpd> Set								      /REV=
;															     INTEXC
				;3265
				;3266	;	FPD breakout, continued.
				;3267	;	Opcode is known to be in the range 00..3F or FD00..FD3F, inclusive.
				;3268	;	Within this range, the clsss breakdown is as follows:
				;3269	;
				;3270	;		Class 1:	MOVC3 (28), MOVC5 (2C), CMPC3 (29), CMPC5 (2D),
				;3271	;				LOCC (3A), SKPC (3B), SCANC (2A), SPANC (2B)
				;3272	;		Class 2:	CVTPS (08), CVTSP (09), CRC (0B), ADDP4 (20),
				;3273	;				ADDP6 (21), SUBP4 (22), SUBP6 (23), CVTPT (24), MULP (25),
				;3274	;				CVTTP (26), DIVP (27), MOVTC (2E), MOVTUC (2F), MOVP (34),
				;3275	;				CMPP3 (35), CVTPL (36), CMPP4 (37), EDITPC (38), MATCHC (39),
				;3276	;		Class 3:	CVTDH (FD32)
				;3277	;
				;3278	;	Class 1 instructions are first separated and dispatched, followed by
				;3279	;	the single class 3 instruction.  All others are then dispatched to the
				;3280	;	emulated instruction handler.
				;3281	;
				;3282	;	At this point,
				;3283	;		W1<7:0> =	unmasked opcode (bits <15:8> not zero)
				;3284	;		W2	=	opcode AND FA#16
				;3285	;		WBUS.Z	=	1 if opcode is MOVCx, CMPCx (from cycle 3)
				;3286
				;3287	IE.FPD.00..3F:
				;3288		;---------------------------------------; a<7:6> = 00:
E 483  0400,2770,0C20,0163 J 163;3289		[W2] <-- [W1] AND 000000[0EE], LONG	; [4] mask opcode to bits<7:5,3:1>
				;3290
				;3291		;---------------------------------------;
				;3292		[WBUS] <-- [W2] XOR 000000[2A], LONG,	; [5] test for SCANC/SPANC/LOCC/SKPC
E 163  2600,2150,2030,4161 B 161;3293		CASE [ALU.NZV] AT [FPD.TEST]		; case on MOVCx/CMPCx opcode
				;3294
				;3295	;= ALIGNLIST x0xx	(FPD.TEST,		MOVC.CMPC.FPD)
				;3296	;  ALU.NZVC set by XOR, bit<31> clear in both operands	--> N = V = C = 0
				;3297
				;3298	FPD.TEST:
				;3299		;---------------------------------------; alu.z = 0:
E 161  0001,D882,1800,0043 J 043;3300		[W5] <-- ZEXT [R0] RSH [24.], LONG	; [6] isolate delta PC for unpack
				;3301
				;3302		;---------------------------------------;
			    p110;3303		[W2] <-- [W1] AND 000000[0FF], LONG,	; [7] mask opcode to bits <7:0>
E 043  2400,27F8,0C20,41E1 B 0E1;3304		CASE [ALU.NZV] AT [FPD.EMULATE.TEST]	; case on SCANC/SPANC/LOCC/SKPC
				;3305
				;3306	;= ALIGNLIST x0xx	(FPD.EMULATE.TEST,	SCANC.LOCC.FPD)
				;3307	;  ALU.NZVC set by XOR, bit<31> clear in both operands	--> N = V = C = 0
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  110
;    INTEXC.MIC 	     FPD -- PSL<fpd> Set								      /REV=
;															     INTEXC
				;3308
				;3309	;	FPD breakout continued.
				;3310	;	Opcode is known to be in the range 00..3F or FD00..FD3F, inclusive,
				;3311	;	and not one of the string instructions.
				;3312	;	Separate out CVTDH and dispatch the rest to the emulated instruction
				;3313	;	handler.
				;3314	;
				;3315	;	At this point,
				;3316	;		W2	=	opcode AND FF#16
				;3317
				;3318	FPD.EMULATE.TEST:
				;3319		;---------------------------------------;
			    p276;3320		[WBUS] <-- [W2] XOR 000000[32], LONG,	; [8] test for CVTDH
E 0E1  0600,2190,2030,2497 S 497;3321		CALL [WAIT.ONE.CYCLE]			; [9] wait for condition codes
				;3322
				;3323		;---------------------------------------;
				;3324		[W2] <-- [PSL] ANDNOT 000000[0FF],	; [10] copy PSL, clear <7:0>
				;3325		LONG,					;
			    p631;3326		Q <-- PASSA [PSL],			; save current PSL
E 0E2  2482,67F8,0CC0,41F0 B 0F0;3327		CASE [ALU.NZV] AT [EMULATE.FPD] 	; case on CVTDH
				;3328
				;3329	;= ALIGNLIST x0xx	(EMULATE.FPD,		FPD.CVTDH)
				;3330	;  ALU.NZVC set by XOR, bit<31> clear in both operands	--> N = V = C = 0
				;3331
				;3332	FPD.CVTDH:
			    p126;3333		;---------------------------------------; alu.z = 1:
E 0F4  0000,0000,2000,0100 J 100;3334		RESERVED INSTRUCTION FAULT		; [12] reserved opcode, fault
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  111
;    INTEXC.MIC 	     FPD -- PSL<fpd> Set								      /REV=
;															     INTEXC
				;3335
				;3336	;	FPD breakout, continued.
				;3337	;	Opcode is known to be in the range C0..FF or FDC0..FDFF, inclusive.
				;3338	;	Within this range, the clsss breakdown is as follows:
				;3339	;
				;3340	;		Class 1:	None
				;3341	;		Class 2:	ASHP (F8), CVTLP (F9)
				;3342	;		Class 3:	CVTHF (FDF6), CVTHD (FDF7)
				;3343	;
				;3344	;	Class 2 instructions are first separated and dispatched.  All others
				;3345	;	are then dispatched to the reserved instruction fault handler.
				;3346	;
				;3347	;	At this point,
				;3348	;		W2	=	opcode AND FA#16
				;3349
				;3350	IE.FPD.C0..FF:
				;3351		;---------------------------------------; a<7:6> = 11:
			    p276;3352		[WBUS] <-- [W2] XOR 000000[0F8], LONG,	; [4] test for ASHP/CVTLP/FC/FD
E 48F  0600,27C0,2030,2497 S 497;3353		CALL [WAIT.ONE.CYCLE]			; [5] wait for condition codes
				;3354
				;3355		;---------------------------------------;
E 480  2000,0000,2000,4120 B 420;3356		CASE [ALU.NZV] AT [FPD.TEST.1]		; [6] case on ASHP/CVTLP/FC/FD
				;3357
				;3358	;= ALIGNLIST x0xx	(FPD.TEST.1,		ASHP.CVTLP.FPD)
				;3359	;  ALU.NZVC set by XOR, bit<31> clear in both operands	--> N = V = C = 0
				;3360
				;3361	FPD.TEST.1:
			    p126;3362		;---------------------------------------; alu.z = 0:
E 420  0000,0000,2000,0100 J 100;3363		RESERVED INSTRUCTION FAULT		; [7] opcodes reserved, fault
				;3364
				;3365	ASHP.CVTLP.FPD:
				;3366		;---------------------------------------; alu.z = 1:
				;3367		[W2] <-- [PSL] ANDNOT 000000[0FF],	; [7] copy PSL, clear <7:0>
				;3368		LONG,					;
			    p631;3369		Q <-- PASSA [PSL],			; save current PSL
E 424  0482,67F8,0CC0,00F0 J 0F0;3370		GOTO [EMULATE.FPD]			; join FPD flow
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  112
;    INTEXC.MIC 	     FPD -- PSL<fpd> Set								      /REV=
;															     INTEXC
				;3371
				;3372	;	FPD breakout, continued.
				;3373	;	Opcode is known to be in the range 40..BF or FD40..FDBF, inclusive.
				;3374	;	Within this range, the clsss breakdown is as follows:
				;3375	;
				;3376	;		Class 1:	None
				;3377	;		Class 2:	None
				;3378	;		Class 3:	ACBF (4F), EMODF (54), POLYF (55), ACBD (6F), EMODD (74),
				;3379	;				POLYD (75), ACBG (FD4F), EMODG (FD54), POLYG (FD55),
				;3380	;				CVTGH (FD56), ADDH2 (FD60), ADDH3 (FD61), SUBH2 (FD62),
				;3381	;				SUBH3 (FD63), MULH2 (FD64), MULH3 (FD65), DIVH2 (FD66),
				;3382	;				DIVH3 (FD67), CVTHB (FD68), CVTHW (FD69), CVTHL (FD6A),
				;3383	;				CVTRHL (FD6B), CVTBH (FD6C), CVTWH (FD6D), CVTLH (FD6E),
				;3384	;				ACBH (FD6F), MOVH (FD70), CMPH (FD71), MNEGH (FD72),
				;3385	;				TSTH (FD73), EMODH (FD74), POLYH (FD75), CVTHG (FD76),
				;3386	;				CLRO (FD7C), MOVO (FD7D), MOVAO (FD7E), PUSHAO (FD7F),
				;3387	;				CVTFH (FD98)
				;3388	;
				;3389	;	All instructions are dispatched to the reserved instruction fault handler.
				;3390
				;3391	IE.FPD.40..7F:
			    p126;3392		;---------------------------------------; a<7:6> = 01:
E 487  0000,0000,2000,0100 J 100;3393		RESERVED INSTRUCTION FAULT		; [4] all opcodes reserved, fault
				;3394
				;3395	IE.FPD.80..BF:
			    p126;3396		;---------------------------------------; a<7:6> = 10:
E 48B  0000,0000,2000,0100 J 100;3397		RESERVED INSTRUCTION FAULT		; [4] all opcodes reserved, fault
				;3398
;3399	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  113
;    INTEXC.MIC 	     Double Parameter Exceptions -- Memory Management Fault				      /REV=
;															     INTEXC
;3400	.TOC	"	Double Parameter Exceptions -- Memory Management Fault"
;3401
;3402	;	Memory management exceptions push two parameters on the stack:
;3403	;	the virtual address of the faulting access, and a fault type code.
;3404	;
;3405	;	An ACV exception results from an attempt to access a page with
;3406	;	insufficient privilege.
;3407	;
;3408	;	A TNV exception results from an attempt to access a page which
;3409	;	has PTE.V = 0.
;3410	;
;3411	;	A modify fault results from an attempt to write a page which
;3412	;	has PTE.M = 0.
;3413	;
;3414	;	Modify faults are intercepted and handled entirely by the microcode.
;3415	;	ACV and TNV exceptions are faults and cause the current instruction
;3416	;	to be packed up (interruptible instructions) or the instruction stream
;3417	;	to be backed up (all others).  This flow is entered from a memory
;3418	;	management microtrap, or by direct dispatch from PROBEx or CHMx.
;3419	;
;3420	;	Entry conditions (microtrap):
;3421	;		IPR.MMEADR =	fault address
;3422	;		IPR.MMESTS<2> = 0: read reference
;3423	;				1: write reference
;3424	;
;3425	;	Entry conditions (microcode dispatch):
;3426	;		VA = W4 =	fault address
;3427	;		SAVEPC	=	backed up PC
;3428	;		MMGT.MODE =	mode of faulting reference
;3429	;
;3430	;	Preserved resources used:
;3431	;		W4	=	fault address from IPR.MMEADR
;3432	;		W5	=	fault status from IPR.MMESTS
;3433	;
;3434	;	Exit conditions:
;3435	;		Current instruciton has been packed up, or instruction stream backed up.
;3436	;		For modify faults, PTE<M> has been set and the instruction stream restarted.
;3437	;		For ACV or TNV, exception taken through the appropriate vector in the
;3438	;		SCB.  For ACV/TNV, the stack frame is:
;3439	;
;3440	;		+---------------------------------------------------------+-+-+-+-+
;3441	;		|				0			  |A|M|P|L|  fault flags
;3442	;		+---------------------------------------------------------+-+-+-+-+
;3443	;		|				VA				  |  VA of reference which faulted
;3444	;		+-----------------------------------------------------------------+
;3445	;		|				PC				  |
;3446	;		+-----------------------------------------------------------------+
;3447	;		|				PSL				  |
;3448	;		+-----------------------------------------------------------------+
;3449	;
				;3450	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  114
;    INTEXC.MIC 	     Double Parameter Exceptions -- Memory Management Fault				      /REV=
;															     INTEXC
				;3451
				;3452	;	Memory management exception.
				;3453
				;3454	;	Note: IE.CLEANUP.CPU is not called directly from the entry point
				;3455	;	because the MMESTS and MMEADR IPRs must be read before the special
				;3456	;	packup routines are called.  This avoids destroying the IPR state
				;3457	;	in the packup routines.
				;3458
				;3459	IE.MEMMGT..:
				;3460		;*********** Microtrap entry ***********;
				;3461		Q <-- PASSB [PSL.TP]000000,		; mask to clear PSL<TP>
				;3462		RESET CPU,				; abort current operations
				;3463		CALL [WAIT.TWO.CYCLES], 		; wait for RESET CPU to take effect
			    p163;3464							; >> Fbox sync via DST <> NONE
E 018  0002,BA00,2006,22B7 S 2B7;3465			sim exception
				;3466
				;3467		;---------------------------------------;
				;3468		VA <-- K10.[IPR.MMESTS],		; read fault status code
				;3469		[W5] <-- MEM.PR (VA), LONG,		; into W5
E 019  00D4,3D41,1801,0144 J 144;3470			sim addr [k]
				;3471
				;3472		;---------------------------------------;
				;3473		VA <-- K10.[IPR.MMEADR],		; read fault address
			    p159;3474		[W4] <-- MEM.PR (VA), LONG,		; into W4
E 144  00D4,3D01,1401,22D7 S 2D7;3475		CALL [IE.CLEANUP.CPU]			; cleanup CPU state, state<3:0> unchanged
				;3476							; PSL<TP> = 0, SAVEPC = BPC
				;3477
				;3478	;	Note: Do not change the bit position or polarity of the
				;3479	;	MMESTS read/write bit without changing the state bit
				;3480	;	usage at CHMX.PROBEX.MM.FAULT.	They must be the same.
				;3481	;
				;3482	;	Note: The following TBIS can not cause an infinite loop
				;3483	;	in the Mbox because the preceding RESET CPU and read of
				;3484	;	backup PC guarantee that there are no TB miss sequences
				;3485	;	in progress when the command enters the EM latch.
				;3486
				;3487		;---------------------------------------;
				;3488		VA&, [WBUS] <-- [W4], LONG,		; invalidate the TB location
				;3489		TB INVALIDATE SINGLE,			; for the faulting address so that
				;3490							; the probe below misses
				;3491							; >> TB INVALIDATE, implicit sync performed
				;3492		ACCESS B [W5],				; test mmests<2> (read/write bit)
E 145  6010,0031,2050,4BD2 B 1D2;3493		CASE [STATE.5-3] AT [IE.MEMMGT.NEW]	; see if we've been here before
				;3494
				;3495	;= ALIGNLIST 001x	(IE.MEMMGT.NEW, 	IE.MEMMGT.SNV,
				;3496	;=			 IE.MEMMGT.MACH.CHK,	IE.MEMMGT.DOUBLE.ERROR)
				;3497
				;3498	;	STATE<5:4> = 00, new exception.
				;3499	;	Re-probe address to determine if the memory management state
				;3500	;	has changed.
				;3501
				;3502	IE.MEMMGT.NEW:
				;3503		;---------------------------------------; state<5:4> = 00:
			    p115;3504		[MMGT.MODE] <-- ZEXT [RN.MODE.OPCODE] RSH [22.], ; load curmod into mode reg
E 1D2  6001,D67A,D800,43D7 B 1D7;3505		CASE [B.2-0] AT [IE.MEMMGT.R]		; case on modify bit from status
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  115
;    INTEXC.MIC 	     Double Parameter Exceptions -- Memory Management Fault				      /REV=
;															     INTEXC
				;3506
				;3507	;	Memory management fault, continued.
				;3508	;	Entered from above, or as an alternate entry from CHMX.PROBEX.MM.FAULT.
				;3509	;	A RESET CPU must have been done, and the fault address must have been
				;3510	;	invalidated from the TB.  STATE<2> may be set if entered from
				;3511	;	CHMX.PROBEX.MM.FAULT.
				;3512	;
				;3513	;	Due to macropipeline considerations, the state of a faulting page
				;3514	;	may have changed since the original fault was detected.  Therefore,
				;3515	;	the address must be re-probed, and the probe status must be used
				;3516	;	to determine if a fault really exists (the fault may have changed,
				;3517	;	or disappeared).  If the re-probe indicates that a fault still
				;3518	;	exists, the MMESTS value is re-read to build the stack frame.
				;3519	;
				;3520	;	Note: A RESET CPU clears the lock on MMESTS and MMEADR and the
				;3521	;	re-probe loads these registers without locking them again.  MMESTS
				;3522	;	is reread after the probe if the probe status indicates an
				;3523	;	exception condition.
				;3524	;
				;3525	;	At this point,
				;3526	;		VA = W4 =	faulting address
				;3527	;		SAVEPC	=	backed up PC
				;3528	;		MMGT.MODE =	mode of faulting reference
				;3529
				;3530	;= ALIGNLIST 011x	(IE.MEMMGT.R,	IE.MEMMGT.W)
				;3531
				;3532	IE.MEMMGT.R:
				;3533		;---------------------------------------; b<2> = 0 or state<2> = 0:
				;3534		[W2] <-- PROBE.R.MODE (VA),		; re-probe address for read access
E 1D7  005C,0000,0C00,0196 J 196;3535		GOTO [IE.MEMMGT.TEST.PROBE]		; join common flow
				;3536
				;3537	IE.MEMMGT.W:
				;3538		;---------------------------------------; b<2> = 1 or state<2> = 1::
				;3539		[W2] <-- PROBE.W.MODE (VA),		; re-probe address for write access
E 1DF  007C,0000,0C00,0196 J 196;3540		GOTO [IE.MEMMGT.TEST.PROBE]		; re-join common flow
				;3541
				;3542	IE.MEMMGT.TEST.PROBE:
				;3543		;---------------------------------------;
E 196  0000,0018,2000,0231 J 231;3544		ACCESS B [W2]				; test the probe status returned
				;3545
				;3546	;	Note: The following TBIS can not cause an infinite loop
				;3547	;	in the Mbox because the probe status is accessed before the
				;3548	;	command is issued, thereby guaranteeing that no TB miss
				;3549	;	sequence is in progress.
				;3550
				;3551		;---------------------------------------;
				;3552		[WBUS] <-- [W4], LONG,			; test sign bit of faulting address for
				;3553		TB INVALIDATE SINGLE,			; M=0 flow and remove entry from TB
			    p116;3554							; >> TB INVALIDATE, implicit sync performed
E 231  6010,0000,2050,43F1 B 2F1;3555		CASE [B.2-0] AT [IE.MEMMGT.PROBE.OK]	; case on probe status
				;3556
				;3557	;= ALIGNLIST 000x	(IE.MEMMGT.PROBE.OK,	IE.MEMMGT.PROBE.M0,
				;3558	;=			 IE.MEMMGT.PROBE.TNV,	IE.MEMMGT.PROBE.PPTE.TNV,
				;3559	;=			 IE.MEMMGT.PROBE.ACV,	IE.MEMMGT.PROBE.101,
				;3560	;=			 IE.MEMMGT.PROBE.110,	IE.MEMMGT.PROBE.111)
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  116
;    INTEXC.MIC 	     Double Parameter Exceptions -- Memory Management Fault				      /REV=
;															     INTEXC
				;3561
				;3562	;	Memory management fault, continued.
				;3563	;	No fault case.
				;3564	;
				;3565	;	This can happen due to the delay between the time that the
				;3566	;	fault is detected in the Mbox and the time that it is reported
				;3567	;	to the Ebox.  In this instance, the instruction stream is simply
				;3568	;	restarted.
				;3569	;
				;3570	;	At this point,
				;3571	;		SAVEPC	=	backup PC
				;3572
				;3573	IE.MEMMGT.PROBE.OK:
				;3574		;---------------------------------------; b<2:0>=000: no fault
				;3575		[WBUS] <-- [SAVEPC], LONG,		; get backup PC back
				;3576		LOAD PC,				; reload and start instruction
			    p144;3577							; >> LOAD PC: sync required before exit
E 2F1  0024,0000,2280,0271 J 271;3578		GOTO [SYNC.RESTART.IBOX.NO.RETIRE]	; sync with LOAD PC, restart Ibox
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  117
;    INTEXC.MIC 	     Double Parameter Exceptions -- Memory Management Fault				      /REV=
;															     INTEXC
				;3579
				;3580	;	Memory management fault, continued.
				;3581	;	M=0 fault case.
				;3582	;
				;3583	;	To avoid the overhead involved in dispatching modify faults to the
				;3584	;	operating system, microcode handles these events as internal micro-
				;3585	;	modify faults by reading the PTE, setting the M-bit, and writing
				;3586	;	it back to memory.
				;3587	;
				;3588	;	At this point,
				;3589	;		VA = W4 =	faulting address
				;3590	;		MMEPTE	=	virtual or physical PTE address
				;3591	;		SAVEPC	=	backed up PC
				;3592	;		W4<31> tested on Abus during the previous cycle.
				;3593
				;3594	IE.MEMMGT.PROBE.M0:
				;3595		;---------------------------------------; b<2:0>=001: M=0
				;3596		VA <-- K10.[IPR.MMEPTE], LONG,		; read PTE address from Mbox
				;3597		[W2] <-- MEM.PR (VA),			; into W2
E 2F3  E0D4,3D21,0C01,4747 B 247;3598		CASE [A31.BQA.BNZ1] AT [IE.MEMMGT.M0.PX] ; case on VA<31> to separate P0,P1/S0
				;3599
				;3600	;= ALIGNLIST 011x	(IE.MEMMGT.M0.PX,	IE.MEMMGT.M0.S0)
				;3601
				;3602	;	P0 or P1 address: PTE is in system virtual memory.  The read and write
				;3603	;	can only fault due to a TNV or a length violation.  The Mbox must
				;3604	;	have read the same location to generate the M=0 status for the
				;3605	;	PROBE, so the read can fail only if the PTE mapping the PPTE went
				;3606	;	from valid to invalid between the PROBE TB fill and now.  This is
				;3607	;	a software bug in violation of section 4.7, pages 4-28 and 4-29
				;3608	;	of the SRM.  Even if there is a software bug, state<4> is not set at this
				;3609	;	point, so a microtrap will come back in the top, which will dispatch a fault
				;3610	;	thru the SCB vector.  An REI should correctly restart the instruction.
				;3611
				;3612	IE.MEMMGT.M0.PX:
				;3613		;---------------------------------------; a<31>=0: P0, P1 address
				;3614		VA <-- [W2], LONG,			; read PTE from system virtual memory
E 247  0048,0001,0830,019C J 19C;3615		[W1] <-- MEM.NOCHK (VA) 		; with no access check
				;3616
				;3617		;---------------------------------------;
				;3618		MEM.NOCHK (VA)&,			; re-write PTE with M bit set
			    p116;3619		[WBUS] <-- [W1] OR [PTE.M]000000, LONG, ; and exit thru no-fault flow
E 19C  0568,3820,2020,02F1 J 2F1;3620		GOTO [IE.MEMMGT.PROBE.OK]		; restart instruction stream
				;3621
				;3622	;	S0 address: PTE is in physical memory
				;3623
				;3624	IE.MEMMGT.M0.S0:
				;3625		;---------------------------------------; a<31>=1: S0 address
				;3626		VA <-- [W2], LONG,			; read PTE from physical memory
E 24F  0050,0001,0830,01A4 J 1A4;3627		[W1] <-- MEM.PHYS (VA)			;
				;3628
				;3629		;---------------------------------------;
				;3630		MEM.PHYS (VA)&, 			; re-write PTE with M bit set
			    p116;3631		[WBUS] <-- [W1] OR [PTE.M]000000, LONG, ; and exit thru no-fault flow
E 1A4  0570,3820,2020,02F1 J 2F1;3632		GOTO [IE.MEMMGT.PROBE.OK]		; restart instruction stream
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  118
;    INTEXC.MIC 	     Double Parameter Exceptions -- Memory Management Fault				      /REV=
;															     INTEXC
				;3633
				;3634	;	Memory management fault, continued.
				;3635	;	TNV and ACV fault cases.
				;3636	;
				;3637	;	At this point,
				;3638	;		VA = W4 =	faulting address
				;3639	;		MMESTS	=	fault status
				;3640	;		SAVEPC	=	backed up PC
				;3641
				;3642	IE.MEMMGT.PROBE.TNV:
				;3643		;---------------------------------------; b<2:0>=010: TNV
				;3644		[W2] <-- [SCBB] + 000000[SCB.TNV],	; get SCB offset for TNV fault
E 2F5  0880,2120,0E60,01BF J 1BF;3645		GOTO [IE.MEMMGT.ACV.TNV]		; join common flows
				;3646
				;3647	IE.MEMMGT.PROBE.PPTE.TNV:
				;3648		;---------------------------------------; b<2:0>=011: PPTE TNV
				;3649		[W2] <-- [SCBB] + 000000[SCB.TNV],	; get SCB offset for TNV fault
E 2F7  0880,2120,0E60,01BF J 1BF;3650		GOTO [IE.MEMMGT.ACV.TNV]		; join common flows
				;3651
				;3652	IE.MEMMGT.PROBE.ACV:
				;3653		;---------------------------------------; b<2:0>=100: ACV
				;3654		[W2] <-- [SCBB] + 000000[SCB.ACV],	; get SCB offset for ACV fault
E 2F9  0880,2100,0E60,01BF J 1BF;3655		GOTO [IE.MEMMGT.ACV.TNV]		; join common flows
				;3656
				;3657	IE.MEMMGT.ACV.TNV:
				;3658		;---------------------------------------;
				;3659		VA <-- K10.[IPR.MMESTS],		; read fault status code
				;3660		[W5] <-- MEM.PR (VA), LONG,		; into E-box
E 1BF  00D4,3D41,1801,01C9 J 1C9;3661			sim addr [k]
				;3662
				;3663		;---------------------------------------;
				;3664		VA <-- [W2],				; get SCB vector address
				;3665		[W1] <-- MEM.SCB (VA), LONG,		; and read vector
E 1C9  0050,0001,0830,01CE J 1CE;3666			sim addr [scb]
				;3667
				;3668		;---------------------------------------;
E 1CE  0400,2038,1860,0274 J 274;3669		[W5] <-- [W5] AND 000000[07], LONG	; mask parameter to 3 bits
				;3670
				;3671		;---------------------------------------;
				;3672		[W2] <-- [PSL], LONG,			; save current PSL
				;3673		STATE.4 <-- 1,				; flag start of exception
				;3674		STATE.3-0 <-- 0,			; clear other state flags
			    p153;3675							; >> no state<3> restriction after RESET CPU
E 274  1001,C000,0CC8,2311 S 311;3676		CALL [IE.EXCEPTION]			; call exception handling routine
				;3677
				;3678		;---------------------------------------;
				;3679		VA <-- [VA] - 4,			; decrement stack for a push
			    p124;3680		MEM (VA)&, [WBUS] <-- PASSB [W4], LONG, ; push address in page on stack
E 275  0CE4,802B,20B0,027D J 27D;3681		GOTO [IE.PUSH.W5.EXIT]			; go push W5 on stack and exit
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  119
;    INTEXC.MIC 	     Double Parameter Exceptions -- Memory Management Fault				      /REV=
;															     INTEXC
				;3682
				;3683	;	Memory management fault, continued.
				;3684	;	Illegal probe status cases.
				;3685
				;3686	IE.MEMMGT.PROBE.101:
			    p135;3687		;---------------------------------------; b<2:0>=101:
E 2FB  0080,3008,A400,0038 J 038;3688		MACHINE CHECK [MCHK.UNKNOWN.MSTATUS]	; initiate machine check
				;3689
				;3690	IE.MEMMGT.PROBE.110:
			    p135;3691		;---------------------------------------; b<2:0>=110:
E 2FD  0080,3008,A400,0038 J 038;3692		MACHINE CHECK [MCHK.UNKNOWN.MSTATUS]	; initiate machine check
				;3693
				;3694	IE.MEMMGT.PROBE.111:
			    p135;3695		;---------------------------------------; b<2:0>=111:
E 2FF  0080,3008,A400,0038 J 038;3696		MACHINE CHECK [MCHK.UNKNOWN.MSTATUS]	; initiate machine check
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  120
;    INTEXC.MIC 	     Double Parameter Exceptions -- Memory Management Fault				      /REV=
;															     INTEXC
				;3697
				;3698	;	Memory management fault continued.
				;3699	;	Nested memory management fault within exception flows (STATE<5:4> neq 00).
				;3700
				;3701	;	STATE<5:4> = 01, memory management fault while writing to kernel or interrupt stack.
				;3702	;		Initiate kernel stack not valid exception (kernel stack)
				;3703	;		or interrupt stack not valid console restart (interrupt stack).
				;3704
				;3705	;	The PSL<is> bit is updated in IE.INTERRUPT/IE.EXCEPTION before any virtual
				;3706	;	stack writes are attempted and is therefore valid at this point.
				;3707
				;3708	IE.MEMMGT.SNV:
				;3709		;---------------------------------------; state<5:4> = 01:
				;3710		STATE.5 <-- 1,				; set state<5>
				;3711		STATE.3-0 <-- 0,			; clear state<3:0>
			    p130;3712							; >> no state<3> restriction after RESET CPU
E 1D6  B002,0000,2008,4DB6 B 1B6;3713		CASE [PSL.26-24] AT [IE.KSNV]		; case on PSL<is>
				;3714
				;3715	;= ALIGNLIST 011x	(IE.KSNV,	IE.ISNV)
				;3716
				;3717	IE.ISNV:
			    p.84;3718		;---------------------------------------; psl<is> = 1:
E 1BE  0500,2820,A4C0,0035 J 035;3719		CONSOLE HALT NO CLEANUP [ERR.INTSTK]	; interrupt stack not valid, invoke console
				;3720							; >> string packup possible, no cleanup
				;3721							; >> may be done
				;3722
				;3723	;	STATE<5:4> = 10, memory management fault while inside the machine check flows.
				;3724	;		This is not recoverable, force a console restart.
				;3725
				;3726	IE.MEMMGT.MACH.CHK:
			    p.84;3727		;---------------------------------------; state<5:4> = 10:
E 1DA  0500,2880,A4C0,0034 J 034;3728		CONSOLE HALT [ERR.IE0]			; ACV/TNV in machine check, invoke console
				;3729
				;3730	;	STATE<5:4> = 11, memory management fault while inside the kernel stack not valid flows.
				;3731	;		This is not recoverable, force a console restart.
				;3732
				;3733	IE.MEMMGT.DOUBLE.ERROR:
			    p.84;3734		;---------------------------------------; state<5:4> = 11:
E 1DE  0500,2888,A4C0,0034 J 034;3735		CONSOLE HALT [ERR.IE1]			; ACV/TNV in ker stk invalid, invoke console
				;3736
;3737	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  121
;    INTEXC.MIC 	     Single Parameter Exceptions -- Arithmetic Traps and Faults 			      /REV=
;															     INTEXC
;3738	.TOC	"	Single Parameter Exceptions -- Arithmetic Traps and Faults"
;3739
;3740	;	These arithmetic exceptions push one parameter on the stack:
;3741	;	the trap/fault type code.
;3742	;
;3743	;	Arithmetic traps result from arithmetic errors in integer instructions,
;3744	;	and from a subscript range error in INDEX.
;3745	;
;3746	;	Arithmetic faults result from arithmetic errors in floating point
;3747	;	instructions.
;3748	;
;3749	;	Arithmetic traps only occur after instructions; arithmetic faults
;3750	;	occur in mid instruction.  Because of the macro-pipeline, both require
;3751	;	the instruction stream to be backed up;  however, traps preserve
;3752	;	PSL<tp>, while faults clear PSL<tp>.
;3753	;
;3754	;	The arithmetic traps are reached from normal execution flows or
;3755	;	via an integer overflow microtrap.
;3756	;
;3757	;	The arithmetic faults are reached from floating execution flows
;3758	;	via a floating condition microtrap.
;3759	;
;3760	;	Entry conditions (integer overflow trap, floating faults):
;3761	;		none
;3762	;
;3763	;	Entry conditions (subscript, divide by zero traps):
;3764	;		instruction explicitly retired
;3765	;
;3766	;	Preserved resources used:
;3767	;		W5	=	fault or trap code
;3768	;
;3769	;	Exit conditions:
;3770	;		Instruction stream has been backed up.
;3771	;		Exception taken through arithmetic exception vector in SCB.
;3772	;		Stack frame:
;3773	;
;3774	;		+-----------------------------------------------------------------+
;3775	;		|		ARITH.FAULT.xxx or ARITH.TRAP.xxx		  |  fault or trap code
;3776	;		+-----------------------------------------------------------------+
;3777	;		|				PC				  |
;3778	;		+-----------------------------------------------------------------+
;3779	;		|				PSL				  |
;3780	;		+-----------------------------------------------------------------+
;3781	;
				;3782	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  122
;    INTEXC.MIC 	     Single Parameter Exceptions -- Arithmetic Traps and Faults 			      /REV=
;															     INTEXC
				;3783
				;3784	;	Integer overflow trap.
				;3785	;	Entered by microtrap after last microinstruction of current instruction
				;3786	;	completes.  All resources available.
				;3787
				;3788	IE.INT.OVERFLOW..:
				;3789		;*********** Microtrap entry ***********;
				;3790		Q <-- 0,				; no PSL bits to clear
				;3791		RESET CPU,				; abort current operations
				;3792		CALL [IE.CLEANUP.CPU.NO.PACKUP],	; cleanup CPU state, state<3:0> = 0
				;3793							; PSL<TP> unchanged, SAVEPC = BPC
			    p159;3794							; >> Fbox sync via DST <> NONE
E 008  0002,C000,2006,22D5 S 2D5;3795			sim exception
				;3796
				;3797		;---------------------------------------;
			    p124;3798		[W5] <-- 000000[ARITH.TRAP.INTOVF], LONG, ; get proper trap code
E 009  0080,2008,1800,01D3 J 1D3;3799		GOTO [IE.ARITH.COMMON]			; join common code
				;3800
				;3801
				;3802	;	Subscript range trap.
				;3803	;	Entered from INDEX flows, all resources available, INDEX instruction retired.
				;3804
				;3805	IE.SUBSCRIPT.ERROR..:
				;3806		;---------------------------------------;
				;3807		Q <-- 0,				; no PSL bits to clear
				;3808		RESET CPU,				; abort current operations
				;3809		CALL [IE.CLEANUP.CPU.NO.PACKUP],	; cleanup CPU state, state<3:0> = 0
				;3810							; PSL<TP> unchanged, SAVEPC = BPC
			    p159;3811							; >> Fbox sync via DST <> NONE
E 044  0002,C000,2006,22D5 S 2D5;3812			sim exception
				;3813
				;3814		;---------------------------------------;
			    p124;3815		[W5] <-- 000000[ARITH.TRAP.SUBRNG], LONG,; get trap code
E 045  0080,2038,1800,01D3 J 1D3;3816		GOTO [IE.ARITH.COMMON]			; join common code
				;3817
				;3818
				;3819	;	Divide by zero trap.
				;3820	;	Entered from DIVIn, EDIV flows, all resources available, divide instruction retired.
				;3821
				;3822	IE.DIVIDE.ERROR..:
				;3823		;---------------------------------------;
				;3824		Q <-- 0,				; no PSL bits to clear
				;3825		RESET CPU,				; abort current operations
				;3826		CALL [IE.CLEANUP.CPU.NO.PACKUP],	; cleanup CPU state, state<3:0> = 0
				;3827							; PSL<TP> unchanged, SAVEPC = BPC
			    p159;3828							; >> Fbox sync via DST <> NONE
E 048  0002,C000,2006,22D5 S 2D5;3829			sim exception
				;3830
				;3831		;---------------------------------------;
			    p124;3832		[W5] <-- 000000[ARITH.TRAP.INTDIV], LONG,; get trap code
E 049  0080,2010,1800,01D3 J 1D3;3833		GOTO [IE.ARITH.COMMON]			; join common code
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  123
;    INTEXC.MIC 	     Single Parameter Exceptions -- Arithmetic Traps and Faults 			      /REV=
;															     INTEXC
				;3834
				;3835	;	Floating overflow fault.
				;3836	;	Entered by microtrap from faulting Fbox instruction.
				;3837
				;3838	;	At this point:
				;3839	;		FBOX.CONDITION<2:1> =	encoded Fbox fault code
				;3840
				;3841	IE.FLT.FAULT..:
				;3842		;*********** Microtrap entry ***********;
				;3843		Q <-- PASSB [PSL.TP]000000,		; mask to clear PSL<TP>
				;3844		RESET CPU,				; abort current operations
				;3845		CALL [IE.CLEANUP.CPU.NO.PACKUP],	; cleanup CPU state, state<3:0> = 0
				;3846							; PSL<TP> = 0, SAVEPC = BPC
			    p159;3847							; >> Fbox sync via DST <> NONE
E 020  0002,BA00,2006,22D5 S 2D5;3848			sim exception
				;3849
				;3850		;---------------------------------------;
E 021  2000,0000,2000,5102 B 002;3851		CASE [FBOX.CONDITION] AT [IE.FLT.RSVD.OPERAND] ; case on fault code
				;3852
				;3853	;= ALIGNLIST 001x	(IE.FLT.RSVD.OPERAND,	IE.FLT.DIVIDE.ZERO,
				;3854	;=			 IE.FLT.OVERFLOW,	IE.FLT.UNDERFLOW)
				;3855
				;3856	IE.FLT.RSVD.OPERAND:
				;3857		;---------------------------------------; b<1:0> = 00: reserved operand
				;3858		VA <-- [SCBB] + 000000[SCB.RESOP],	; offset into SCB for reserved operand
				;3859		[W1] <-- MEM.SCB (VA), LONG,		; read SCB vector
			    p129;3860		GOTO [IE.FAULT.COMMON], 		; join common code
E 002  08D0,20C1,0A60,0286 J 286;3861			sim addr [scb]
				;3862
				;3863	IE.FLT.DIVIDE.ZERO:
				;3864		;---------------------------------------; b<1:0> = 01: divide by zero
			    p124;3865		[W5] <-- 000000[ARITH.FAULT.FLTDIV], LONG, ; get proper fault code
E 006  0080,2048,1800,01D3 J 1D3;3866		GOTO [IE.ARITH.COMMON]			; join common code
				;3867
				;3868	IE.FLT.OVERFLOW:
				;3869		;---------------------------------------; b<1:0> = 10: floating overflow
			    p124;3870		[W5] <-- 000000[ARITH.FAULT.FLTOVF], LONG, ; get proper fault code
E 00A  0080,2040,1800,01D3 J 1D3;3871		GOTO [IE.ARITH.COMMON]			; join common code
				;3872
				;3873	IE.FLT.UNDERFLOW:
				;3874		;---------------------------------------; b<1:0> = 10: floating underflow
			    p124;3875		[W5] <-- 000000[ARITH.FAULT.FLTUND], LONG, ; get proper fault code
E 00E  0080,2050,1800,01D3 J 1D3;3876		GOTO [IE.ARITH.COMMON]			; join common code
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  124
;    INTEXC.MIC 	     Single Parameter Exceptions -- Arithmetic Traps and Faults 			      /REV=
;															     INTEXC
				;3877
				;3878	;	Common exit points for arithmetic traps and floating point faults.
				;3879
				;3880	;	At this point,
				;3881	;		W5	=	fault or trap code
				;3882	;		SAVEPC	=	backed up PC
				;3883
				;3884	IE.ARITH.COMMON:
				;3885		;---------------------------------------;
				;3886		VA <-- [SCBB] + 000000[SCB.ARITH],	; get SCB offset for arithmetic exception
				;3887		[W1] <-- MEM.SCB (VA), LONG,		; read SCB vector
E 1D3  08D0,21A1,0A60,027C J 27C;3888			sim addr [scb]
				;3889
				;3890		;---------------------------------------;
				;3891		[W2] <-- [PSL], LONG,			; save current PSL
				;3892		STATE.4 <-- 1,				; flag start of exception
				;3893		STATE.3-0 <-- 0,			; clear other state flags
			    p153;3894							; >> no state<3> restriction after RESET CPU
E 27C  1001,C000,0CC8,2311 S 311;3895		CALL [IE.EXCEPTION]			; call exception handling routine
				;3896
				;3897	IE.PUSH.W5.EXIT:
				;3898		;---------------------------------------;
				;3899		VA <-- [VA] - 4,			; decrement stack for a push
			    p151;3900		MEM (VA)&, [WBUS] <-- PASSB [W5], LONG, ; push parameter on stack
E 27D  0CE4,8033,20B0,02AB J 2AB;3901		GOTO [IE.LOAD.PC]			; load pc and exit from flows
				;3902
;3903	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  125
;    INTEXC.MIC 	     Zero Parameter Exceptions -- Reserved Inst, Addr, Operand; Suspended Vector; Trace; KSNV /REV=
;															     INTEXC
;3904	.TOC	"	Zero Parameter Exceptions -- Reserved Inst, Addr, Operand; Suspended Vector; Trace; KSNV"
;3905
;3906	;	These instruction-related exceptions push no parameters on the stack:
;3907	;	the SCB vector provides sufficient information to process the exception.
;3908	;
;3909	;	A reserved instruction fault results from processing an undefined or
;3910	;	privileged instruction.
;3911	;
;3912	;	A reserved addressing mode fault results from processing an undefined or
;3913	;	reserved addressing mode.
;3914	;
;3915	;	A reserved operand fault results from processing an invalid operand in an
;3916	;	instruction.
;3917	;
;3918	;	A suspended vector faults results from issuing a vector instruction to
;3919	;	a suspended vector unit.
;3920	;
;3921	;	A trace trap occurs if TP is set at execution dispatch.
;3922	;
;3923	;	A kernel stack not valid abort results from an ACV or TNV microtrap inside
;3924	;	an exception.
;3925	;
;3926	;	Except for kernel stack not valid, which only occurs inside another exception,
;3927	;	these exceptions causes the the currently executing instruction to be packed up
;3928	;	(interruptible instructions) or the instruction stream to be backed up (all others).
;3929	;
;3930	;	This code is also used by XFC and BPT.
;3931	;
;3932	;	Entry conditions:
;3933	;		none
;3934	;
;3935	;	Preserved resources used:
;3936	;		none
;3937	;
;3938	;	Exit conditions:
;3939	;		Current instruction has been packed up, or instruction stream backed up.
;3940	;		Exception taken through specified vector in SCB.  Stack frame:
;3941	;
;3942	;		+-----------------------------------------------------------------+
;3943	;		|				PC				  |
;3944	;		+-----------------------------------------------------------------+
;3945	;		|				PSL				  |
;3946	;		+-----------------------------------------------------------------+
;3947	;
				;3948	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  126
;    INTEXC.MIC 	     Zero Parameter Exceptions -- Reserved Inst, Addr, Operand; Suspended Vector; Trace; KSNV /REV=
;															     INTEXC
				;3949
				;3950	;	Reserved instruction fault.
				;3951	;	Entered by I-box initial dispatch with the I-box suspended or
				;3952	;	from execution flows via the RESERVED INSTRUCTION FAULT macro.
				;3953
				;3954	RSVD.OPCODE..:
				;3955		;********** Hardware dispatch **********;
				;3956		Q <-- PASSB [PSL.TP]000000,		; mask to clear PSL<TP>
				;3957		RESET CPU,				; abort current operations
				;3958		CALL [IE.CLEANUP.CPU.NO.PACKUP],	; cleanup CPU state, state<3:0> = 0
				;3959							; PSL<TP> = 0, SAVEPC = BPC
			    p159;3960							; >> Fbox sync via DST <> NONE
E 100  0002,BA00,2006,22D5 S 2D5;3961			sim rsvd opcode
				;3962
				;3963		;---------------------------------------;
				;3964		VA <-- [SCBB] + 000000[SCB.RESPRIV],	; offset into SCB for reserved instruction
				;3965		[W1] <-- MEM.SCB (VA), LONG,		; read SCB vector
			    p129;3966		GOTO [IE.FAULT.COMMON], 		; join common code
E 101  08D0,2081,0A60,0286 J 286;3967			sim addr [scb]
				;3968
				;3969
				;3970	;	Reserved instruction fault.
				;3971	;	Entered by microtrap when a floating point instruction is
				;3972	;	dispatched and the Fbox is disabled.
				;3973
				;3974	IE.RSVD.OPCODE.TRAP..:
				;3975		;********** Hardware dispatch **********;
				;3976		Q <-- PASSB [PSL.TP]000000,		; mask to clear PSL<TP>
				;3977		RESET CPU,				; abort current operations
				;3978		CALL [IE.CLEANUP.CPU.NO.PACKUP],	; cleanup CPU state, state<3:0> = 0
				;3979							; PSL<TP> = 0, SAVEPC = BPC
			    p159;3980							; >> Fbox sync via DST <> NONE
E 010  0002,BA00,2006,22D5 S 2D5;3981			sim rsvd opcode
				;3982
				;3983		;---------------------------------------;
				;3984		VA <-- [SCBB] + 000000[SCB.RESPRIV],	; offset into SCB for reserved instruction
				;3985		[W1] <-- MEM.SCB (VA), LONG,		; read SCB vector
			    p129;3986		GOTO [IE.FAULT.COMMON], 		; join common code
E 011  08D0,2081,0A60,0286 J 286;3987			sim addr [scb]
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  127
;    INTEXC.MIC 	     Zero Parameter Exceptions -- Reserved Inst, Addr, Operand; Suspended Vector; Trace; KSNV /REV=
;															     INTEXC
				;3988
				;3989	;	Reserved addressing mode fault.
				;3990	;	Entered by microtrap.
				;3991
				;3992	IE.RSVD.ADDRESS..:
				;3993		;********** Hardware dispatch **********;
				;3994		Q <-- PASSB [PSL.TP]000000,		; mask to clear PSL<TP>
				;3995		RESET CPU,				; abort current operations
				;3996		CALL [IE.CLEANUP.CPU.NO.PACKUP],	; cleanup CPU state, state<3:0> = 0
				;3997							; PSL<TP> = 0, SAVEPC = BPC
			    p159;3998							; >> Fbox sync via DST <> NONE
E 01C  0002,BA00,2006,22D5 S 2D5;3999			sim exception
				;4000
				;4001		;---------------------------------------;
				;4002		VA <-- [SCBB] + 000000[SCB.RESADD], LONG, ; offset into SCB for reserved addressing mode
				;4003		[W1] <-- MEM.SCB (VA), LONG,		; read SCB vector
			    p129;4004		GOTO [IE.FAULT.COMMON], 		; join common code
E 01D  08D0,20E1,0A60,0286 J 286;4005			sim addr [scb]
				;4006
				;4007
				;4008	;	Reserved operand fault.
				;4009	;	Entered from execution flows via the RESERVED OPERAND FAULT
				;4010	;	macro.
				;4011
				;4012	IE.RSVD.OPERAND..:
				;4013		;---------------------------------------;
				;4014		Q <-- PASSB [PSL.TP]000000,		; mask to clear PSL<TP>
				;4015		RESET CPU,				; abort current operations
				;4016		CALL [IE.CLEANUP.CPU],			; cleanup CPU state, state<3:0> unchanged
				;4017							; PSL<TP> = 0, SAVEPC = BPC
			    p159;4018							; >> Fbox sync via DST <> NONE
E 03C  0002,BA00,2006,22D7 S 2D7;4019			sim exception
				;4020
				;4021		;---------------------------------------;
				;4022		VA <-- [SCBB] + 000000[SCB.RESOP], LONG, ; offset into SCB for reserved operand
			    p129;4023		[W1] <-- MEM.SCB (VA), LONG,		; read SCB vector
E 03D  08D0,20C1,0A60,0286 J 286;4024		GOTO [IE.FAULT.COMMON]			; join common code
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  128
;    INTEXC.MIC 	     Zero Parameter Exceptions -- Reserved Inst, Addr, Operand; Suspended Vector; Trace; KSNV /REV=
;															     INTEXC
				;4025
				;4026	;	Trace trap.
				;4027	;	Entered by microsequencer initial dispatch.
				;4028
				;4029	IE.TRACE.TRAP..:
				;4030		;********** Hardware dispatch **********;
				;4031		Q <-- PASSB [PSL.TP]000000,		; mask to clear PSL<TP>
				;4032		RESET CPU,				; abort current operations
				;4033		CALL [IE.CLEANUP.CPU.NO.PACKUP],	; cleanup CPU state, state<3:0> = 0
				;4034							; PSL<TP> = 0, SAVEPC = BPC
			    p159;4035							; >> Fbox sync via DST <> NONE
E 028  0002,BA00,2006,22D5 S 2D5;4036			sim exception
				;4037
				;4038		;---------------------------------------;
				;4039		VA <-- [SCBB] + 000000[SCB.TP], 	; offset into SCB for trace trap
				;4040		[W1] <-- MEM.SCB (VA), LONG,		; read SCB vector
			    p129;4041		GOTO [IE.FAULT.COMMON], 		; join common code
E 029  08D0,2141,0A60,0286 J 286;4042			sim addr [scb]
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  129
;    INTEXC.MIC 	     Zero Parameter Exceptions -- Reserved Inst, Addr, Operand; Suspended Vector; Trace; KSNV /REV=
;															     INTEXC
				;4043
				;4044	;	Common zero parameter fault/trap flows.
				;4045	;
				;4046	;	At this point,
				;4047	;		W1	=	SCB vector (read in progress)
				;4048	;		SAVEPC	=	backed up PC
				;4049
				;4050	IE.FAULT.COMMON:
				;4051		;---------------------------------------;
				;4052		[W2] <-- [PSL], LONG,			; save current PSL
				;4053		STATE.4 <-- 1,				; flag start of exception
				;4054		STATE.3-0 <-- 0,			; clear other state flags
			    p153;4055							; >> no state<3> restriction after RESET CPU
E 286  1001,C000,0CC8,2311 S 311;4056		CALL [IE.EXCEPTION]			; call exception handling routine
				;4057
				;4058		;---------------------------------------;
				;4059		[WBUS] <-- [W1] ANDNOT 000000[3], LONG, ; Wbus <-- vector with bits<1:0> = 00
				;4060		LOAD PC,				; load new PC, restart prefetching
			    p151;4061							; >> LOAD PC: sync required before exit
E 287  04A4,2018,2020,02CD J 2CD;4062		GOTO [IE.UPDATE.SP]			; update sp and exit
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  130
;    INTEXC.MIC 	     Zero Parameter Exceptions -- Reserved Inst, Addr, Operand; Suspended Vector; Trace; KSNV /REV=
;															     INTEXC
				;4063
				;4064	;	Kernel stack not valid abort.
				;4065	;	Entered from ACV/TNV exceptions flows.
				;4066
				;4067	;	At this point,
				;4068	;		W2	=	original PSL
				;4069	;		SAVEPC	=	old PC
				;4070	;		STATE<5:0> =	110000
				;4071
				;4072	;	IE.MEMMGT guarantees reset of the CPU.
				;4073
				;4074	IE.KSNV:
				;4075		;---------------------------------------; psl<is> = 0:
				;4076		VA <-- [SCBB] + 000000[SCB.KSNV],	; offset into SCB for kernel stack not valid
				;4077		[W1] <-- MEM.SCB (VA), LONG,		; read SCB vector
				;4078		STATE.3-0 <-- 0,			; clear other state flags
				;4079							; >> no state<3> restriction after RESET CPU
			    p153;4080		CALL [IE.EXCEPTION],			; call exception handling routine
E 1B6  08D0,2041,0A68,2311 S 311;4081			sim addr [scb]
				;4082
				;4083		;---------------------------------------;
				;4084		[WBUS] <-- [W1] ANDNOT 000000[3], LONG, ; Wbus <-- vector with bits<1:0> = 00
				;4085		LOAD PC,				; load new PC, restart prefetching
			    p151;4086							; >> LOAD PC: sync required before exit
E 1B7  04A4,2018,2020,02CD J 2CD;4087		GOTO [IE.UPDATE.SP]			; update sp and exit
				;4088
;4089	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  131
;    INTEXC.MIC 	     Hardware Error									      /REV=
;															     INTEXC
;4090	.TOC	"	Hardware Error"
;4091
;4092	;	These conditions represent hardware errors.
;4093	;
;4094	;	Asynchronous hardware errors are those that are detected and reported
;4095	;	asynchronously with respect to the instruction flow in the Ebox.  At
;4096	;	present, there are two such errors:
;4097	;
;4098	;		Ebox S3 stall timeout: The Ebox contains a very long counter
;4099	;		that counts as long as the Ebox is in an S3 stall (or an S4 stall,
;4100	;		which causes an S3 stall).  If the counter reaches its maximum
;4101	;		value, a microtrap is requested.  This can happen if some other
;4102	;		internal error causes the Ebox to get out of sync with one of
;4103	;		the queues, causing an infinite stall.
;4104	;
;4105	;		Mbox TB parity error: If the Mbox detects a parity error on the
;4106	;		TB, a microtrap is requested.
;4107	;
;4108	;	Synchronous hardware errors are those that are reported synchronously
;4109	;	with respect to the instruction flow in the Ebox.  An example of such
;4110	;	an error is a cache or memory error on an instruction operand.	This
;4111	;	event is reported via the error bits in the MD file, and a microtrap
;4112	;	is requested when the microword that references this location advances
;4113	;	to S4.
;4114	;
;4115	;	Entry conditions:
;4116	;		none
;4117	;
;4118	;	Exit conditions:
;4119	;		Machine check
;4120	;
;4121	;	Preserved resources used:
;4122	;		See machine check flow
				;4123	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  132
;    INTEXC.MIC 	     Hardware Error									      /REV=
;															     INTEXC
				;4124
				;4125	;	Asynchronous hardware error.
				;4126	;	Entered by microtrap.
				;4127	;
				;4128	;	S3 stall timeout, which is one of two events which forces this microtrap,
				;4129	;	asserts a special reset signal for 18 cycles to the Mbox and Cbox.  Because
				;4130	;	of this assertion the microcode must not make any Mbox request during this
				;4131	;	interval.  This restriction is enforced by simply waiting out the assertion
				;4132	;	before entering the machine check flow.  Note that the value 23 is used
				;4133	;	because it was the most conventient value provided by the nested routines
				;4134	;	which was above the required value of 18.
				;4135
				;4136	IE.ASYNC.HW.ERROR..:
				;4137		;*********** Microtrap entry ***********;
			    p163;4138		RESET CPU,				; clear out Ibox and Mbox
E 004  0000,0000,2006,22B4 S 2B4;4139		CALL [WAIT.23.CYCLES]			; add required delay
				;4140
			    p135;4141		;---------------------------------------;
E 005  0080,3028,A400,0038 J 038;4142		MACHINE CHECK [MCHK.ASYNC.ERROR]	; initiate machine check
				;4143
				;4144	;	Synchronous harware error.
				;4145	;	Entered by microtrap.
				;4146
				;4147	IE.SYNC.HW.ERROR..:
			    p135;4148		;*********** Microtrap entry ***********;
E 014  0080,3030,A400,0038 J 038;4149		MACHINE CHECK [MCHK.SYNC.ERROR] 	; initiate machine check
				;4150
;4151	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  133
;    INTEXC.MIC 	     Machine Check Exception								      /REV=
;															     INTEXC
;4152	.TOC	"	Machine Check Exception"
;4153
;4154	;	This exception represents a system error.  Depending on the type
;4155	;	of error, the setting of the VAX restart bit, and other conditions,
;4156	;	the current process may be restartable, it may have to be stopped,
;4157	;	or the operating system may have to be stopped.
;4158	;
;4159	;	A machine check results from an internally detected consistency error,
;4160	;	eg, microcode reaches an "impossible" state, or an externally detected
;4161	;	hardware error, e.g., memory parity.
;4162	;
;4163	;	A machine check is technically an ABORT.  The current instruction is unwound,
;4164	;	but there is no guarantee that the instruction can be properly restarted.
;4165	;	As much diagnostic information as possible is pushed on the stack, and the
;4166	;	rest is left to the operating system.
;4167	;
;4168	;	There is one condition in which case the PC pushed on the stack may not be
;4169	;	correct.  This occurs if a PTE read error is detected on an Ebox reference
;4170	;	in the middle of an interruptable instruction.	In this instance, PC may point
;4171	;	at the instruction FOLLOWING the interruptable instruction, and the SAVPC value
;4172	;	pushed on the stack may point at the instruction.  This condition is denoted
;4173	;	by the fact that PSL<FPD> is set, and the error registers indicate that a
;4174	;	PTE read error occurred.
;4175	;
;4176	;	Entry conditions:
;4177	;		SAVEPSL =	fault code
;4178	;		STATE<5> =	1 if inside ksnv or machine check flows
;4179	;		STATE<4> =	1 if inside exception flows
;4180	;
;4181	;	Preserved resources used:
;4182	;		W4	=	saved Q
;4183	;		W5	=	saved VA
;4184	;
;4185	;	Exit conditions:
;4186	;		Exception taken through machine check vector in SCB.
;4187	;		Stack frame:
;4188	;
;4189	;		+-----------------------------------------------------------------+
;4190	;		|			    00000n (HEX)			  |  byte count
;4191	;		+-----------------------------------------------------------------+
;4192	;		|ASTLVL|	 |   MC code	|		 |	CPUID	  |
;4193	;		+-----------------------------------------------------------------+
;4194	;		|			      INT.SYS				  |
;4195	;		+-----------------------------------------------------------------+
;4196	;		|			      SAVEPC				  |
;4197	;		+-----------------------------------------------------------------+
;4198	;		|				VA				  |
;4199	;		+-----------------------------------------------------------------+
;4200	;		|				 Q				  |
;4201	;		+-----------------------------------------------------------------+
;4202	;		|			   RN.MODE.OPCODE			  |
;4203	;		+-----------------------------------------------------------------+
;4204	;		|				PC				  |  backed-up PC
;4205	;		+-----------------------------------------------------------------+
;4206	;		|				PSL				  |  PSL at time of fault
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  134
;    INTEXC.MIC 	     Machine Check Exception								      /REV=
;															     INTEXC
;4207	;		+-----------------------------------------------------------------+
;4208
				;4209	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  135
;    INTEXC.MIC 	     Machine Check Exception								      /REV=
;															     INTEXC
				;4210
				;4211	;	Machine check exception.
				;4212	;	Build stack frame and dispatch through machine check vector.
				;4213	;
				;4214	;	NOTE: SAVEPC is preserved for one particular error case.  See the brief
				;4215	;	description above and the full description in the error handling chapter
				;4216	;	of the design spec.
				;4217
				;4218	IE.MACHINE.CHECK..:
				;4219		;---------------------------------------;
				;4220		RESET CPU,				; abort current operations
				;4221		[ASTLVL] <-- [ASTLVL] ANDNOT 00[0FF]0000, ; Make room for machine check code
				;4222		CALL [WAIT.TWO.CYCLES], 		; wait for RESET to take effect
			    p163;4223							; >> Fbox sync via DST <> NONE
E 038  0480,37F8,9656,22B7 S 2B7;4224			sim exception
				;4225
				;4226		;---------------------------------------;
				;4227		[W4] <-- B [Q], 			; save Q around call
E 039  0082,4050,1690,01F2 J 1F2;4228		Q <-- PASSA [SAVEPSL]			; move MC code to Q
				;4229
				;4230		;---------------------------------------;
E 1F2  0500,0050,9650,01FA J 1FA;4231		[ASTLVL] <-- [ASTLVL] OR [Q]		; Combine ASTLVL and MC code
				;4232
				;4233		;---------------------------------------;
				;4234		[W5] <-- [VA], LONG,			; save VA around call
E 1FA  1001,0000,18B0,0263 J 263;4235		FLUSH BRANCH PREDICTION TABLE		; flush branch prediction table
				;4236
				;4237		;---------------------------------------;
				;4238		[SAVEPSL] <-- [SAVEPC], 		; save SAVEPC around call
			    p159;4239		Q <-- PASSB [PSL.TP]000000,		; mask to clear PSL<TP>
E 263  0002,BA00,A680,22D7 S 2D7;4240		CALL [IE.CLEANUP.CPU]			; cleanup CPU state, state<3:0> unchanged
				;4241							; PSL<TP> = 0, SAVEPC = BPC
				;4242
				;4243	;	Note: The following microinstruction depends on the
				;4244	;	fact that CEFSTS<RDLK> is bit 0, and that there are
				;4245	;	only read-only and write-1-to-clear bits in this
				;4246	;	register.
				;4247
				;4248		;---------------------------------------;
				;4249		VA <-- K10.[IPR.CEFSTS],		; load CEFSTS IPR address
			    p137;4250		MEM.PR (VA)&, [WBUS] <-- PASSA [K1], LONG, ; unconditionally clear RDLK bit
E 264  60F4,7583,2321,4BE2 B 2E2;4251		CASE [STATE.5-3] AT [IE.MACHCHK.NEW]	; see if we've been here before
				;4252
				;4253	;= ALIGNLIST 001x	(IE.MACHCHK.NEW,	IE.MACHCHK.DOUBLE.ERROR,
				;4254	;=			 IE.MACHCHK.MCHK,	IE.MACHCHK.KSNV)
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  136
;    INTEXC.MIC 	     Machine Check Exception								      /REV=
;															     INTEXC
				;4255
				;4256	;	Machine check, continued.
				;4257	;	Nested machine check, invoke console.
				;4258	;
				;4259	;	STATE<5:4> = 01, machine check while inside normal exception flows.
				;4260	;		This is not recoverable, force a console restart.
				;4261
				;4262	IE.MACHCHK.DOUBLE.ERROR:
			    p.84;4263		;---------------------------------------; state<5:4> = 01:
E 2E6  0500,2828,A4C0,0034 J 034;4264		CONSOLE HALT [ERR.DOUBLE]		; nested machine check, invoke console
				;4265
				;4266	;	STATE<5:4> = 10, machine check while inside the machine check flows.
				;4267	;		This is not recoverable, force a console restart.
				;4268
				;4269	IE.MACHCHK.MCHK:
			    p.84;4270		;---------------------------------------; state<5:4> = 10:
E 2EA  0500,2890,A4C0,0034 J 034;4271		CONSOLE HALT [ERR.IE2]			; nested machine check, invoke console
				;4272
				;4273	;	STATE<5:4> = 11, machine check while inside the kernel stack not valid flows.
				;4274	;		This is not recoverable, force a console restart.
				;4275
				;4276	IE.MACHCHK.KSNV:
			    p.84;4277		;---------------------------------------; state<5:4> = 11:
E 2EE  0500,2898,A4C0,0034 J 034;4278		CONSOLE HALT [ERR.IE3]			; nested machine check, invoke console
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  137
;    INTEXC.MIC 	     Machine Check Exception								      /REV=
;															     INTEXC
				;4279
				;4280	;	STATE<5:4> = 00, new exception, process.
				;4281	;	Save state, cleanup, process exception.
				;4282
				;4283	;	At this point,
				;4284	;		W4	=	saved Q
				;4285	;		W5	=	saved VA
				;4286	;		SAVEPC	=	backed up PC
				;4287	;		SAVEPSL =	saved SAVEPC
				;4288	;		ASTLVL	=	ASTLVL, machine check code, CPUID
				;4289
				;4290	IE.MACHCHK.NEW:
				;4291		;---------------------------------------; state<5:4> = 00:
				;4292		VA <-- [SCBB] + 000000[SCB.MACHCHK],	; get SCB offset for machine check
				;4293		[W1] <-- MEM.SCB (VA), LONG,		; read SCB vector
				;4294		STATE.5 <-- 1,				; flag start of machine check
E 2E2  18D2,2021,0A60,0282 J 282;4295			sim addr [scb]
				;4296
				;4297		;---------------------------------------;
				;4298		[W2] <-- [PSL], LONG,			; save current PSL
				;4299		Q <-- PASSB [RN.MODE.OPCODE],		; save VRB before stack write
				;4300		STATE.3-0 <-- 0,			; clear other state flags
			    p153;4301							; >> no state<3> restriction after RESET CPU
E 282  0002,8078,0CC8,2311 S 311;4302		CALL [IE.EXCEPTION]			; call exception handling routine
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  138
;    INTEXC.MIC 	     Machine Check Exception								      /REV=
;															     INTEXC
				;4303
				;4304	;	Machine check, continued.
				;4305	;	Write parameters to stack.
				;4306
				;4307	;	At this point,
				;4308	;		W1	=	SCB vector
				;4309	;		W4	=	saved Q
				;4310	;		W5	=	saved VA
				;4311	;		SAVEPC	=	backed up PC
				;4312	;		SAVEPSL =	machine check parameter
				;4313	;		VA	=	running stack pointer
				;4314	;		Q	=	RN.MODE.OPCODE
				;4315
				;4316		;---------------------------------------;
				;4317		VA <-- [VA] - 4,			; decrement stack pointer
				;4318		MEM (VA)&, [WBUS] <-- PASSB [Q],	; push rn.mode.opcode
			    p139;4319		LONG,					;
E 283  0CE4,8053,20B0,2267 S 267;4320		CALL [WRITE.W4.PREV]			; push saved Q
				;4321
				;4322		;---------------------------------------;
				;4323		VA <-- [VA] - 4,			; decrement stack pointer
E 284  0CE4,8033,20B0,02B0 J 2B0;4324		MEM (VA)&, [WBUS] <-- PASSB [W5], LONG	; push saved VA on stack
				;4325
				;4326		;---------------------------------------;
			    p139;4327		[W4] <-- [SAVEPSL], LONG,		; get saved SAVEPC
E 2B0  0000,0000,1690,2267 S 267;4328		CALL [WRITE.W4.PREV]			; push on stack
				;4329
				;4330		;---------------------------------------;
			    p139;4331		[W4] <-- [INT.SYS], LONG,		; get interrupt system
E 2B1  0000,0000,1700,2267 S 267;4332		CALL [WRITE.W4.PREV]			; push on stack
				;4333
				;4334		;---------------------------------------;
			    p139;4335		[W4] <-- [ASTLVL], LONG,		; get ASTLVL, CPUID, MC code
E 2B2  0000,0000,1650,2267 S 267;4336		CALL [WRITE.W4.PREV]			; push on stack
				;4337
				;4338		;---------------------------------------;
				;4339		VA <-- [VA] - 4,			; decrement stack pointer
				;4340		MEM (VA)&, [WBUS] <-- PASSB 000000[24.], ; push byte count
E 2B3  0CE4,A0C3,20B0,024C J 24C;4341		LONG					;
				;4342
				;4343		;---------------------------------------;
				;4344		[WBUS] <-- [W1] ANDNOT 000000[3], LONG, ; Wbus <-- vector with bits<1:0> = 00
E 24C  04A4,2018,2020,0251 J 251;4345		LOAD PC 				; load new PC, restart prefetching
				;4346							; >> LOAD PC: sync required before exit
				;4347							; do not clear state flags
				;4348
				;4349		;---------------------------------------;
E 251  0000,0000,78B0,025C J 25C;4350		[SP] <-- [VA], LONG			; update SP for pushes
				;4351
				;4352		;---------------------------------------;
				;4353		VA <-- K10.[IPR.CWB],			; push writes out of the chip
			    p144;4354		MEM.PR (VA)&, [WBUS] <-- PASSA [K0], LONG,
E 25C  00F4,6883,2311,0271 J 271;4355		GOTO [SYNC.RESTART.IBOX.NO.RETIRE]	; restart Ibox and decode next instruction
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  139
;    INTEXC.MIC 	     Machine Check Exception								      /REV=
;															     INTEXC
				;4356
				;4357	;	One line subroutine to decrement stack pointer, write W4 to stack.
				;4358	;
				;4359	;	Entry conditions:
				;4360	;		VA	=	current stack pointer
				;4361	;		W4	=	value to be pushed on stack
				;4362	;
				;4363	;	Exit conditions:
				;4364	;		VA	=	updated stack pointer after push
				;4365	;		W4 written on stack
				;4366
				;4367	WRITE.W4.PREV:
				;4368		;---------------------------------------;
				;4369		VA <-- [VA] - 4,			; decrement stack pointer
				;4370		MEM (VA)&, [WBUS] <-- PASSB [W4], LONG, ; push parameter on stack
E 267  0CE4,802B,20B0,0800 R	;4371		RETURN					; return to caller
				;4372
;4373	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  140
;    INTEXC.MIC 	     Interrupts 									      /REV=
;															     INTEXC
;4374	.TOC	"	Interrupts"
;4375
;4376	;	An interrupt differs from a zero parameter exception only in
;4377	;	the selection of the SCB vector (based on the interrupt level
;4378	;	or an external vector) and the value of the final IPL (set to
;4379	;	the level of the interrupt).
;4380	;
;4381	;	The interrupt flows are entered from execution dispatch or from an
;4382	;	interruptible instruction and cause the currently executing instruction
;4383	;	to be packed up (interruptible instruction) or the instruction stream
;4384	;	to be backed up (all others).  PSL<tp> is preserved on an interrupt
;4385	;	between instructions and clear on an interrupt fault.
;4386	;
;4387	;	Entry conditions:
;4388	;		INT.SYS<20:16> =	highest priority oustanding interrupt
;4389	;
;4390	;	Resources available (execution dispatch):
;4391	;		all chip resources
;4392	;
;4393	;	Resources available (fault):
;4394	;		W1, W4, W5
;4395	;
;4396	;	Exit conditions:
;4397	;		Current instruction has been packed up, or instruction stream backed up.
;4398	;		Exception taken through hardware interrupt vector in SCB.  Stack frame:
;4399	;
;4400	;		+-----------------------------------------------------------------+
;4401	;		|				PC				  |
;4402	;		+-----------------------------------------------------------------+
;4403	;		|				PSL				  |
;4404	;		+-----------------------------------------------------------------+
;4405	;
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  141
;    INTEXC.MIC 	     Interrupts 									      /REV=
;															     INTEXC
;4406
;4407	;	Interrupt requests are detected and prioritized by the interrupt section of the chip.  If an interrupt is
;4408	;	pending whose requested IPL is above the value of the PSL IPL (the current IPL is not considered for HALT),
;4409	;	the interrupt section asserts an interrupt request to the I-box.  At the next macro instruction boundary,
;4410	;	the microsequencer supplies the interrupt pending dispatch, whose handler starts at IE.INT.  In addition, the
;4411	;	interrupt section supplies the interrupt-pending signal as a dispatch condition on the microtest bus
;4412	;	(the SHF.NZ.INT decode) for use by the string microcode.  If an interrupt is requested during the execution
;4413	;	of the main loop of string instructions, the microcode dispatches directly to IE.INT.FAULT.
;4414	;
;4415	;	To find the highest priority interrupt request, microcode reads the Interrupt State Register (ISR) via the
;4416	;	INT.SYS decode.  When INT.SYS is read, the interrupt section supplies the encoded value of the highest
;4417	;	interrupt request in bits <20:16>.
;4418	;
;4419	;	There are three types of interrupts possible: Hardwired, Device, and Software.	Hardwired interrupt requests
;4420	;	are specific-purpose interrupts that are recevied by edge-sensitive logic, and remain asserted until cleared
;4421	;	by the microcode.  Such interrupts have implied SCB vectors.
;4422	;
;4423	;	Device interrupt requests are general-purpose interrupts that are receive by level-sensitive logic, and
;4424	;	remain asserted as long as the device asserts the request line.  They are cleared when the device receives
;4425	;	a a read of the IAK1x IPR corresponding to the interrupt request level.
;4426	;
;4427	;	Software interrupt requests implement the architecturally-defined software interrupt mechanism, and remain
;4428	;	asserted until microcode clears the corresponding SISR bit.
;4429	;
;4430	;	As viewed by the microcode thru the INT.SYS decodes, the Interrupt State Register looks as follows:
;4431	;
;4432	;	 31 30 29 28|27 26 25 24|23 22 21 20|19 18 17 16|15 14 13 12|11 10 09 08|07 06 05 04|03 02 01 00
;4433	;	+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
;4434	;	|  |  |  |  |  | 0  0|	| 0  0	0| INT.ID (RO)	|	       SISR<15:01> (RW) 	     |	|
;4435	;	+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
;4436	;	  |  |	|  |  |        |								       |
;4437	;	  |  |	|  |  |        +-- INT_TIM_L request flop (WC)				ICCS<6> (RW) --+
;4438	;	  |  |	|  |  +-- S_ERR_L request flop (WC)
;4439	;	  |  |	|  +-- PMF request flop (WC)
;4440	;	  |  |	+-- H_ERR_L request flop (WC)
;4441	;	  |  +-- PWRFL_L request flop (WC)
;4442	;	  +-- HALT_L request flop (WC)
;4443	;
;4444	;	The following table lists, in order of interrupt priority, the following information about each possible
;4445	;	interrupt request:
;4446	;
;4447	;		o The request source
;4448	;		o The IPL at which the interrupt is taken, in both hex and decimal
;4449	;		o The INT.ID encoding for the interrupt, in both hex and decimal
;4450	;		o The ISR bit number of the state element for the interrupt request
;4451	;		o The method for clearing the interrupt request
;4452	;		o The SCB vector used to service the interrupt
;4453	;
;4454	;	Note that in most cases, the encoded INT.ID value is equal to both the IPL and the ISR state element
;4455	;	bit number.  Exceptions to this rule are annotated with the "&" and "%" flags.	Also note that the
;4456	;	IRQ_L<2> interrupt request takes priority over the INT_TIM_L interrupt request, even though they are at
;4457	;	the same IPL, because IRQ_L<2> is used to implement inter-processor interrupts in multi-processor systems,
;4458	;	and such interrupts must take priority over interval timer interrupts.
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  142
;    INTEXC.MIC 	     Interrupts 									      /REV=
;															     INTEXC
;4459
;4460	;	Interrupt	      INT.ID	   IPL	  ISR Bit	Method For
;4461	;	Request      Type     Hex Dec	 Hex Dec    Dec      Clearing Request		    SCB Vector Used
;4462	;	-------      ----     --- ---	 --- ---    ---     --------------------     -----------------------------
;4463	;	HALT_L	      HW       1F  31	  1F  31     31     Write ISR bit with 1     Console halt (code ERR.HLTPIN)
;4464	;	PWRFL_L       HW       1E  30	  1E  30     30     Write ISR bit with 1     SCB.PWRFL
;4465	;	H_ERR_L       HW       1D  29	  1D  29     29     Write ISR bit with 1     SCB.HERR
;4466	;	Perf. Monitor PM       1B  27	  1B  27     28%    Write ISR bit with 1     Handled by microcode
;4467	;	S_ERR_L       HW       1A  26	  1A  26     27%    Write ISR bit with 1     SCB.SERR
;4468	;	IRQ_L<3>      DV       17  23	  17  23     26%    Read IAK17 IPR	     Supplied by device
;4469	;	IRQ_L<2>      DV       16  22	  16  22     25%    Read IAK16 IPR	     Supplied by device
;4470	;	INT_TIM_L     HW       1C& 28&	  16  22     24%    Write ISR bit with 1     SCB.INTTIM
;4471	;	IRQ_L<1>      DV       15  21	  15  21     23%    Read IAK15 IPR	     Supplied by device
;4472	;	IRQ_L<0>      DV       14  20	  14  20     22%    Read IAK14 IPR	     Supplied by device
;4473	;	SISR<15>      SW       0F  15	  0F  15     15     Write ISR bit with 0     SCB.IPLSOFT+(4*0F)
;4474	;	SISR<14>      SW       0E  14	  0E  14     14     Write ISR bit with 0     SCB.IPLSOFT+(4*0E)
;4475	;	SISR<13>      SW       0D  13	  0D  13     13     Write ISR bit with 0     SCB.IPLSOFT+(4*0D)
;4476	;	SISR<12>      SW       0C  12	  0C  12     12     Write ISR bit with 0     SCB.IPLSOFT+(4*0C)
;4477	;	SISR<11>      SW       0B  11	  0B  11     11     Write ISR bit with 0     SCB.IPLSOFT+(4*0B)
;4478	;	SISR<10>      SW       0A  10	  0A  10     10     Write ISR bit with 0     SCB.IPLSOFT+(4*0A)
;4479	;	SISR<9>       SW       09  09	  09  09     09     Write ISR bit with 0     SCB.IPLSOFT+(4*09)
;4480	;	SISR<8>       SW       08  08	  08  08     08     Write ISR bit with 0     SCB.IPLSOFT+(4*08)
;4481	;	SISR<7>       SW       07  07	  07  07     07     Write ISR bit with 0     SCB.IPLSOFT+(4*07)
;4482	;	SISR<6>       SW       06  06	  06  06     06     Write ISR bit with 0     SCB.IPLSOFT+(4*06)
;4483	;	SISR<5>       SW       05  05	  05  05     05     Write ISR bit with 0     SCB.IPLSOFT+(4*05)
;4484	;	SISR<4>       SW       04  04	  04  04     04     Write ISR bit with 0     SCB.IPLSOFT+(4*04)
;4485	;	SISR<3>       SW       03  03	  03  03     03     Write ISR bit with 0     SCB.IPLSOFT+(4*03)
;4486	;	SISR<2>       SW       02  02	  02  02     02     Write ISR bit with 0     SCB.IPLSOFT+(4*02)
;4487	;	SISR<1>       SW       01  01	  01  01     01     Write ISR bit with 0     SCB.IPLSOFT+(4*01)
;4488	;	No Interrupt  --       00  00	  00  00     00     Dismiss interrupt
;4489	;	-----------------------------------------------------------------------------------------------
;4490	;	Type:						Flags:
;4491	;	    DV - Device interrupt			    & - INT.ID value differs from IPL
;4492	;	    HW - Hardwired interrupt			    % - ISR bit number differs from IPL
;4493	;	    SW - Software Interrupt
;4494	;	    PM - Performance monitoring interrupt
				;4495	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  143
;    INTEXC.MIC 	     Interrupts 									      /REV=
;															     INTEXC
				;4496
				;4497	;	Interrupt at initial dispatch.
				;4498
				;4499	IE.INT..:
				;4500		;********** Hardware dispatch **********;
				;4501		Q <-- 0,				; no PSL bits to clear
				;4502		RESET CPU,				; abort current operations
				;4503		CALL [IE.CLEANUP.CPU.NO.PACKUP],	; cleanup CPU state, state<3:0> = 0,
			    p159;4504							; PSL<TP> unchanged, SAVEPC = BPC
E 024  0002,C000,2006,22D5 S 2D5;4505			sim exception
				;4506
				;4507		;---------------------------------------;
				;4508		[W3] <-- [INT.SYS] AND 00[1F]0000,	; get and mask interrupt id
			    p144;4509		LONG,					;
E 025  0400,30F8,1300,026C J 26C;4510		GOTO [IE.INT.CONT]			; join common code
				;4511
				;4512	;	Interrupt in mid instruction via the INTERRUPT FAULT macro.
				;4513
				;4514	IE.INT.FAULT..:
				;4515		;---------------------------------------;
				;4516		Q <-- PASSB [PSL.TP]000000,		; mask to clear PSL<TP>
				;4517		RESET CPU,				; abort current operations
				;4518		CALL [IE.CLEANUP.CPU],			; cleanup CPU state, state<3:0> unchanged,
			    p159;4519							; PSL<TP> = 0, SAVEPC = BPC
E 040  0002,BA00,2006,22D7 S 2D7;4520			sim exception
				;4521
				;4522		;---------------------------------------;
				;4523		[W3] <-- [INT.SYS] AND 00[1F]0000,	; get and mask interrupt id
			    p144;4524		LONG,					;
E 041  0400,30F8,1300,026C J 26C;4525		GOTO [IE.INT.CONT]			; join common code
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  144
;    INTEXC.MIC 	     Interrupts 									      /REV=
;															     INTEXC
				;4526
				;4527	;	Interrupt, continued.
				;4528
				;4529	;	At this point,
				;4530	;		W3<20:16> =	interrupt id
				;4531	;		SAVEPC	=	old PC
				;4532
				;4533	IE.INT.CONT:
				;4534		;---------------------------------------;
				;4535		[W1] <-- ZEXT [W3] RSH [16.], LONG,	; position to <4:0> for case, SC load
E 26C  0001,D022,0802,8334 J 334;4536		DL <-- WORD				; set dl = word for vector read
				;4537
				;4538		;---------------------------------------;
				;4539		[W2] <-- [W1] LSH [2], LONG,		; position to <6:2> for soft vector
				;4540		SC <-- A [W1],				; load to SC to make mask
				;4541		ACCESS B [W1],				; test bits <4:3>
E 334  2001,4212,0C2A,4160 B 360;4542		CASE [ALU.NZV] AT [IE.INT.CONTINUE]	; case on interrupt id = 0
				;4543
				;4544	;= ALIGNLIST x0xx	(IE.INT.CONTINUE,	IE.NO.INTERRUPT)
				;4545	;  ALU.NZVC set by AND with mask<31> = 0 --> N = V = C = 0
				;4546
				;4547	;	Enter here at the completion of a PMF interrupt to re-enable
				;4548	;	the counters and restart the instruction stream.
				;4549
				;4550	IE.ENABLE.PMF.RESTART:
				;4551		;---------------------------------------;
			    p276;4552		[ECR] <-- [ECR] OR 00[ECR.PMF.ENABLE]0000, ; re-enable PMF counters
E 363  0500,3008,EBA0,2497 S 497;4553		CALL [WAIT.ONE.CYCLE]			; delay after ISR change
				;4554
				;4555	IE.NO.INTERRUPT:
				;4556		;---------------------------------------; alu.z = 1:
				;4557		[WBUS] <-- [SAVEPC], LONG,		; get old PC
				;4558		LOAD PC,				; load new PC, restart prefetching
				;4559							; >> LOAD PC: sync required before exit
				;4560		STATE.5-4 <-- 0,			; clear exception flags
E 364  1025,4000,2280,0271 J 271;4561		GOTO [SYNC.RESTART.IBOX.NO.RETIRE]	; go resume instruction parsing
				;4562
				;4563	SYNC.RESTART.IBOX.NO.RETIRE:
				;4564		;---------------------------------------;
				;4565		SYNCHRONIZE MBOX,			; >> sync with LOAD PC
				;4566		RESTART IBOX,				; restart Ibox
E 271  1020,0100,2004,1000 L	;4567		LAST CYCLE NO RETIRE			; decode next instruction
				;4568
				;4569	;	Interrupt present, dispatch based on interrupt type.
				;4570
				;4571	IE.INT.CONTINUE:
				;4572		;---------------------------------------; alu.z = 0:
				;4573		Q <-- [K1] LSH (SC), LONG,		; create mask to clear interrupt request
			    p145;4574		ACCESS B [W1],				; test bits <2:0>
E 360  8003,4010,2320,4440 B 340;4575		CASE [B.5-3] AT [IE.SWRE.INT]		; case on interrupt id <4:3>
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  145
;    INTEXC.MIC 	     Interrupts 									      /REV=
;															     INTEXC
				;4576
				;4577	;	Software interrupt processing.
				;4578
				;4579	;	At this point,
				;4580	;		W2<6:2> =	interrupt id, masked
				;4581	;		W3<20:16> =	interrupt id (new IPL), masked
				;4582	;		SAVEPC	=	old PC
				;4583	;		Q	=	1b<interrupt id>
				;4584
				;4585	;= ALIGNLIST x00x	(IE.SWRE.INT,		IE.SWRE.INT.1,
				;4586	;=			 IE.DEVICE.INT, 	IE.HARDWIRE.INT)
				;4587	;  INT.SYS masked to 5 bits --> B<5> = 0 --> B<5:3> = 0??
				;4588
				;4589	IE.SWRE.INT:
				;4590		;---------------------------------------; b<4:3> = 00:
				;4591		[INT.SYS] <-- [INT.SYS] ANDNOT [Q],	; clear software interrupt request
				;4592		LONG,					; >> Int sys change, no decode for 4 cycles
E 340  0480,0050,C300,0280 J 280;4593		GOTO [IE.CLEAR.SWRE.INT]		; join common flows
				;4594
				;4595	IE.SWRE.INT.1:
				;4596		;---------------------------------------; b<4:3> = 01:
				;4597		[INT.SYS] <-- [INT.SYS] ANDNOT [Q],	; clear software interrupt request
				;4598		LONG,					; >> Int sys change, no decode for 4 cycles
E 342  0480,0050,C300,0280 J 280;4599		GOTO [IE.CLEAR.SWRE.INT]		; join common flows
				;4600
				;4601	IE.CLEAR.SWRE.INT:
				;4602		;---------------------------------------;
				;4603		[W2] <-- [W2] + 000000[SCB.IPLSOFT],	; add offset to SCB block base
E 280  0880,2400,0C30,0290 J 290;4604		LONG					;
				;4605
				;4606		;---------------------------------------;
				;4607		VA <-- [SCBB] + [W2],			; compute SCB offset
				;4608		[W1] <-- MEM.SCB (VA), LONG,		; read SCB vector
			    p151;4609		GOTO [IE.INT.COMMON],			; go to common code
E 290  08D0,0019,0A60,02AA J 2AA;4610			sim addr [scb]
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  146
;    INTEXC.MIC 	     Interrupts 									      /REV=
;															     INTEXC
				;4611
				;4612	;	Vectored interrupt processing.
				;4613
				;4614	;	At this point,
				;4615	;		W2<6:2> =	interrupt id, masked
				;4616	;		W3<20:16> =	interrupt id (new IPL), masked
				;4617	;		SAVEPC	=	old PC
				;4618	;		DL	=	WORD
				;4619
				;4620	IE.DEVICE.INT:
				;4621		;---------------------------------------; b<4:3> = 10:
				;4622		VA <-- [W2] + K10.[IPR.IAK.BASE],	; add IPL to pre-biased IAK base
E 344  08D4,2585,0831,0292 J 292;4623		[W1] <-- MEM.PR (VA), LEN(DL)		; read appropriate off-chip IPR
				;4624
				;4625		;---------------------------------------;
E 292  0080,0071,2000,0294 J 294;4626		VA <-- B [K.FFFF], LONG 		; get mask to clear upper word
				;4627
				;4628		;---------------------------------------;
				;4629		[W1] <-- [VA] AND [W1], LONG,		; zero upper word
E 294  0400,0010,08B0,0425 J 425;4630		ACCESS B [W1]				; test offset<1:0>
				;4631
				;4632		;---------------------------------------;
				;4633		VA <-- [SCBB] + [W1], LONG,		; compute SCB offset
E 425  6880,0011,2260,43B8 B 4B8;4634		CASE [B.2-0] AT [IE.INT.NORMAL] 	; case on offset<1:0>
				;4635
				;4636	;	Bits <1:0> of the returned vector specify how the microcode
				;4637	;	should process the interrupt, as follows:
				;4638	;
				;4639	;	00	Normal interrupt
				;4640	;	01	Qbus interrupt with IPL forced to 17
				;4641	;	1x	Micro-passive release
				;4642
				;4643	;= ALIGNLIST 100x	(IE.INT.NORMAL, 	IE.INT.QBUS,
				;4644	;=			 IE.PASSIVE.RELEASE.10, IE.PASSIVE.RELEASE.11)
				;4645
				;4646	IE.INT.QBUS:
				;4647		;---------------------------------------; b<1:0> = 01:
				;4648		[W3] <-- 00[17]0000, LONG,		; Qbus system, force IPL = 17
E 4BA  0080,30B8,1000,04B8 J 4B8;4649		GOTO [IE.INT.NORMAL]			; go to common code
				;4650
				;4651	IE.INT.NORMAL:
				;4652		;---------------------------------------; b<1:0> = 00:
				;4653		VA <-- [VA] ANDNOT 000000[03],		; force offset aligned
				;4654		[W1] <-- MEM.SCB (VA), LONG,		; read SCB vector
			    p151;4655		GOTO [IE.INT.COMMON],			; join common code
E 4B8  04D0,2019,08B0,02AA J 2AA;4656			sim addr [scb]
				;4657
				;4658	IE.PASSIVE.RELEASE.10:
				;4659		;---------------------------------------; b<1:0> = 10:
				;4660		[WBUS] <-- [SAVEPC], LONG,		; get old PC
				;4661		LOAD PC,				; load new PC, restart prefetching
				;4662							; >> LOAD PC: sync required before exit
			    p144;4663		STATE.5-4 <-- 0,			; clear exception flags
E 4BC  1025,4000,2280,0271 J 271;4664		GOTO [SYNC.RESTART.IBOX.NO.RETIRE]	; go resume instruction parsing
				;4665
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  147
;    INTEXC.MIC 	     Interrupts 									      /REV=
;															     INTEXC
				;4666	IE.PASSIVE.RELEASE.11:
				;4667		;---------------------------------------; b<1:0> = 11:
				;4668		[WBUS] <-- [SAVEPC], LONG,		; get old PC
				;4669		LOAD PC,				; load new PC, restart prefetching
				;4670							; >> LOAD PC: sync required before exit
			    p144;4671		STATE.5-4 <-- 0,			; clear exception flags
E 4BE  1025,4000,2280,0271 J 271;4672		GOTO [SYNC.RESTART.IBOX.NO.RETIRE]	; go resume instruction parsing
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  148
;    INTEXC.MIC 	     Interrupts 									      /REV=
;															     INTEXC
				;4673
				;4674	;	Hardwired interrupt processing, continued.
				;4675	;	Predefined interrupts.
				;4676
				;4677	;	At this point,
				;4678	;		W3<20:16> =	interrupt id (new IPL), masked
				;4679	;		SAVEPC	=	old PC
				;4680	;		Q	=	1b<interrupt id>
				;4681
				;4682	IE.HARDWIRE.INT:
				;4683		;---------------------------------------; b<4:3> = 11:
				;4684		[WBUS] <-- [K1], LONG,			; clear wbus.z for ipl 1b interrupt
E 346  6000,0000,2320,43A1 B 3A1;4685		CASE [B.2-0] AT [IE.INT.IPL18]		; case on all hardwired levels
				;4686
				;4687	;= ALIGNLIST 000x	(IE.INT.IPL18,	IE.INT.IPL19,	IE.INT.IPL1A,	IE.INT.IPL1B,
				;4688	;=			 IE.INT.IPL1C,	IE.INT.IPL1D,	IE.INT.IPL1E,	IE.INT.IPL1F)
				;4689
				;4690	IE.INT.IPL18:
			    p135;4691		;---------------------------------------; b<2:0> = 000:
E 3A1  0080,3010,A400,0038 J 038;4692		MACHINE CHECK [MCHK.INT.ID.VALUE]	; no such interrupt level, machine check
				;4693
				;4694	IE.INT.IPL19:
			    p135;4695		;---------------------------------------; b<2:0> = 001:
E 3A3  0080,3010,A400,0038 J 038;4696		MACHINE CHECK [MCHK.INT.ID.VALUE]	; no such interrupt level, machine check
				;4697
				;4698	IE.INT.IPL1A:
				;4699		;---------------------------------------; b<2:0> = 010:
				;4700		VA <-- [SCBB] + 000000[SCB.SERR],	; set up SCB offset for soft err interrupt
				;4701		[W1] <-- MEM.SCB (VA), LONG,		; read SCB vector
E 3A5  08D0,22A1,0A60,0296 J 296;4702			sim addr [scb]
				;4703
				;4704		;---------------------------------------;
				;4705		[INT.SYS] <-- [INT.SYS] OR [ISR.SERR]000000, ; clear interrupt request
			    p151;4706		LONG,					; with different ISR bit
E 296  0500,3840,C300,02AA J 2AA;4707		GOTO [IE.INT.COMMON]			; join common interrupt code
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  149
;    INTEXC.MIC 	     Interrupts 									      /REV=
;															     INTEXC
				;4708
				;4709	;	Hardwired interrupt processing, continued.
				;4710	;
				;4711	;	At this point,
				;4712	;		W3<20:16> =	interrupt id (new IPL), masked
				;4713	;		SAVEPC	=	old PC
				;4714	;		Q	=	1b<interrupt id>
				;4715	;		WBUS.Z	=	0 (from previous cycle)
				;4716
				;4717	IE.INT.IPL1B:
				;4718		;---------------------------------------; b<2:0> = 011:
			    p496;4719		[ECR] <-- [ECR] ANDNOT 00[ECR.PMF.ENABLE]0000, ; disable PMF counters
E 3A7  0480,3008,EBA0,2177 S 177;4720		CALL [UPDATE.PMF.COUNTERS]		; update the memory counters
				;4721
				;4722		;---------------------------------------;
				;4723		[INT.SYS] <-- [INT.SYS] OR [ISR.PMF]000000, ; clear interrupt request
			    p144;4724		LONG,					; with different ISR bit
E 3A8  0500,3880,C300,0363 J 363;4725		GOTO [IE.ENABLE.PMF.RESTART]		; re-enable counters, restart
				;4726							;>> Int sys change, no decode for 4 cycles
				;4727
				;4728	IE.INT.IPL1C:
				;4729		;---------------------------------------; b<2:0> = 100
				;4730		VA <-- [SCBB] + 000000[SCB.INTTIM],	; set up SCB offset for timer interrupt
				;4731		[W1] <-- MEM.SCB (VA), LONG,		; read SCB vector
E 3A9  08D0,2601,0A60,029B J 29B;4732			sim addr [scb]
				;4733
				;4734		;---------------------------------------;
E 29B  0080,30B0,1000,02C3 J 2C3;4735		[W3] <-- 00[16]0000, LONG		; interval timer is really IPL 16
				;4736
				;4737		;---------------------------------------;
				;4738		[INT.SYS] <-- [INT.SYS] OR [ISR.INT_TIM]000000, ; clear interrupt request
			    p151;4739		LONG,					; with different ISR bit
E 2C3  0500,3808,C300,02AA J 2AA;4740		GOTO [IE.INT.COMMON]			; join common interrupt code
				;4741
				;4742	IE.INT.IPL1D:
				;4743		;---------------------------------------; b<2:0> = 101:
				;4744		VA <-- [SCBB] + 000000[SCB.HERR],	; set up SCB offset for hard err interrupt
				;4745		[W1] <-- MEM.SCB (VA), LONG,		; read SCB vector
			    p150;4746		GOTO [IE.CLEAR.HWRE.INT],		; go join common interrupt code
E 3AB  08D0,2301,0A60,02C7 J 2C7;4747			sim addr [scb]
				;4748
				;4749	IE.INT.IPL1E:
				;4750		;---------------------------------------; b<2:0> = 110:
				;4751		VA <-- [SCBB] + 000000[SCB.PWRFL],	; set up SCB offset for power fail interrupt
				;4752		[W1] <-- MEM.SCB (VA), LONG,		; read SCB vector
			    p150;4753		GOTO [IE.CLEAR.HWRE.INT],		; go join common interrupt code
E 3AD  08D0,2061,0A60,02C7 J 2C7;4754			sim addr [scb]
				;4755
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  150
;    INTEXC.MIC 	     Interrupts 									      /REV=
;															     INTEXC
				;4756
				;4757	;	Hardwired interrupt processing, continued.
				;4758	;
				;4759	;	At this point,
				;4760	;		W3<20:16> =	interrupt id (new IPL), masked
				;4761	;		SAVEPC	=	old PC
				;4762	;		Q	=	1b<interrupt id>
				;4763	;		WBUS.Z	=	0 (from previous cycle)
				;4764
				;4765	IE.INT.IPL1F:
				;4766		;---------------------------------------; b<2:0> = 111:
				;4767		[INT.SYS] <-- [INT.SYS] OR [ISR.HALT]000000, ; clear halt interrupt request
E 3AF  0500,3C00,C300,02C5 J 2C5;4768		LONG					; >> Int sys change, no decode for 4 cycles
				;4769
			    p.84;4770		;---------------------------------------;
E 2C5  0500,2810,A4C0,0035 J 035;4771		CONSOLE HALT NO CLEANUP [ERR.HLTPIN]	; HALT L asserted, invoke console
				;4772							; >> string packup possible, no cleanup
				;4773							; >> may be done
				;4774
				;4775	IE.CLEAR.HWRE.INT:
				;4776		;---------------------------------------;
				;4777		[INT.SYS] <-- [INT.SYS] OR [Q], LONG,	; clear hardwired interrupt request
			    p151;4778							; >> Int sys change, no decode for 4 cycles
E 2C7  0500,0050,C300,02AA J 2AA;4779		GOTO [IE.INT.COMMON]			; go join common interrupt code
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  151
;    INTEXC.MIC 	     Interrupts 									      /REV=
;															     INTEXC
				;4780
				;4781	;	Merge point for interrupts.
				;4782
				;4783	;	At this point,
				;4784	;		W1	=	SCB vector
				;4785	;		W3	=	new IPL
				;4786
				;4787	IE.INT.COMMON:
				;4788		;---------------------------------------;
				;4789		[W2] <-- [PSL], LONG,			; save PSL
				;4790		STATE.4 <-- 1,				; flag exception
				;4791		STATE.3-0 <-- 0,			; clear other state flags
			    p153;4792							; >> no state<3> restriction after RESET CPU
E 2AA  1001,C000,0CC8,2368 S 368;4793		CALL [IE.INTERRUPT]			; call interrupt processor
				;4794
				;4795	IE.LOAD.PC:
				;4796		;---------------------------------------;
				;4797		[WBUS] <-- [W1] ANDNOT 000000[3], LONG, ; Wbus <-- vector with bits<1:0> = 00
				;4798		LOAD PC,				; load new PC, restart prefetching
				;4799							; >> LOAD PC: sync required before exit
E 2AB  04A4,2018,2020,02CD J 2CD;4800		GOTO [IE.UPDATE.SP]
				;4801
				;4802	;	Exit from exception flows.  A LOAD PC must have been done after the
				;4803	;	last stack write.  This is used as an implicit synchonization event with
				;4804	;	the Mbox such that the LOAD PC stalls until the final write clears
				;4805	;	the memory management checks.  state<5:4> must not be cleared in this
				;4806	;	cycle because a fault on the final stack write would be detected after
				;4807	;	the state bits are cleared.
				;4808
				;4809	IE.UPDATE.SP:
				;4810		;---------------------------------------;
				;4811		[SP] <-- PASSA [VA], LONG,		; update SP for pushes
E 2CD  0080,6883,78B1,02D1 J 2D1;4812		VA <-- K10.[IPR.CWB]			; load CWB address
				;4813
				;4814		;---------------------------------------;
				;4815		MEM.PR (VA)&, [WBUS] <-- [K0], LONG,	; push writes out of the chip
			    p144;4816		STATE.5-4 <-- 0,			; clear permanent state bits
E 2D1  1075,4000,2310,0271 J 271;4817		GOTO [SYNC.RESTART.IBOX.NO.RETIRE]	; sync with LOAD PC, exit instruction
				;4818
;4819	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  152
;    INTEXC.MIC 	     Interrupt and Exception Handling Subroutines					      /REV=
;															     INTEXC
;4820	.TOC	"	Interrupt and Exception Handling Subroutines"
;4821
;4822	;	IE.INTERRUPT -- interrupt handling.
;4823	;
;4824	;	Entry conditions:
;4825	;		W1	=	SCB offset (read in progress)
;4826	;		W2	=	current PSL
;4827	;		W3<20:16> =	new IPL, masked
;4828	;		SAVEPC	=	old PC
;4829	;		STATE<3:0> =	0
;4830	;
;4831	;	Exit conditions:
;4832	;		W1	=	SCB vector
;4833	;		W2	=	original PSL
;4834	;		VA	=	new SP
;4835	;		W0,W3	=	trashed
;4836	;		SAVEPC	=	old PC
;4837	;		PSL, PC 	pushed on interrupt or kernel stack
;4838	;		W4, W5, Q, SAVEPSL all preserved.
;4839	;
;4840	;	IE.EXCEPTION -- exception handling.
;4841	;
;4842	;	Entry conditions:
;4843	;		W1	=	SCB offset (read in progress)
;4844	;		W2	=	current PSL
;4845	;		SAVEPC	=	old PC
;4846	;		STATE<3:0> =	0
;4847	;
;4848	;	Exit conditions:
;4849	;		W1	=	SCB vector
;4850	;		W2	=	original PSL
;4851	;		VA	=	new SP
;4852	;		W0,W3	=	trashed
;4853	;		SAVEPC	=	old PC
;4854	;		PSL, PC 	pushed on interrupt or kernel stack
;4855	;		W4, W5, Q, SAVEPSL all preserved.
;4856
				;4857	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  153
;    INTEXC.MIC 	     Interrupt and Exception Handling Subroutines					      /REV=
;															     INTEXC
				;4858
				;4859	;	Exception handler.
				;4860
				;4861	IE.EXCEPTION:
				;4862		;---------------------------------------;
				;4863		[W3] <-- [PSL] AND 00[1F]0000, LONG,	; start new PSL with current <ipl>
				;4864		STATE.0 <-- 1,				; flag exception vs interrupt
E 311  A400,30F8,10C8,CD68 B 368;4865		CASE [PSL.26-24] AT [IE.EXC.PRVMODE.00]; case on current mode to set prev mode
				;4866
				;4867	;= ALIGNLIST 100x	(IE.EXC.PRVMODE.00,	IE.EXC.PRVMODE.01,
				;4868	;=			 IE.EXC.PRVMODE.10,	IE.EXC.PRVMODE.11)
				;4869
				;4870	IE.EXC.PRVMODE.01:
				;4871		;---------------------------------------; psl<25:24> = 01:
				;4872		[W3] <-- [W3] OR 00[40]0000, LONG,	; new PSL<prv_mode> = curr PSL<cur_mode>
E 36A  0500,3200,1040,0368 J 368;4873		GOTO [IE.EXC.PRVMODE.00]		; go save current stack
				;4874
				;4875	IE.EXC.PRVMODE.10:
				;4876		;---------------------------------------; psl<25:24> = 10:
				;4877		[W3] <-- [W3] OR 00[80]0000, LONG,	; new PSL<prv_mode> = curr PSL<cur_mode>
E 36C  0500,3400,1040,0368 J 368;4878		GOTO [IE.EXC.PRVMODE.00]		; go save current stack
				;4879
				;4880	IE.EXC.PRVMODE.11:
				;4881		;---------------------------------------; psl<25:24> = 11:
				;4882		[W3] <-- [W3] OR 00[0C0]0000, LONG,	; new PSL<prv_mode> = curr PSL<cur_mode>
E 36E  0500,3600,1040,0368 J 368;4883		GOTO [IE.EXC.PRVMODE.00]		; go save current stack
				;4884
				;4885	;	Interrupt handler.
				;4886
				;4887	IE.INTERRUPT:
				;4888	IE.EXC.PRVMODE.00:
				;4889		;---------------------------------------; psl<25:24> = 00:
				;4890		[W0] <-- [SAVEPC], LONG,		; move old PC to W0 for later use
				;4891		ACCESS B [W1],				; get vector, check bits<1:0>
				;4892		CASE [PSL.26-24] AT [IE.INTEXC.SWAP.KS],; case on PSL current mode bits
			    p154;4893			sim cond k s3.[1],
E 368  A000,0010,068F,4D51 B 351;4894			sim ie.intexc
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  154
;    INTEXC.MIC 	     Interrupt and Exception Handling Subroutines					      /REV=
;															     INTEXC
				;4895
				;4896	;	Interrupt/exception processing, continued.
				;4897	;	Save current stack pointer.
				;4898
				;4899	;	At this point,
				;4900	;		W0,SAVEPC =	old PC
				;4901	;		W1	=	SCB vector
				;4902	;		W2	=	current PSL
				;4903	;		W3	=	new PSL
				;4904	;		STATE<0> =	1 if exception
				;4905	;		W4, W5, Q, SAVEPSL all preserved.
				;4906
				;4907	;= ALIGNLIST 000x	(IE.INTEXC.SWAP.KS,	IE.INTEXC.SWAP.ES,
				;4908	;=			 IE.INTEXC.SWAP.SS,	IE.INTEXC.SWAP.US,
				;4909	;=			 IE.INTEXC.SWAP.IS,	IE.INTEXC.SWAP.101,
				;4910	;=			 IE.INTEXC.SWAP.110,	IE.INTEXC.SWAP.111)
				;4911
				;4912	IE.INTEXC.SWAP.KS:
				;4913		;---------------------------------------; psl<26:24> = 000:
			    p155;4914		[KSP] <-- [SP], LONG,			; save SP in KSP register
E 351  6000,0000,81E0,4369 B 369;4915		CASE [B.2-0] AT [IE.INTEXC.KS]		; case on vector<1:0>
				;4916
				;4917	IE.INTEXC.SWAP.ES:
				;4918		;---------------------------------------; psl<26:24> = 001:
			    p155;4919		[ESP] <-- [SP], LONG,			; save SP in ESP register
E 353  6000,0000,85E0,4369 B 369;4920		CASE [B.2-0] AT [IE.INTEXC.KS]		; case on vector<1:0>
				;4921
				;4922	IE.INTEXC.SWAP.SS:
				;4923		;---------------------------------------; psl<26:24> = 010:
			    p155;4924		[SSP] <-- [SP], LONG,			; save SP in SSP register
E 355  6000,0000,89E0,4369 B 369;4925		CASE [B.2-0] AT [IE.INTEXC.KS]		; case on vector<1:0>
				;4926
				;4927	IE.INTEXC.SWAP.US:
				;4928		;---------------------------------------; psl<26:24> = 011:
			    p155;4929		[USP] <-- [SP], LONG,			; save SP in USP register
E 357  6000,0000,8DE0,4369 B 369;4930		CASE [B.2-0] AT [IE.INTEXC.KS]		; case on vector<1:0>
				;4931
				;4932	IE.INTEXC.SWAP.IS:
				;4933		;---------------------------------------; psl<26:24> = 100:
			    p155;4934		[W3] <-- [W3] OR [04]000000, LONG,	; set <is> in new PSL
E 359  6500,3820,1040,4369 B 369;4935		CASE [B.2-0] AT [IE.INTEXC.KS]		; case on vector<1:0>
				;4936
				;4937	IE.INTEXC.SWAP.101:
			    p.84;4938		;---------------------------------------; psl<26:24> = 101:
E 35B  0500,28C8,A4C0,0034 J 034;4939		CONSOLE HALT [ERR.IE.PSL.26-24.101]	; on interrupt stack in exec mode, die
				;4940
				;4941	IE.INTEXC.SWAP.110:
			    p.84;4942		;---------------------------------------; psl<26:24> = 110:
E 35D  0500,28D0,A4C0,0034 J 034;4943		CONSOLE HALT [ERR.IE.PSL.26-24.110]	; on interrupt stack in super mode, die
				;4944
				;4945	IE.INTEXC.SWAP.111:
			    p.84;4946		;---------------------------------------; psl<26:24> = 111:
E 35F  0500,28D8,A4C0,0034 J 034;4947		CONSOLE HALT [ERR.IE.PSL.26-24.111]	; on interrupt stack in user mode, die
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  155
;    INTEXC.MIC 	     Interrupt and Exception Handling Subroutines					      /REV=
;															     INTEXC
				;4948
				;4949	;	Interrupt/exception processing, continued.
				;4950	;	Process based on vector<1:0>.
				;4951
				;4952	;	At this point,
				;4953	;		W0,SAVEPC =	old PC
				;4954	;		W1	=	SCB vector
				;4955	;		W2	=	current PSL
				;4956	;		W3	=	new PSL
				;4957	;		STATE<0> =	1 if exception
				;4958	;		W4, W5, Q, SAVEPSL all preserved.
				;4959
				;4960	;= ALIGNLIST 100x	(IE.INTEXC.KS,	IE.INTEXC.IS,
				;4961	;=			 IE.INTEXC.WCS, IE.INTEXC.RES)
				;4962
				;4963	;	Vector<1:0> = 00, process on kernel stack.
				;4964
				;4965	IE.INTEXC.KS:
				;4966		;---------------------------------------; b<1:0> = 00:
				;4967		[PSL] <-- [W3], LONG,			; load new PSL
			    p157;4968							; >> Int sys change, no decode for 4 cycles
E 369  A000,0000,3040,4D56 B 356;4969		CASE [PSL.26-24] AT [IE.INTEXC.KS.LOAD] ; case on old PSL<is> to load new stk
				;4970
				;4971	;	Vector<1:0> = 01, process on interrupt stack.
				;4972	;	If exception, set PSL<ipl> = 1F.
				;4973
				;4974	IE.INTEXC.IS:
				;4975		;---------------------------------------; b<1:0> = 01:
				;4976		[W3] <-- [W3] OR [04]000000, LONG,	; set new PSL<is> = 1
E 36B  4500,3820,1040,4A7C B 37C;4977		CASE [STATE.2-0] AT [IE.INTEXC.IS.INT]	; case on interrupt vs exception
				;4978
				;4979	;= ALIGNLIST **0x	(IE.INTEXC.IS.INT,	IE.INTEXC.IS.EXC)
				;4980	;  STATE<2:1> = 00 --> STATE<2:0> = 00?
				;4981
				;4982	IE.INTEXC.IS.INT:
				;4983		;---------------------------------------; state<0> = 0:
				;4984		[PSL] <-- [W3], LONG,			; load new PSL
			    p157;4985							; >> Int sys change, no decode for 4 cycles
E 37C  A000,0000,3040,4D77 B 377;4986		CASE [PSL.26-24] AT [IE.INTEXC.IS.LOAD] ; case on old PSL<is> to load new stk
				;4987
				;4988	IE.INTEXC.IS.EXC:
				;4989		;---------------------------------------; state<0> = 1:
				;4990		[PSL] <-- [W3] OR 00[1F]0000, LONG,	; load new PSL, force ipl to 1F
			    p157;4991							; >> Int sys change, no decode for 4 cycles
E 37E  A500,30F8,3040,4D77 B 377;4992		CASE [PSL.26-24] AT [IE.INTEXC.IS.LOAD] ; case on old PSL<is> to load new stk
				;4993
				;4994	;	Vector<1:0> = 10, process in WCS, gonzo for VLSI chips.
				;4995
				;4996	IE.INTEXC.WCS:
			    p.84;4997		;---------------------------------------; b<1:0> = 10:
E 36D  0500,2840,A4C0,0035 J 035;4998		CONSOLE HALT NO CLEANUP [ERR.WCSVEC]	; invalid vector, invoke console
				;4999							; >> string packup possible, no cleanup
				;5000							; >> may be done
				;5001
				;5002	;	Vector<1:0> = 11, process nowhere, gonzo for everybody.
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  156
;    INTEXC.MIC 	     Interrupt and Exception Handling Subroutines					      /REV=
;															     INTEXC
				;5003
				;5004	IE.INTEXC.RES:
			    p.84;5005		;---------------------------------------; b<1:0> = 11:
E 36F  0500,2838,A4C0,0035 J 035;5006		CONSOLE HALT NO CLEANUP [ERR.ILLVEC]	; invalid vector, invoke console
				;5007							; >> string packup possible, no cleanup
				;5008							; >> may be done
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  157
;    INTEXC.MIC 	     Interrupt and Exception Handling Subroutines					      /REV=
;															     INTEXC
				;5009
				;5010	;	Interrupt/exception processing, continued.
				;5011	;	Load new stack ptr, if needed, write PSL, PC to stack frame.
				;5012
				;5013	;	At this point,
				;5014	;		W0,SAVEPC =	old PC
				;5015	;		W1	=	SCB vector
				;5016	;		W2	=	current PSL
				;5017	;		W4, W5, Q, SAVEPSL all preserved.
				;5018
				;5019	;= ALIGNLIST 011x	(IE.INTEXC.KS.LOAD,	IE.INTEXC.KS.NOLOAD)
				;5020
				;5021	IE.INTEXC.KS.LOAD:
				;5022		;---------------------------------------; psl<is> = 0:
E 356  0000,0000,7A00,035E J 35E;5023		[SP] <-- [KSP], LONG			; load new stack pointer
				;5024
				;5025	IE.INTEXC.KS.NOLOAD:
				;5026		;---------------------------------------; psl<is> = 1:
				;5027		VA <-- [SP] - 4,			; decrement the stack for a push
				;5028		MEM (VA)&, [WBUS] <-- PASSB [W2], LONG, ; write old PSL to stack
				;5029		GOTO [IE.INTEXC.WRITE.OLDPC],		; go write PC
E 35E  0CE4,801B,21E0,02D3 J 2D3;5030			sim addr [sp]
				;5031
				;5032	;= ALIGNLIST 011x	(IE.INTEXC.IS.LOAD,	IE.INTEXC.IS.NOLOAD)
				;5033
				;5034	IE.INTEXC.IS.LOAD:
				;5035		;---------------------------------------; psl<is> = 0:
E 377  0000,0000,7A40,037F J 37F;5036		[SP] <-- [ISP], LONG			; load new stack pointer
				;5037
				;5038	IE.INTEXC.IS.NOLOAD:
				;5039		;---------------------------------------; psl<is> = 1:
				;5040		VA <-- [SP] - 4,			; decrement the stack for a push
				;5041		MEM (VA)&, [WBUS] <-- PASSB [W2], LONG, ; write old PSL to stack
				;5042		GOTO [IE.INTEXC.WRITE.OLDPC],		; go write PC
E 37F  0CE4,801B,21E0,02D3 J 2D3;5043			sim addr [sp]
				;5044
				;5045	IE.INTEXC.WRITE.OLDPC:
				;5046		;---------------------------------------;
				;5047		VA <-- [VA] - 4,			; decrement the stack for a push
				;5048		MEM (VA)&, [WBUS] <-- PASSB [W0], LONG, ; push old PC
E 2D3  0CE4,800B,20B0,0800 R	;5049		RETURN					; return to caller
				;5050
;5051	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  158
;    INTEXC.MIC 	     CPU Cleanup Subroutine								      /REV=
;															     INTEXC
;5052	.TOC	"	CPU Cleanup Subroutine"
;5053
;5054	;	IE.CLEANUP.CPU -- clean up CPU, with possible packup
;5055	;	IE.CLEANUP.CPU.NO.PACKUP -- clean up CPU with no packup
;5056	;
;5057	;	Entry conditions:
;5058	;		RESET CPU done in previous or earlier cycle.
;5059	;		Ibox stopped.
;5060	;		Fbox synchronization done in previous or earlier microword (via DST field anything other than NODST)
;5061	;		Q	=	mask of bits to clear in the PSL
;5062	;		STATE<3> =	1 for string packup or interlocked queue instruction
;5063	;		W0	=	address of queue header (if state<3> = 1 from interlocked queue instruction)
;5064	;		W0	=	character or mask (if state<3> = 1 from string instruction)
;5065	;		W3	=	packup state (if state<3> = 1 from string instruction)
;5066	;
;5067	;	Exit conditions:
;5068	;		Q, W1 trashed
;5069	;		W4, W5 preserved
;5070	;		state<3> cleared
;5071	;		state<2:0> cleared only on call to IE.CLEANUP.CPU.NO.PACKUP (see CHMX.PROBEX.MM.FAULT)
;5072	;		pending EM latch stores have completed.
;5073	;		PA queue flushed.
;5074	;		Mbox restarted.
;5075	;		RLOG unwind complete.
;5076	;		PC queue is flushed.
;5077	;		Ibox stopped, waiting for LOAD PC, RESTART IBOX.
;5078	;		PSL	=	old PSL after being masked with Q
;5079	;		SAVEPC	=	backed up PC
;5080	;
;5081	;	Note:	W4, W5 must be preserved by this routine and by all
;5082	;		instruction specific cleanup routines.
;5083
				;5084	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  159
;    INTEXC.MIC 	     CPU Cleanup Subroutine								      /REV=
;															     INTEXC
				;5085
				;5086	;	CPU cleanup routine.
				;5087
				;5088	IE.CLEANUP.CPU.NO.PACKUP:
				;5089		;---------------------------------------;
E 2D5  0000,0000,2008,02D7 J 2D7;5090		STATE.3-0 <-- 0 			; disable packup of instruction
				;5091							; >> potential RESET CPU last cycle:
				;5092							; >> no Wn write or MRQ this cycle
				;5093							; >> no PSL read this cycle
				;5094							; >> no state<3> restriction after RESET CPU
				;5095
				;5096	IE.CLEANUP.CPU:
				;5097		;---------------------------------------;
				;5098		VA <-- K10.[IPR.BPC.UNWIND], LONG,	; load BPC/unwind IPR address
				;5099							; >> potential RESET CPU last cycle:
				;5100							; >> no Wn write or MRQ this cycle
				;5101							; >> no PSL read this cycle
E 2D7  0080,3AE1,2001,0519 J 519;5102			sim addr [k]
				;5103
				;5104		;---------------------------------------;
				;5105		[PSL] <-- [PSL] ANDNOT [Q], LONG,	; clear PSL bits based on mask
E 519  6480,0050,30C0,4B7D B 57D;5106		CASE [STATE.5-3] AT [IE.CLEANUP.CPU.NORMAL] ; need to packup state?
				;5107
				;5108	;= ALIGNLIST	110x	(IE.CLEANUP.CPU.NORMAL, IE.CLEANUP.CPU.PACKUP)
				;5109
				;5110	;	Normal cleanup, or end of queue instruction packup.  There may
				;5111	;	still be a store in the EM latch, and the PA queue may not be
				;5112	;	flushed until the store has completed.	The Ibox IPR read of BPC
				;5113	;	stalls in S4 until a store has cleared the EM latch.  At that
				;5114	;	point, the PA queue may be flushed and the Mbox restartd.
				;5115
				;5116	IE.CLEANUP.CPU.NORMAL:
				;5117		;---------------------------------------;
				;5118		[W1] <-- MEM.PR (VA), LONG,		; unwind RLOG, read BPC, sync
				;5119							; with possible EM latch store;
				;5120		FLUSH PA QUEUE, 			; flush the PA queue,
E 57D  1054,0400,0804,82E0 J 2E0;5121		RESTART MBOX				; and restart the Mbox
				;5122
				;5123	;	The PC queue flush is delayed until the Ibox returns the IPR
				;5124	;	read data to the working register.
				;5125
				;5126		;---------------------------------------;
				;5127		[SAVEPC] <-- [W1], LONG,		; wait for Ibox, return BPC in SAVEPC
				;5128		FLUSH PC QUEUE, 			; and then flush the PC queue
E 2E0  1003,0000,A020,0800 R	;5129		RETURN					; return to caller
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  160
;    INTEXC.MIC 	     CPU Cleanup Subroutine								      /REV=
;															     INTEXC
				;5130
				;5131	;	CPU cleanup, continued.
				;5132	;	Special packup needed, go to packup routine based on opcode.
				;5133	;
				;5134	;	At this point,
				;5135	;		W0	=	address of header (queue), character (string)
				;5136	;		W3	=	used in MOVCx packup.
				;5137	;		RN.MODE.OPCODE = current opcode.
				;5138	;
				;5139	;	Opcode<6> can be used to distinguish the string instructions from the
				;5140	;		queue instructions.
				;5141	;
				;5142	;		MOVC3	=	28	-->	IE.CLEANUP.CPU.STRING and STRING.PACK
				;5143	;		CMPC3	=	29	-->	IE.CLEANUP.CPU.STRING and STRING.PACK
				;5144	;		SCANC	=	2A	-->	IE.CLEANUP.CPU.STRING and STRING.PACK
				;5145	;		SPANC	=	2B	-->	IE.CLEANUP.CPU.STRING and STRING.PACK
				;5146	;		MOVC5	=	2C	-->	IE.CLEANUP.CPU.STRING and STRING.PACK
				;5147	;		CMPC5	=	2D	-->	IE.CLEANUP.CPU.STRING and STRING.PACK
				;5148	;		LOCC	=	3A	-->	IE.CLEANUP.CPU.STRING and STRING.PACK
				;5149	;		SKPC	=	3B	-->	IE.CLEANUP.CPU.STRING and STRING.PACK
				;5150	;		INSQHI	=	5C	-->	IE.CLEANUP.CPU.QUEUE
				;5151	;		INSQTI	=	5D	-->	IE.CLEANUP.CPU.QUEUE
				;5152	;		REMQHI	=	5E	-->	IE.CLEANUP.CPU.QUEUE
				;5153	;		REMQTI	=	5F	-->	IE.CLEANUP.CPU.QUEUE
				;5154
				;5155	IE.CLEANUP.CPU.PACKUP:
				;5156		;---------------------------------------;
E 57F  0003,D078,2000,02E4 J 2E4;5157		Q <-- ZEXT [RN.MODE.OPCODE] RSH [16.]	; extract opcode for test
				;5158
				;5159		;---------------------------------------;
				;5160		VA <-- K10.[IPR.BPC], LONG,		; load BPC IPR address for string
				;5161		ACCESS A [Q],				; test opcode<6>
E 2E4  0080,3AC1,20A1,0520 J 520;5162			sim addr [k]
				;5163
				;5164		;---------------------------------------;
			    p162;5165		Q <-- [W0] LSH [24.], LONG,		; position match character for string
E 520  A003,5800,2010,458A B 58A;5166		CASE [A.7-5] AT [IE.CLEANUP.CPU.STRING] ; case on string vs. queue
				;5167
				;5168	;= ALIGNLIST	101x	(IE.CLEANUP.CPU.STRING, IE.CLEANUP.CPU.QUEUE)
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  161
;    INTEXC.MIC 	     CPU Cleanup Subroutine								      /REV=
;															     INTEXC
				;5169
				;5170	;	CPU cleanup, continued.
				;5171	;	Process exception in interlocked queue instruction.
				;5172	;
				;5173	;	At this point,
				;5174	;		W0	=	address of queue header
				;5175
				;5176	IE.CLEANUP.CPU.QUEUE:
				;5177		;---------------------------------------; opcode<6> = 1 --> queue:
				;5178		VA <-- [W0],				; VA <-- H
				;5179		[W3] <-- MEM.LOCK (VA), LONG,		; read header, acquire hardware interlock
				;5180		STATE.3-0 <-- 0,			; clear state<3> before mem ref
				;5181							; >> no state<3> restriction after RESET CPU
E 58E  004C,0001,1018,0350 J 350;5182			sim addr [queue.1]
				;5183
				;5184		;---------------------------------------;
				;5185		MEM.UNLOCK (VA)&, [WBUS] <-- [W3] ANDNOT 000000[01], ; release secondary interlock
E 350  04EC,2008,2040,0352 J 352;5186		LONG					; update header
				;5187
				;5188		;---------------------------------------;
				;5189		VA <-- K10.[IPR.BPC.UNWIND], LONG,	; load BPC/unwind IPR address
			    p159;5190		GOTO [IE.CLEANUP.CPU.NORMAL],		; join normal cleanup flow
E 352  0080,3AE1,2001,057D J 57D;5191			sim addr [k]
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  162
;    INTEXC.MIC 	     CPU Cleanup Subroutine								      /REV=
;															     INTEXC
				;5192
				;5193	;	CPU cleanup, continued.
				;5194	;	Process exception in string instruction.
				;5195	;
				;5196	;	At this point,
				;5197	;		VA	=	IPR.BPC
				;5198	;		Q<31:24> =	character or mask.
				;5199	;		W3	=	used in MOVCx packup.
				;5200	;
				;5201
				;5202	;	There may still be a store in the EM latch, and the PA queue
				;5203	;	may not be flushed until the store has completed.  The Ibox IPR
				;5204	;	read of BPC stalls in S4 until a store has cleared the EM latch.
				;5205	;	At that point, the PA queue may be flushed.
				;5206
				;5207	IE.CLEANUP.CPU.STRING:
				;5208		;---------------------------------------; opcode<6> = 0 --> string:
				;5209		[W1] <-- MEM.PR (VA), LONG,		; read BPC, sync
				;5210							; with possible EM latch store;
E 58A  1054,0400,0800,0354 J 354;5211		FLUSH PA QUEUE				; flush the PA queue,
				;5212
				;5213	;	Once the Ibox has returned BPC, the instruction is retired so that
				;5214	;	the PC of the instruction after the string instruction is visible.
				;5215	;	A second read of BPC returns this value, and we now have both the
				;5216	;	PC of the string instruction, and the PC of the following instruction.
				;5217
				;5218		;---------------------------------------;
				;5219		[SAVEPC] <-- [W1], LONG,		; wait for Ibox, return BPC in SAVEPC
E 354  1000,4000,A020,035A J 35A;5220		RETIRE INSTRUCTION			; retire rlog and PC queue resources
				;5221
				;5222		;---------------------------------------;
				;5223		VA <-- K10.[IPR.BPC.UNWIND], LONG,	; load BPC/unwind IPR address
E 35A  00D4,3AE1,0C01,0367 J 367;5224		[W2] <-- MEM.PR (VA), LONG		; unwind RLOG, read PC
				;5225
				;5226	;	The PC queue flush is delayed until the Ibox returns the IPR
				;5227	;	read data to the working register.  The second RESET CPU is required
				;5228	;	because the RETIRE INSTRUCTION left the instruction queue in an
				;5229	;	inconsistent state.
				;5230
				;5231		;---------------------------------------;
				;5232		ACCESS B [W2],				; wait for PC read to complete
				;5233		FLUSH PC QUEUE, 			; and flush the PC queue
			    p553;5234		RESET CPU,				; reset the corrupt instruction queue
E 367  1003,0018,2006,05A4 J 5A4;5235		GOTO [STRING.PACK]			; join common string flow, then return
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  163
;    INTEXC.MIC 	     CPU Cleanup Subroutine								      /REV=
;															     INTEXC
				;5236
				;5237	;	Subroutines to delay a specified number of cycles
				;5238	;	before returning to the caller.
				;5239
				;5240	WAIT.23.CYCLES:
				;5241		;---------------------------------------;
E 2B4  0000,0000,2000,22B5 S 2B5;5242		CALL [WAIT.11.CYCLES]			; wait 11, fall thru
				;5243
				;5244	WAIT.11.CYCLES:
				;5245		;---------------------------------------;
E 2B5  0000,0000,2000,22B6 S 2B6;5246		CALL [WAIT.5.CYCLES]			; wait 5, fall thru
				;5247
				;5248	WAIT.5.CYCLES:
				;5249		;---------------------------------------;
E 2B6  0000,0000,2000,22B7 S 2B7;5250		CALL [WAIT.TWO.CYCLES]			; wait 2, fall thru
				;5251
				;5252	WAIT.TWO.CYCLES:
			    p276;5253		;---------------------------------------;
E 2B7  0000,0000,2000,0497 J 497;5254		GOTO [WAIT.ONE.CYCLE]
				;5255
				;5256	;= END INTEXC
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  164
; INTLOGADR.MIC 	     INTLOGADR.MIC -- Integer, Logical, and Address Class Instructions			      /REV=
;
				;5257	.TOC	"INTLOGADR.MIC -- Integer, Logical, and Address Class Instructions"
				;5258	.TOC	"Revision 1.0"
				;5259
				;5260	;	Bob Supnik
				;5261
;5262	.nobin
;5263	;****************************************************************************
;5264	;*									    *
;5265	;*  COPYRIGHT (c) 1987, 1988, 1989, 1990, 1991, 1992 BY 		    *
;5266	;*  DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASSACHUSETTS.		    *
;5267	;*  ALL RIGHTS RESERVED.						    *
;5268	;*									    *
;5269	;*  THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED   *
;5270	;*  ONLY IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE   *
;5271	;*  INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE OR ANY  OTHER   *
;5272	;*  COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY   *
;5273	;*  OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE IS  HEREBY   *
;5274	;*  TRANSFERRED.							    *
;5275	;*									    *
;5276	;*  THE INFORMATION IN THIS SOFTWARE IS  SUBJECT TO CHANGE WITHOUT NOTICE   *
;5277	;*  AND  SHOULD  NOT  BE  CONSTRUED AS	A COMMITMENT BY DIGITAL EQUIPMENT   *
;5278	;*  CORPORATION.							    *
;5279	;*									    *
;5280	;*  DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE  OR  RELIABILITY OF ITS   *
;5281	;*  SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.		    *
;5282	;*									    *
;5283	;****************************************************************************
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  165
; INTLOGADR.MIC 	     Revision History									      /REV=
;
;5284	.TOC	"	Revision History"
;5285
;5286	; Edit	  Date	 Who	     Description
;5287	; ---- --------- ---	---------------------
;5288	; (1)0 18-Jul-90 GMU	Initial production microcode.
;5289	;
;5290	; Begin version 1.0 here
;5291	;   11 05-Jun-90 GMU	Update SEQ.COND names to match implementation.
;5292	;   10 01-May-90 GMU	Uncomment references to CWB IPR.
;5293	;    9 26-Apr-90 GMU	Convert '*' fill constraints to 'x' constraints.
;5294	;    8 29-Mar-90 DGM	Optimize ASHL flow for left 0-31
;5295	;    7 21-Mar-90 DGM	Update comments
;5296	;    6 16-Jan-90 DGM	Change field queue alignment
;5297	;    5	3-Jan-90 DGM	Remove all ALU SEXT and ZEXT functions
;5298	;    4 30-Nov-89 GMU	Convert ADWC/SBWC flows to avoid ALU functions that
;5299	;			use PSL<C> carry-in.
;5300	;    3 19-Oct-89 GMU	Add CWB to ADAWI with register destination.
;5301	;    2 24-AUG-89 GMU	Fix PSL condition code sets for second LW of MOVQ.
;5302	;    1 17-Aug-89 GMU	convert split dispatch for ADAWI to use field queue.
;5303	; (0)0 15-Jul-87 RMS	Trial microcode.
;5304
				;5305	.bin
				;5306	;= BEGIN INTLOG
;5307	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  166
; INTLOGADR.MIC 	     Revision History									      /REV=
;															     INTLOG
;5308
;5309	;	This module implements the integer and logical class, and address class, instructions,
;5310	;	except for multiply and divide.  The instructions in these classes are:
;5311	;
;5312	;
;5313	;	Integer and Logical Instructions
;5314	;
;5315	;	Opcode	 Instruction							N Z V C 	Exceptions
;5316	;	------	 -----------							------- 	----------
;5317	;
;5318	;	58	 ADAWI add.rw, sum.mw						* * * * 	iov
;5319	;
;5320	;	80	 ADDB2 add.rb, sum.mb						* * * * 	iov
;5321	;	C0	 ADDL2 add.rl, sum.ml						* * * * 	iov
;5322	;	A0	 ADDW2 add.rw, sum.mw						* * * * 	iov
;5323	;
;5324	;	81	 ADDB3 add1.rb, add2.rb, sum.wb 				* * * * 	iov
;5325	;	C1	 ADDL3 add1.rl, add2.rl, sum.wl 				* * * * 	iov
;5326	;	A1	 ADDW3 add1.rw, add2.rw, sum.ww 				* * * * 	iov
;5327	;
;5328	;	D8	 ADWC add.rl, sum.ml						* * * * 	iov
;5329	;
;5330	;	78	 ASHL cnt.rb, src.rl, dst.wl					* * * 0 	iov
;5331	;	79	 ASHQ cnt.rb, src.rq, dst.wq					* * * 0 	iov
;5332	;
;5333	;	8A	 BICB2 mask.rb, dst.mb						* * 0 -
;5334	;	CA	 BICL2 mask.rl, dst.ml						* * 0 -
;5335	;	AA	 BICW2 mask.rw, dst.mw						* * 0 -
;5336	;
;5337	;	8B	 BICB3 mask.rb, src.rb, dst.wb					* * 0 -
;5338	;	CB	 BICL3 mask.rl, src.rl, dst.wl					* * 0 -
;5339	;	AB	 BICW3 mask.rw, src.rw, dst.ww					* * 0 -
;5340	;
;5341	;	88	 BISB2 mask.rb, dst.mb						* * 0 -
;5342	;	C8	 BISL2 mask.rl, dst.ml						* * 0 -
;5343	;	A8	 BISW2 mask.rw, dst.mw						* * 0 -
;5344	;
;5345	;	89	 BISB3 mask.rb, src.rb, dst.wb					* * 0 -
;5346	;	C9	 BISL3 mask.rl, src.rl, dst.wl					* * 0 -
;5347	;	A9	 BISW3 mask.rw, src.rw, dst.ww					* * 0 -
;5348	;
;5349	;	93	 BITB mask.rb, src.rb						* * 0 -
;5350	;	D3	 BITL mask.rl, src.rl						* * 0 -
;5351	;	B3	 BITW mask.rw, src.rw						* * 0 -
;5352	;
;5353	;	94	 CLRB dst.wb							0 1 0 -
;5354	;	D4	 CLRL{=F} dst.wl						0 1 0 -
;5355	;	7C	 CLRQ{=D=G} dst.wq						0 1 0 -
;5356	;	B4	 CLRW dst.ww							0 1 0 -
;5357	;
;5358	;	91	 CMPB src1.rb, src2.rb						* * 0 *
;5359	;	D1	 CMPL src1.rl, src2.rl						* * 0 *
;5360	;	B1	 CMPW src1.rw, src2.rw						* * 0 *
;5361	;
;5362	;	98	 CVTBL src.rb, dst.wl						* * 0 0
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  167
; INTLOGADR.MIC 	     Revision History									      /REV=
;															     INTLOG
;5363	;	99	 CVTBW src.rb, dst.wl						* * 0 0
;5364	;	F6	 CVTLB src.rl, dst.wb						* * * 0 	iov
;5365	;	F7	 CVTLW src.rl, dst.ww						* * * 0 	iov
;5366	;	33	 CVTWB src.rw, dst.wb						* * * 0 	iov
;5367	;	32	 CVTWL src.rw, dst.wl						* * 0 0
;5368	;
;5369	;	97	 DECB dif.mb							* * * * 	iov
;5370	;	D7	 DECL dif.ml							* * * * 	iov
;5371	;	B7	 DECW dif.mw							* * * * 	iov
;5372	;
;5373	;	96	 INCB sum.mb							* * * * 	iov
;5374	;	D6	 INCL sum.ml							* * * * 	iov
;5375	;	B6	 INCW sum.mw							* * * * 	iov
;5376	;
;5377	;	92	 MCOMB src.rb, dst.wb						* * 0 -
;5378	;	D2	 MCOML src.rl, dst.wl						* * 0 -
;5379	;	B2	 MCOMW src.rw, dst.ww						* * 0 -
;5380	;
;5381	;	8E	 MNEGB src.rb, dst.wb						* * * * 	iov
;5382	;	CE	 MNEGL src.rl, dst.wl						* * * * 	iov
;5383	;	AE	 MNEGW src.rw, dst.ww						* * * * 	iov
;5384	;
;5385	;	90	 MOVB src.rb, dst.wb						* * 0 -
;5386	;	D0	 MOVL src.rl, dst.wl						* * 0 -
;5387	;	7D	 MOVQ src.rq, dst.wq						* * 0 -
;5388	;	B0	 MOVW src.rw, dst.ww						* * 0 -
;5389	;
;5390	;	9A	 MOVZBW src.rb, dst.wb						0 * 0 -
;5391	;	9B	 MOVZBL src.rb, dst.wl						0 * 0 -
;5392	;	3C	 MOVZWL src.rw, dst.ww						0 * 0 -
;5393	;
;5394	;	DD	 PUSHL src.rl, {-(SP).wl}					* * 0 -
;5395	;
;5396	;	9C	 ROTL cnt.rb, src.rl, dst.wl					* * 0 -
;5397	;
;5398	;	D9	 SBWC sub.rl, dif.ml						* * * * 	iov
;5399	;
;5400	;	82	 SUBB2 sub.rb, dif.mb						* * * * 	iov
;5401	;	C2	 SUBL2 sub.rl, dif.ml						* * * * 	iov
;5402	;	A2	 SUBW2 sub.rw, dif.mw						* * * * 	iov
;5403	;
;5404	;	83	 SUBB3 sub.rb, min.rb, dif.wb					* * * * 	iov
;5405	;	C3	 SUBL3 sub.rl, min.rl, dif.wl					* * * * 	iov
;5406	;	A3	 SUBW3 sub.rw, min.rw, dif.ww					* * * * 	iov
;5407	;
;5408	;	95	 TSTB src.rb							* * 0 0
;5409	;	D5	 TSTL src.rl							* * 0 0
;5410	;	B5	 TSTW src.rw							* * 0 0
;5411	;
;5412	;	8C	 XORB2 mask.rb, dst.mb						* * 0 -
;5413	;	CC	 XORL2 mask.rl, dst.ml						* * 0 -
;5414	;	AC	 XORW2 mask.rw, dst.mw						* * 0 -
;5415	;
;5416	;	8D	 XORB3 mask.rb, src.rb, dst.wb					* * 0 -
;5417	;	CD	 XORL3 mask.rl, src.rl, dst.wl					* * 0 -
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  168
; INTLOGADR.MIC 	     Revision History									      /REV=
;															     INTLOG
;5418	;	AD	 XORW3 mask.rw, src.rw, dst.ww					* * 0 -
;5419	;
;5420	;
;5421	;	Address Instructions
;5422	;
;5423	;	Opcode	 Instruction							N Z V C 	Exceptions
;5424	;	------	 -----------							------- 	----------
;5425	;
;5426	;	9E	 MOVAB src.ab, dst.wl						* * 0 -
;5427	;	DE	 MOVAL{=F} src.al, dst.wl					* * 0 -
;5428	;	7E	 MOVAQ{=D=G} src.aq, dst.wl					* * 0 -
;5429	;	3E	 MOVAW src.aw, dst.wl						* * 0 -
;5430	;
;5431	;	9F	 PUSHAB src.ab, {-(SP).wl}					* * 0 -
;5432	;	DF	 PUSHAL{=F} src.al, {-(SP).wl}					* * 0 -
;5433	;	7F	 PUSHAQ{=D=G} src.aq, {-(SP).wl}				* * 0 -
;5434	;	3F	 PUSHAW src.aw, {-(SP).wl}					* * 0 -
;5435	;
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  169
; INTLOGADR.MIC 	     TSTx										      /REV=
;															     INTLOG
;5436	.TOC	"	TSTx"
;5437
;5438	;	These instructions test the source operand against zero.
;5439	;
;5440	;	Mnemonic      Opcode	Operation				Spec	AT/DL		Dispatch
;5441	;	--------      ------	---------				----	-----		--------
;5442	;	TSTB		95	src.rb - 0				1	r/b		TSTX..
;5443	;	TSTW		B5	src.rw - 0				1	r/w		TSTX..
;5444	;	TSTL		D5	src.rl - 0				1	r/l		TSTX..
;5445	;
;5446	;	Entry conditions:
;5447	;		source queue	=	src.rx operand
;5448	;		dest queue	=	none
;5449	;		branch queue	=	none
;5450	;		field queue	=	none
;5451	;		DL		=	data length of first operand
;5452	;		Ibox state	=	running
;5453	;		Mbox state	=	running
;5454	;
;5455	;	Exit conditions:
;5456	;		The PSL condition codes are set.
;5457	;
;5458	;	Condition codes:
;5459	;		N <-- dst lss 0
;5460	;		Z <-- dst eql 0
;5461	;		V <-- 0 		[Integer overflow trap disabled.]
;5462	;		C <-- 0
;5463	;
				;5464	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  170
; INTLOGADR.MIC 	     TSTx										      /REV=
;															     INTLOG
				;5465
				;5466	;	TSTx operation:
				;5467	;
				;5468	;		src.rx - 0
				;5469
				;5470	TSTX..:
				;5471		;********** Hardware dispatch **********;
				;5472		[WBUS] <-- [S1], LEN(DL),		; src operand to Wbus for test
				;5473		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 102  0000,0004,208D,1000 L	;5474		LAST CYCLE				; decode next instruction
				;5475
;5476	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  171
; INTLOGADR.MIC 	     INCx, DECx 									      /REV=
;															     INTLOG
;5477	.TOC	"	INCx, DECx"
;5478
;5479	;	These instructions increment or decrement the destination operand.
;5480	;
;5481	;	Mnemonic      Opcode	Operation				Spec	AT/DL		Dispatch
;5482	;	--------      ------	---------				----	-----		--------
;5483	;	INCB		96	dst.mb <-- dst.mb + 1			1	m/b		INCX..
;5484	;	INCW		B6	dst.mw <-- dst.mw + 1			1	m/w		INCX..
;5485	;	INCL		D6	dst.ml <-- dst.ml + 1			1	m/l		INCX..
;5486	;
;5487	;	DECB		97	dst.mb <-- dst.mb - 1			1	m/b		DECX..
;5488	;	DECW		B7	dst.mw <-- dst.mw - 1			1	m/w		DECX..
;5489	;	DECL		D7	dst.ml <-- dst.ml - 1			1	m/l		DECX..
;5490	;
;5491	;	Entry conditions:
;5492	;		source queue	=	dst.mx operand
;5493	;		dest queue	=	dst.mx result
;5494	;		branch queue	=	none
;5495	;		field queue	=	none
;5496	;		DL		=	data length of first operand
;5497	;		Ibox state	=	running
;5498	;		Mbox state	=	running
;5499	;
;5500	;	Exit conditions:
;5501	;		The PSL condition codes are set.
;5502	;		The result has been stored in the destination memory location or register.
;5503	;
;5504	;	Condition codes:
;5505	;		(INCx)			(DECx)
;5506	;		N <-- dst lss 0 	N <-- dst lss 0
;5507	;		Z <-- dst eql 0 	Z <-- dst eql 0
;5508	;		V <-- overflow		V <-- overflow		[Integer overflow trap enabled.]
;5509	;		C <-- carry out 	C <-- borrow out
;5510	;
				;5511	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  172
; INTLOGADR.MIC 	     INCx, DECx 									      /REV=
;															     INTLOG
				;5512
				;5513	;	INCx operation:
				;5514	;
				;5515	;		dst.mx <-- dst.mx + 1
				;5516
				;5517	INCX..:
				;5518		;********** Hardware dispatch **********;
				;5519		[DST] <-- [S1] + 1, LEN(DL),		; increment operand, store
				;5520		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 120  0800,0004,248D,1800 L	;5521		LAST CYCLE CHECK OVERFLOW		; decode next instruction
				;5522
				;5523
				;5524	;	DECx operation:
				;5525	;
				;5526	;		dst.mx <-- dst.mx - 1
				;5527
				;5528	DECX..:
				;5529		;********** Hardware dispatch **********;
				;5530		[DST] <-- [S1] - 1, LEN(DL),		; decrement operand, store
				;5531		SET PSL CC.IIIJ,			; set psl cc's, psl map is iiij
E 122  0B00,0004,248D,9800 L	;5532		LAST CYCLE CHECK OVERFLOW		; decode next instruction
				;5533
;5534	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  173
; INTLOGADR.MIC 	     CLRx										      /REV=
;															     INTLOG
;5535	.TOC	"	CLRx"
;5536
;5537	;	These instructions clear the destination operand.
;5538	;
;5539	;	Mnemonic      Opcode	Operation				Spec	AT/DL		Dispatch
;5540	;	--------      ------	---------				----	-----		--------
;5541	;	CLRB		94	dst.wb <-- 0				1	w/b		CLRX..
;5542	;	CLRW		B4	dst.ww <-- 0				1	w/w		CLRX..
;5543	;	CLRL		D4	dst.wl <-- 0				1	w/l		CLRX..
;5544	;	CLRQ		7C	dst.wq <-- 0				1	w/q		CLRQ..
;5545	;
;5546	;	Entry conditions:
;5547	;		source queue	=	none
;5548	;		dest queue	=	dst.wx result
;5549	;		branch queue	=	none
;5550	;		field queue	=	none
;5551	;		DL		=	data length of first operand
;5552	;		Ibox state	=	running
;5553	;		Mbox state	=	running
;5554	;
;5555	;	Exit conditions:
;5556	;		The PSL condition codes are set.
;5557	;		The result has been stored in the destination memory location or register.
;5558	;
;5559	;	Condition codes:
;5560	;		N <-- 0
;5561	;		Z <-- 1
;5562	;		V <-- 0 		[Integer overflow trap enabled.]
;5563	;		C <-- C
;5564	;
				;5565	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  174
; INTLOGADR.MIC 	     CLRx										      /REV=
;															     INTLOG
				;5566
				;5567	;	CLRx operation:
				;5568	;
				;5569	;		dst.wx <-- 0
				;5570
				;5571	CLRX..:
				;5572		;********** Hardware dispatch **********;
				;5573		Q&, [DST] <-- PASSB 000000[00], 	; write zero to destination, set shift latch
				;5574		LEN(DL),				;
				;5575		SET PSL CC.IIIP,			; set psl cc's, default map is iiip
E 10C  0002,A006,240C,1000 L	;5576		LAST CYCLE				; decode next instruction
				;5577
				;5578	CLRQ..:
				;5579		;********** Hardware dispatch **********;
				;5580		Q&, [DST] <-- PASSB 000000[00], 	; write zero to destination, set shift latch
				;5581		LEN(DL),				;
E 10E  0002,A006,240C,0376 J 376;5582		SET PSL CC.IIIP 			; set psl cc's, default map is iiip
				;5583
				;5584	WRITE.QW:
				;5585		;---------------------------------------;
				;5586		[DST] <-- [Q], LONG,			; write high result to destination
E 376  0000,0000,24A0,1000 L	;5587		LAST CYCLE				; decode next instruction
				;5588
;5589	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  175
; INTLOGADR.MIC 	     CMPx, BITx 									      /REV=
;															     INTLOG
;5590	.TOC	"	CMPx, BITx"
;5591
;5592	;	These instructions operate on two read only sources.
;5593	;
;5594	;	Mnemonic      Opcode	Operation				Spec	AT/DL		Dispatch
;5595	;	--------      ------	---------				----	-----		--------
;5596	;	CMPB		91	src1.rb - src2.rb			2	rr/bb		CMPI..
;5597	;	CMPW		B1	src1.rw - src2.rw			2	rr/ww		CMPI..
;5598	;	CMPL		D1	src1.rl - src2.rl			2	rr/ll		CMPI..
;5599	;
;5600	;	BITB		93	src1.rb and src2.rb			2	rr/bb		BITX..
;5601	;	BITW		B3	src1.rw and src2.rw			2	rr/ww		BITX..
;5602	;	BITL		D3	src1.rl and src2.rl			2	rr/ll		BITX..
;5603	;
;5604	;	Entry conditions:
;5605	;		source queue	=	src1.rx operand
;5606	;					src2.rx operand
;5607	;		dest queue	=	none
;5608	;		branch queue	=	none
;5609	;		field queue	=	none
;5610	;		DL		=	data length of second operand
;5611	;		Ibox state	=	running
;5612	;		Mbox state	=	running
;5613	;
;5614	;	Exit conditions:
;5615	;		The PSL condition codes are set.
;5616	;
;5617	;	Condition codes:
;5618	;		(CMPx)			(BITx)
;5619	;		N <-- src1 lss src2	N <-- dst lss 0
;5620	;		Z <-- src1 eql src2	Z <-- dst eql 0
;5621	;		V <-- 0 		V <-- 0 		[Integer overflow trap disabled.]
;5622	;		C <-- src1 lssu src2	C <-- C
;5623	;
				;5624	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  176
; INTLOGADR.MIC 	     CMPx, BITx 									      /REV=
;															     INTLOG
				;5625
				;5626	;	CMPx operation:
				;5627	;
				;5628	;		src1.rx - src2.rx
				;5629
				;5630	CMPI..:
				;5631		;********** Hardware dispatch **********;
				;5632		[WBUS] <-- [S1] - [S2], LEN(DL),	; compare operands, result to Wbus
				;5633		SET PSL CC.JIZJ,			; set psl cc's, psl map is jizj
E 106  0A80,004C,208C,9000 L	;5634		LAST CYCLE				; decode next instruction
				;5635
				;5636
				;5637	;	BITx operation:
				;5638	;
				;5639	;		src1.rx and src2.rx
				;5640
				;5641	BITX..:
				;5642		;********** Hardware dispatch **********;
				;5643		[WBUS] <-- [S1] AND [S2], LEN(DL),	; and operands, result to Wbus
				;5644		SET PSL CC.IIIP,			; set psl cc's, default map is iiip
E 104  0400,004C,208C,1000 L	;5645		LAST CYCLE				; decode next instruction
				;5646
;5647	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  177
; INTLOGADR.MIC 	     ADDin, SUBin, BISxn, BICxn, XORxn, ADWC, SBWC					      /REV=
;															     INTLOG
;5648	.TOC	"	ADDin, SUBin, BISxn, BICxn, XORxn, ADWC, SBWC"
;5649
;5650	;	These two operand versions of these instructions operate on a source operand and a destination operand,
;5651	;	and store the result in the destination operand.
;5652	;
;5653	;	The three operand versions of these instructions operate on two source operands, and store the result
;5654	;	in the destination operand.
;5655	;
;5656	;	Mnemonic      Opcode	Operation				Spec	AT/DL		Dispatch
;5657	;	--------      ------	---------				----	-----		--------
;5658	;	ADDB2		80	dst.mb <-- src.rb + dst.mb		2	rm/bb		ADDIN..
;5659	;	ADDW2		A0	dst.mw <-- src.rw + dst.mw		2	rm/ww		ADDIN..
;5660	;	ADDL2		C0	dst.ml <-- src.rl + dst.ml		2	rm/ll		ADDIN..
;5661	;	ADDB3		81	dst.wb <-- src1.rb + src2.rb		3	rrw/bbb 	ADDIN..
;5662	;	ADDW3		A1	dst.ww <-- src1.rw + src2.rw		3	rrw/www 	ADDIN..
;5663	;	ADDL3		C1	dst.wl <-- src1.rl + src2.rl		3	rrw/lll 	ADDIN..
;5664	;
;5665	;	SUBB2		82	dst.mb <-- dst.mb - src.rb		2	rm/bb		SUBIN..
;5666	;	SUBW2		A2	dst.mw <-- dst.mw - src.rw		2	rm/ww		SUBIN..
;5667	;	SUBL2		C2	dst.ml <-- dst.ml - src.rl		2	rm/ll		SUBIN..
;5668	;	SUBB3		83	dst.wb <-- src2.rb - src1.rb		3	rrw/bbb 	SUBIN..
;5669	;	SUBW3		A3	dst.ww <-- src2.rw - src1.rw		3	rrw/www 	SUBIN..
;5670	;	SUBL3		C3	dst.wl <-- src2.rl - src1.rl		3	rrw/lll 	SUBIN..
;5671	;
;5672	;	BISB2		88	dst.mb <-- src.rb or dst.mb		2	rm/bb		BISXN..
;5673	;	BISW2		A8	dst.mw <-- src.rw or dst.mw		2	rm/ww		BISXN..
;5674	;	BISL2		C8	dst.ml <-- src.rl or dst.ml		2	rm/ll		BISXN..
;5675	;	BISB3		89	dst.wb <-- src1.rb or src2.rb		3	rrw/bbb 	BISXN..
;5676	;	BISW3		A9	dst.ww <-- src1.rw or src2.rw		3	rrw/www 	BISXN..
;5677	;	BISL3		C9	dst.wl <-- src1.rl or src2.rl		3	rrw/lll 	BISXN..
;5678	;
;5679	;	BICB2		8A	dst.mb <-- ~src.rb and dst.mb		2	rm/bb		BICXN..
;5680	;	BICW2		AA	dst.mw <-- ~src.rw and dst.mw		2	rm/ww		BICXN..
;5681	;	BICL2		CA	dst.ml <-- ~src.rl and dst.ml		2	rm/ll		BICXN..
;5682	;	BICB3		8B	dst.wb <-- ~src1.rb and src2.rb 	3	rrw/bbb 	BICXN..
;5683	;	BICW3		AB	dst.ww <-- ~src1.rw and src2.rw 	3	rrw/www 	BICXN..
;5684	;	BICL3		CB	dst.wl <-- ~src1.rl and src2.rl 	3	rrw/lll 	BICXN..
;5685	;
;5686	;	XORB2		8C	dst.mb <-- src.rb xor dst.mb		2	rm/bb		XORXN..
;5687	;	XORL2		AC	dst.mw <-- src.rw xor dst.mw		2	rm/ww		XORXN..
;5688	;	XORW2		CC	dst.ml <-- src.rl xor dst.ml		2	rm/ll		XORXN..
;5689	;	XORB3		8D	dst.wb <-- src1.rb xor src2.rb		3	rrw/bbb 	XORXN..
;5690	;	XORL3		AD	dst.ww <-- src1.rw xor src2.rw		3	rrw/www 	XORXN..
;5691	;	XORW3		CD	dst.wl <-- src1.rl xor src2.rl		3	rrw/lll 	XORXN..
;5692	;
;5693	;	ADWC		D8	dst.ml <-- src.rl + dst.ml + C		2	rm/ll		ADWC.SBWC..
;5694	;
;5695	;	SBWC		D9	dst.ml <-- dst.ml - src.rl - C		2	rm/ll		ADWC.SBWC..
;5696	;
;5697	;	Entry conditions:	      (2 operands)  (3 operands)
;5698	;		source queue	=	src.rx	 or   src1.rx	operand
;5699	;					dst.mx	 or   src2.rx	operand
;5700	;		dest queue	=	dst.mx	 or   dst.wx	result
;5701	;		branch queue	=	none
;5702	;		field queue	=	none
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  178
; INTLOGADR.MIC 	     ADDin, SUBin, BISxn, BICxn, XORxn, ADWC, SBWC					      /REV=
;															     INTLOG
;5703	;		DL		=	data length of destination operand
;5704	;		Ibox state	=	running
;5705	;		Mbox state	=	running
;5706	;
;5707	;	Exit conditions:
;5708	;		The PSL condition codes are set.
;5709	;		The result has been stored in the destination memory location or register.
;5710	;
;5711	;	Condition codes:
;5712	;		(ADDin, ADWC)		(SUBin, SBWC)
;5713	;		N <-- dst lss 0 	N <-- dst lss 0
;5714	;		Z <-- dst eql 0 	Z <-- dst eql 0
;5715	;		V <-- overflow		V <-- overflow		[Integer overflow trap enabled.]
;5716	;		C <-- carry out 	C <-- borrow out
;5717	;
;5718	;		(BISxn, BICxn, XORxn)
;5719	;		N <-- dst lss 0
;5720	;		Z <-- dst eql 0
;5721	;		V <-- 0 					[Integer overflow disabled.]
;5722	;		C <-- C
;5723	;
				;5724	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  179
; INTLOGADR.MIC 	     ADDin, SUBin, BISxn, BICxn, XORxn, ADWC, SBWC					      /REV=
;															     INTLOG
				;5725
				;5726	;	ADDin operation:
				;5727	;
				;5728	;		dst.mx <-- dst.mx + src.rx		(ADDi2)
				;5729	;		dst.wx <-- src2.rx + src1.rx		(ADDi3)
				;5730
				;5731	ADDIN..:
				;5732		;********** Hardware dispatch **********;
				;5733		[DST] <-- [S1] + [S2], LEN(DL), 	; compute result, write to destination
				;5734		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 118  0880,004C,248D,1800 L	;5735		LAST CYCLE CHECK OVERFLOW		; decode next instruction
				;5736
				;5737
				;5738	;	SUBin operation:
				;5739	;
				;5740	;		dst.mx <-- dst.mx - src.rx		(SUBi2)
				;5741	;		dst.wx <-- src2.rx - src1.rx		(SUBi3)
				;5742
				;5743	SUBIN..:
				;5744		;********** Hardware dispatch **********;
				;5745		[DST] <-- (-[S1] + [S2]), LEN(DL),	; compute result, write to destination
				;5746		SET PSL CC.IIIJ,			; set psl cc's, psl map is iiij
E 11A  0A00,004C,248D,9800 L	;5747		LAST CYCLE CHECK OVERFLOW		; decode next instruction
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  180
; INTLOGADR.MIC 	     ADDin, SUBin, BISxn, BICxn, XORxn, ADWC, SBWC					      /REV=
;															     INTLOG
				;5748
				;5749	;	BISxn operation:
				;5750	;
				;5751	;		dst.mx <-- dst.mx or src.rx		(BISx2)
				;5752	;		dst.wx <-- src2.rx or src1.rx		(BISx3)
				;5753
				;5754	BISXN..:
				;5755		;********** Hardware dispatch **********;
				;5756		[DST] <-- [S1] OR [S2], LEN(DL),	; compute result, write to destination
				;5757		SET PSL CC.IIIP,			; set psl cc's, default map is iiip
E 128  0500,004C,248C,1000 L	;5758		LAST CYCLE				; decode next instruction
				;5759
				;5760
				;5761	;	BICxn operation:
				;5762	;
				;5763	;		dst.mx <-- dst.mx andnot src.rx 	(BICx2)
				;5764	;		dst.wx <-- src2.rx andnot src1.rx	(BICx3)
				;5765
				;5766	BICXN..:
				;5767		;********** Hardware dispatch **********;
				;5768		[DST] <-- [S2] ANDNOT [S1], LEN(DL),	; compute result, write to destination
				;5769		SET PSL CC.IIIP,			; set psl cc's, default map is iiip
E 12A  0480,0044,249C,1000 L	;5770		LAST CYCLE				; decode next instruction
				;5771
				;5772
				;5773	;	XORxn operation:
				;5774	;
				;5775	;		dst.mx <-- dst.mx xor src.rx		(XORx2)
				;5776	;		dst.wx <-- src2.rx xor src1.rx		(XORx3)
				;5777
				;5778	XORXN..:
				;5779		;********** Hardware dispatch **********;
				;5780		[DST] <-- [S1] XOR [S2], LEN(DL),	; compute result, write to destination
				;5781		SET PSL CC.IIIP,			; set psl cc's, default map is iiip
E 12C  0600,004C,248C,1000 L	;5782		LAST CYCLE				; decode next instruction
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  181
; INTLOGADR.MIC 	     ADDin, SUBin, BISxn, BICxn, XORxn, ADWC, SBWC					      /REV=
;															     INTLOG
				;5783
				;5784	;	ADWC operation:
				;5785	;
				;5786	;		dst.ml <-- dst.ml + src.rl + psl.c
				;5787	;
				;5788	;	SBWC operation:
				;5789	;
				;5790	;		dst.ml <-- dst.ml - src.rl - psl.c
				;5791
				;5792	ADWC.SBWC..:
				;5793		;********** Hardware dispatch **********;
				;5794		[W0] <-- [S1], LONG,			; get first operand
E 11C  0002,8048,0480,0378 J 378;5795		Q <-- PASSB [S2]			; get second operand
				;5796							; wait a cycle for psl.c
				;5797
				;5798		;---------------------------------------;
E 378  0400,2008,20C0,0046 J 046;5799		[WBUS] <-- [PSL] AND 000000[01], LONG	; test PSL<C>
				;5800							; >> PSL<C> reference in 2nd cycle OK
				;5801
			    p182;5802		;---------------------------------------;
E 046  8000,0000,2000,4C51 B 051;5803		CASE [OPCODE.2-0] AT [ADWC]		; break into separate opcode flows
				;5804
				;5805	;= ALIGNLIST	xx0x	(ADWC,			SBWC)
				;5806	;  Opcodes = D8, D9 --> opcode<2:0> = 00?
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  182
; INTLOGADR.MIC 	     ADDin, SUBin, BISxn, BICxn, XORxn, ADWC, SBWC					      /REV=
;															     INTLOG
				;5807
				;5808	;	ADWC, SBWC, continued.
				;5809	;	Complete computation.
				;5810	;
				;5811	;	At this point,
				;5812	;		W0	=	first operand
				;5813	;		Q	=	second operand
				;5814	;		ALU.Z	=	0 if PSL<C>=1, 1 if PSL<C>=0
				;5815
				;5816	;	ADWC
				;5817
				;5818	ADWC:
				;5819		;---------------------------------------; opcode<0> = 0:
E 051  2000,0000,2000,4161 B 061;5820		CASE [ALU.NZV] AT [ADWC.C1]		; case on psl<c> value
				;5821
				;5822	;= ALIGNLIST	x0xx	(ADWC.C1,		ADWC.C0)
				;5823	;  ALU.NZV set from AND with 1 --> N = V = 0
				;5824
				;5825	ADWC.C0:
				;5826		;---------------------------------------; alu.z = 1:
				;5827		[DST] <-- [W0] + [Q], LONG,		; compute result, write to destination
				;5828		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 065  0880,0050,241D,1800 L	;5829		LAST CYCLE CHECK OVERFLOW		; decode next instruction
				;5830
				;5831	ADWC.C1:
				;5832		;---------------------------------------; alu.z = 0:
				;5833		[DST] <-- [W0] + [Q] + 1, LONG, 	; compute result, write to destination
				;5834		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 061  0900,0050,241D,1800 L	;5835		LAST CYCLE CHECK OVERFLOW		; decode next instruction
				;5836
				;5837	;	SBWC
				;5838
				;5839	SBWC:
				;5840		;---------------------------------------; opcode<0> = 1:
E 053  2000,0000,2000,4171 B 071;5841		CASE [ALU.NZV] AT [SBWC.C1]		; case on psl<c> value
				;5842
				;5843	;= ALIGNLIST	x0xx	(SBWC.C1,		SBWC.C0)
				;5844	;  ALU.NZV set from AND with 1 --> N = V = 0
				;5845
				;5846	SBWC.C0:
				;5847		;---------------------------------------; alu.z = 1:
				;5848		[DST] <-- [Q] - [W0], LONG,		; compute result, write to memory
				;5849		SET PSL CC.IIIJ,			; set psl cc's, psl map is iiij
E 075  0A80,0008,24AD,9800 L	;5850		LAST CYCLE CHECK OVERFLOW		; decode next instruction
				;5851
				;5852	SBWC.C1:
				;5853		;---------------------------------------; alu.z = 0:
				;5854		[DST] <-- [Q] - [W0] - 1, LONG, 	; compute result, write to memory
				;5855		SET PSL CC.IIIJ,			; set psl cc's, psl map is iiij
E 071  0780,0008,24AD,9800 L	;5856		LAST CYCLE CHECK OVERFLOW		; decode next instruction
				;5857
;5858	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  183
; INTLOGADR.MIC 	     MOVx, MOVAx, MOVZxy, PUSHL, PUSHAx, MCOMx, MNEGx					      /REV=
;															     INTLOG
;5859	.TOC	"	MOVx, MOVAx, MOVZxy, PUSHL, PUSHAx, MCOMx, MNEGx"
;5860
;5861	;	These instructions move or operate on a source operand and store the result in a destination operand.
;5862	;
;5863	;	Mnemonic      Opcode	Operation				Spec	AT/DL		Dispatch
;5864	;	--------      ------	---------				----	-----		--------
;5865	;	MOVB		90	dst.wb <-- src.rb			2	rw/bb		MOVX..
;5866	;	MOVW		B0	dst.ww <-- src.rw			2	rw/ww		MOVX..
;5867	;	MOVL		D0	dst.wl <-- src.rl			2	rw/ll		MOVX..
;5868	;	MOVQ		7D	dst.wq <-- src.rq			2	rw/qq		MOVQ..
;5869	;
;5870	;	MOVAB		9E	dst.wl <-- src.ab			2	aw/bl		MOVX..
;5871	;	MOVAW		3E	dst.wl <-- src.aw			2	aw/wl		MOVX..
;5872	;	MOVAL		DE	dst.wl <-- src.al			2	aw/ll		MOVX..
;5873	;	MOVAQ		7E	dst.wl <-- src.aq			2	aw/ql		MOVX..
;5874	;
;5875	;	MOVZBL		9A	dst.wl <-- zext(src.rb) 		2	rw/bl		MOVZBX..
;5876	;	MOVZBW		9B	dst.ww <-- zext(src.rb) 		2	rw/bw		MOVZBX..
;5877	;	MOVZWL		3C	dst.wl <-- zext(src.rw) 		2	rw/wl		MOVZWL..
;5878	;
;5879	;	PUSHL		DD	-(sp) <-- src.rl			1	r/l		MOVX..
;5880	;
;5881	;	PUSHAB		9F	-(sp) <-- src.ab			1	a/b		MOVX..
;5882	;	PUSHAW		3F	-(sp) <-- src.aw			1	a/w		MOVX..
;5883	;	PUSHAL		DF	-(sp) <-- src.al			1	a/l		MOVX..
;5884	;	PUSHAQ		7F	-(sp) <-- src.aq			1	a/q		MOVX..
;5885	;
;5886	;	MCOMB		92	dst.wb <-- ~src.rb			2	rw/bb		MCOMX..
;5887	;	MCOMW		B2	dst.ww <-- ~src.rw			2	rw/ww		MCOMX..
;5888	;	MCOML		D2	dst.wl <-- ~src.rl			2	rw/ll		MCOMX..
;5889	;
;5890	;	MNEGB		8E	dst.wb <-- -src.rb			2	rw/bb		MNEGX..
;5891	;	MNEGL		AE	dst.ww <-- -src.rw			2	rw/ww		MNEGX..
;5892	;	MNEGW		CE	dst.wl <-- -src.rl			2	rw/ll		MNEGX..
;5893	;
;5894	;	Entry conditions:
;5895	;		source queue	=	src.rx	or  src.ax operand
;5896	;		dest queue	=	dst.wx	or  (implicit -(sp) specifier)	result
;5897	;		branch queue	=	none
;5898	;		field queue	=	none
;5899	;		DL		=	data length of second operand
;5900	;		Ibox state	=	running
;5901	;		Mbox state	=	running
;5902	;
;5903	;	Exit conditions:
;5904	;		The PSL condition codes are set.
;5905	;		The result has been stored in the destination register or memory location.
;5906	;
;5907	;	Condition codes:
;5908	;		(MOVx, MOVAx, MOVZxy, PUSHL, PUSHAx, MCOMx):
;5909	;		N <-- dst lss 0
;5910	;		Z <-- dst eql 0
;5911	;		V <-- 0 			[Integer overflow trap disabled.]
;5912	;		C <-- C
;5913	;
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  184
; INTLOGADR.MIC 	     MOVx, MOVAx, MOVZxy, PUSHL, PUSHAx, MCOMx, MNEGx					      /REV=
;															     INTLOG
;5914	;		(MNEGx):
;5915	;		N <-- dst lss 0
;5916	;		Z <-- dst eql 0
;5917	;		V <-- overflow			[Integer overflow trap enabled.]
;5918	;		C <-- borrow out
;5919	;
;5920	;	Notes:
;5921	;		1.  Performance:  Creating an implicit specifier for PUSHL, PUSHAx allows
;5922	;		    the I-box to continue instead of suspending.
;5923	;
				;5924	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  185
; INTLOGADR.MIC 	     MOVx, MOVAx, MOVZxy, PUSHL, PUSHAx, MCOMx, MNEGx					      /REV=
;															     INTLOG
				;5925
				;5926	;	MOVx, MOVAx, PUSHL, PUSHAx operation:
				;5927	;
				;5928	;		dst.wx <-- src.rx [src.ax]
				;5929
				;5930	MOVX..:
				;5931		;********** Hardware dispatch **********;
				;5932		[DST] <-- [S1], LEN(DL),		; write source to destination
				;5933		SET PSL CC.IIIP,			; set psl cc's, default map is iiip
E 108  0000,0004,248C,1000 L	;5934		LAST CYCLE				; decode next instruction
				;5935
				;5936	MOVQ..:
				;5937		;********** Hardware dispatch **********;
				;5938		[DST] <-- [S1], LEN(DL),		; save first longword
				;5939		SET PSL CC.IIIP,			; set psl cc's, default map is iiip
E 10A  0002,804C,248C,0399 J 399;5940		Q <-- PASSB [S2]			; save second longword
				;5941
				;5942	WRITE.QW.SETCC:
				;5943		;---------------------------------------;
				;5944		[DST] <-- PASSA [Q], LONG,		; store second longword via shifter
				;5945		SET PSL CC.IIIP.QUAD,			; finish psl cc's from 2nd LW
E 399  0000,4002,24AE,1000 L	;5946		LAST CYCLE
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  186
; INTLOGADR.MIC 	     MOVx, MOVAx, MOVZxy, PUSHL, PUSHAx, MCOMx, MNEGx					      /REV=
;															     INTLOG
				;5947
				;5948	;	MOVZxy operation:
				;5949	;
				;5950	;		dst.wy <-- zext(src.rx)
				;5951
				;5952	MOVZBX..:
				;5953		;********** Hardware dispatch **********;
				;5954		[DST] <-- [S1] AND 000000[0FF], 	; mask source down to a byte
				;5955		LEN(DL),				; write destination word or longword
				;5956		SET PSL CC.IIIP,			; set psl cc's, default map is iiip
E 110  0400,27FC,248C,1000 L	;5957		LAST CYCLE				; decode next instruction
				;5958
				;5959	MOVZWL..:
				;5960		;********** Hardware dispatch **********;
				;5961		[DST] <-- [S1] AND [K.FFFF], LONG,	; mask source down to a word
				;5962		SET PSL CC.IIIP,			; set psl cc's, default map is iiip
E 112  0400,0070,248C,1000 L	;5963		LAST CYCLE				; decode next instruction
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  187
; INTLOGADR.MIC 	     MOVx, MOVAx, MOVZxy, PUSHL, PUSHAx, MCOMx, MNEGx					      /REV=
;															     INTLOG
				;5964
				;5965	;	MCOMx operation:
				;5966	;
				;5967	;		dst.wx <-- ~src.rx
				;5968
				;5969	MCOMX..:
				;5970		;********** Hardware dispatch **********;
				;5971		[DST] <-- NOT [S1], LEN(DL),		; complement source operand, store
				;5972		SET PSL CC.IIIP,			; set psl cc's, default map is iiip
E 114  0D80,0044,240C,1000 L	;5973		LAST CYCLE				; decode next instruction
				;5974
				;5975
				;5976	;	MNEGx operation:
				;5977	;
				;5978	;		dst.wx <-- -src.rx
				;5979
				;5980	MNEGX..:
				;5981		;********** Hardware dispatch **********;
				;5982		[DST] <-- -[S1], LEN(DL),		; negate source operand, store
				;5983		SET PSL CC.IIIJ,			; set psl cc's, psl map is iiij
E 116  0D00,0044,240D,9800 L	;5984		LAST CYCLE CHECK OVERFLOW		; decode next instruction
				;5985
;5986	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  188
; INTLOGADR.MIC 	     ADAWI										      /REV=
;															     INTLOG
;5987	.TOC	"	ADAWI"
;5988
;5989	;	This instruction does an interlocked add to an aligned word in memory.
;5990	;
;5991	;	Mnemonic      Opcode	Operation				Spec	AT/DL			Dispatch
;5992	;	--------      ------	---------				----	-----			--------
;5993	;	ADAWI		58	dst.mw <-- src.rw + dst.mw		2	rv{m1}/ww		ADAWI..
;5994	;
;5995	;	Entry conditions:
;5996	;		source queue	=	src.rw operand
;5997	;					dst.mw operand (register) or dst.mw address (memory)
;5998	;		dest queue	=	dst.mw result (register) or none (memory)
;5999	;		branch queue	=	none
;6000	;		field queue	=	one valid entry for second specifier
;6001	;		DL		=	WORD
;6002	;		Ibox state	=	running
;6003	;		Mbox state	=	stopped
;6004	;
;6005	;	Exit conditions:
;6006	;		The PSL condition codes are set.
;6007	;		The result has been stored in the destination memory location or register.
;6008	;
;6009	;	Condition codes:
;6010	;		N <-- dst lss 0
;6011	;		Z <-- dst eql 0
;6012	;		V <-- overflow		[Integer overflow trap enabled.]
;6013	;		C <-- carry out
;6014	;
;6015	;	Notes:
;6016	;		1.  Performance:  The register flows could be one cycle shorter, except for the MISC
;6017	;		    field conflict of RESTART MBOX and LOAD PSL CC.MAP.IIII.
;6018	;		2.  Memory management:	For memory, the initial read is with write check, thus the write
;6019	;		    forces memory management errors to be made visible before instruction completion.
;6020	;
				;6021	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  189
; INTLOGADR.MIC 	     ADAWI										      /REV=
;															     INTLOG
				;6022
				;6023	;	ADAWI operation:
				;6024	;
				;6025	;		dst.mw <-- src.rw + dst.mw, interlocked
				;6026
				;6027	;
				;6028	;	Note: Constraints for ADAWI.., ADAWI.R, and ADAWI.M are
				;6029	;	done in ALIGN.MIC.
				;6030
				;6031	ADAWI..:
				;6032		;********** Hardware dispatch **********; fq.vr = 11 (invalid)
E 246  4000,0000,2000,5240 B 240;6033		CASE [FQ.VR] AT [ADAWI.M]		; wait for field queue to
				;6034							; indicate register or memory
				;6035
				;6036	ADAWI.R:
				;6037		;---------------------------------------; fq.vr = 01 (valid, register)
				;6038		[DST] <-- [S1] + [S2], LEN(DL), 	; perform add, no interlock for rmode
E 242  0880,004C,248D,039B J 39B;6039		SET PSL CC.IIII 			; set psl cc's, psl map is iiii
				;6040
				;6041		;---------------------------------------;
				;6042		VA <-- K10.[IPR.CWB],			; push out buffered writes
				;6043		MEM.PR (VA)&, [WBUS] <-- PASSA [K0], LONG, ; (NUDGE function)
E 39B  00F4,6883,2311,03A4 J 3A4;6044		GOTO [ADAWI.COMPLETE]			; go restart suspended I-box
				;6045
				;6046	ADAWI.M:
				;6047		;---------------------------------------; fq.vr = 00 (valid, memory)
				;6048		VA <-- B [S2], LONG,			; save dst address, test bit<0>
				;6049		[W0] <-- PASSA [S1],			; save source operand
				;6050			sim cond k s3.[0],
E 240  0080,404B,0480,0521 J 521;6051			sim addr [ea.2]
				;6052
				;6053		;---------------------------------------;
				;6054		NOP,					; nothing to do...
E 521  6000,0000,2000,438D B 58D;6055		CASE [B.2-0] AT [ADAWI.WORD.ALIGNED]	; if not word aligned, reserved operand
				;6056
				;6057	;= ALIGNLIST 110x	(ADAWI.WORD.ALIGNED,	ADAWI.NOT.WORD.ALIGNED)
				;6058
				;6059	ADAWI.NOT.WORD.ALIGNED:
			    p127;6060		;---------------------------------------; b<0> = 1:
E 58F  0000,0000,2000,003C J 03C;6061		RESERVED OPERAND FAULT			; reserved operand fault
				;6062
				;6063	ADAWI.WORD.ALIGNED:
				;6064		;---------------------------------------; b<0> = 0:
E 58D  004C,0004,0800,03A0 J 3A0;6065		[W1] <-- MEM.LOCK (VA), LEN(DL) 	; read destination operand, locked
				;6066
				;6067		;---------------------------------------;
				;6068		MEM.UNLOCK (VA)&, [WBUS] <-- [W0] + [W1], ; compute result
				;6069		LEN(DL),				; write to memory
E 3A0  08EC,0014,201D,03A4 J 3A4;6070		SET PSL CC.IIII 			; set psl cc's, psl map is iiii
				;6071
				;6072	ADAWI.COMPLETE:
				;6073		;---------------------------------------;
				;6074		RESTART MBOX,				; resume operand processing
E 3A4  0000,0000,2004,9800 L	;6075		LAST CYCLE CHECK OVERFLOW		; decode next instruction
;6076	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  190
; INTLOGADR.MIC 	     CVTBW, CVTBL, CVTWL								      /REV=
;															     INTLOG
;6077	.TOC	"	CVTBW, CVTBL, CVTWL"
;6078
;6079	;	These instructions sign extend and move a data item from the first
;6080	;	(source) operand to the second (destination) operand.
;6081	;
;6082	;	Mnemonic      Opcode	Operation				Spec	AT/DL		Dispatch
;6083	;	--------      ------	---------				----	-----		--------
;6084	;	CVTBW		99	dst.ww <-- src.rb			2	rw/bw		CVTBI..
;6085	;	CVTBL		98	dst.wl <-- src.rb			2	rw/bl		CVTBI..
;6086	;	CVTWL		32	dst.wl <-- src.rw			2	rw/wl		CVTWL..
;6087	;
;6088	;	Entry conditions:
;6089	;		source queue	=	src.rx operand
;6090	;		dest queue	=	dst.wx result
;6091	;		branch queue	=	none
;6092	;		field queue	=	none
;6093	;		DL		=	data length of second operand
;6094	;		Ibox state	=	running
;6095	;		Mbox state	=	running
;6096	;
;6097	;	Exit conditions:
;6098	;		The PSL condition codes are set.
;6099	;		The result has been stored in the destination memory location or register.
;6100	;
;6101	;	Condition codes:
;6102	;		N <-- dst lss 0
;6103	;		Z <-- dst eql 0
;6104	;		V <-- 0 		[Integer overflow trap disabled.]
;6105	;		C <-- 0
;6106	;
;6107	;	Notes:
;6108	;		1.  Performance:  Adding the SEXT alu functions makes these instructions a cycle shorter.
;6109	;
				;6110	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  191
; INTLOGADR.MIC 	     CVTBW, CVTBL, CVTWL								      /REV=
;															     INTLOG
				;6111
				;6112	;	CVTBW, CVTBL, CVTWL operation:
				;6113	;
				;6114	;		dst.wy <-- sext(src.wx)
				;6115
				;6116	CVTBI..:
				;6117		;********** Hardware dispatch **********;
E 130  0003,5800,2080,03AA J 3AA;6118		Q <-- [S1] LSH [24.], LONG		; set shifter sign to sign of byte
				;6119
				;6120		;---------------------------------------;
				;6121		[DST] <-- SEXT [Q] RSH [24.], LEN(DL),	; sign extend byte to lw, store wd/lw
				;6122		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 3AA  0001,9856,279D,1000 L	;6123		LAST CYCLE				; decode next instruction
				;6124
				;6125	CVTWL..:
				;6126		;********** Hardware dispatch **********;
E 132  0003,5000,2080,03AC J 3AC;6127		Q <-- [S1] LSH [16.], LONG		; set shifter sign to sign of word
				;6128
				;6129		;---------------------------------------;
				;6130		[DST] <-- SEXT [Q] RSH [16.], LONG,	; sign extend word to longword, store
				;6131		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 3AC  0001,9052,279D,1000 L	;6132		LAST CYCLE				; decode next instruction
				;6133
;6134	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  192
; INTLOGADR.MIC 	     CVTWB, CVTLB, CVTLW								      /REV=
;															     INTLOG
;6135	.TOC	"	CVTWB, CVTLB, CVTLW"
;6136
;6137	;	These instructions truncate and move a data item from the first
;6138	;	(source) operand to the second (destination) operand.
;6139	;
;6140	;	Mnemonic      Opcode	Operation				Spec	AT/DL		Dispatch
;6141	;	--------      ------	---------				----	-----		--------
;6142	;	CVTWB		33	dst.wb <-- src.rw			2	rw/wb		CVTXB..
;6143	;	CVTLB		F6	dst.wb <-- src.rl			2	rw/lb		CVTXB..
;6144	;	CVTLW		F7	dst.ww <-- src.rl			2	rw/lw		CVTLW..
;6145	;
;6146	;	Entry conditions:
;6147	;		source queue	=	src.rx operand
;6148	;		dest queue	=	dst.wx result
;6149	;		branch queue	=	none
;6150	;		field queue	=	none
;6151	;		DL		=	data length of second operand
;6152	;		Ibox state	=	running
;6153	;		Mbox state	=	running
;6154	;
;6155	;	Exit conditions:
;6156	;		The PSL condition codes are set.
;6157	;		The result has been stored in the destination memory location or register.
;6158	;
;6159	;	Condition codes:
;6160	;		N <-- dst lss 0
;6161	;		Z <-- dst eql 0
;6162	;		V <-- overflow		[Integer overflow trap enabled.]
;6163	;		C <-- 0
;6164	;
;6165	;	Notes:
;6166	;		1.  Performance:  Adding the SEXT alu functions makes these instructions a cycle shorter.
;6167	;
				;6168	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  193
; INTLOGADR.MIC 	     CVTWB, CVTLB, CVTLW								      /REV=
;															     INTLOG
				;6169
				;6170	;	CVTWB, CVTLB, CVTLW operation:
				;6171	;
				;6172	;		dst.wy <-- trunc(src.rx)
				;6173
				;6174	CVTXB..:
				;6175		;********** Hardware dispatch **********;
				;6176		VA&, [DST] <-- [S1], LEN(DL),		; result byte to dst
				;6177		Q <-- [S1] LSH [24.],			; set shifter sign to sign of byte
				;6178		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
				;6179							; va = lllb or xxwb,  q = b000
E 136  8003,5805,248D,4C0D B 10D;6180		CASE [OPCODE.2-0] AT [CVTLB]		; breakout into separate flows
				;6181
				;6182	;= ALIGNLIST	110x	(CVTLB, 		CVTWB)
				;6183
				;6184	CVTLB:
				;6185		;---------------------------------------; opcode<0> = 0:
				;6186		Q <-- SEXT [Q] RSH [24.], LONG, 	; sign extend byte to lw
				;6187		DL <-- LONG,				; set dl for lw comparison
E 10D  0003,9850,2393,03E5 J 3E5;6188		GOTO [CVTXI.COMMON]			; join common convert code
				;6189							; va = lllb, q = sssb
				;6190
				;6191	CVTWB:
				;6192		;---------------------------------------; opcode<0> = 1:
				;6193		Q <-- SEXT [Q] RSH [24.], LONG, 	; sign extend byte to lw
				;6194		DL <-- WORD,				; set dl for word comparison
E 10F  0003,9850,2392,83E5 J 3E5;6195		GOTO [CVTXI.COMMON]			; join common convet code
				;6196							; va = xxwb,  q = sssb
				;6197
				;6198	CVTLW..:
				;6199		;********** Hardware dispatch **********;
				;6200		VA&, [DST] <-- [S1], LEN(DL),		; result word to dst
				;6201		Q <-- [S1] LSH [16.],			; set shifter sign to sign of word
E 134  0003,5005,248D,03E4 J 3E4;6202		SET PSL CC.IIII 			; set psl cc's, psl map is iiii
				;6203							; va = llww,  q = ww00
				;6204
				;6205		;---------------------------------------;
				;6206		Q <-- SEXT [Q] RSH [16.], LONG, 	; sign extend word to lw
				;6207		DL <-- LONG,				; set dl for lw comparison
E 3E4  0003,9050,2393,03E5 J 3E5;6208		GOTO [CVTXI.COMMON]			; join common convert code
				;6209							; va = llww,  q = ssww
				;6210
				;6211	CVTXI.COMMON:
				;6212		;---------------------------------------;
				;6213		[WBUS] <-- [VA] XOR [Q], LEN(DL),	; compare src with sext(trunc(src))
				;6214		SET PSL CC.PPJP,			; set psl v if compare <> 0
E 3E5  0600,0054,20BE,9800 L	;6215		LAST CYCLE CHECK OVERFLOW		; decode next instruction
				;6216
;6217	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  194
; INTLOGADR.MIC 	     ROTL										      /REV=
;															     INTLOG
;6218	.TOC	"	ROTL"
;6219
;6220	;	This instruction rotates a longword source operand left or right and stores
;6221	;	the result in the destination operand.
;6222	;
;6223	;	Mnemonic      Opcode	Operation				Spec	AT/DL		Dispatch
;6224	;	--------      ------	---------				----	-----		--------
;6225	;	ROTL		9C	dst.wl <-- src.rl rot cnt.rb		3	rrw/bll 	ROTL..
;6226	;
;6227	;	Entry conditions:
;6228	;		source queue	=	cnt.rb operand
;6229	;					src.rl operand
;6230	;		dest queue	=	dst.wl result
;6231	;		branch queue	=	none
;6232	;		field queue	=	none
;6233	;		DL		=	LONG
;6234	;		Ibox state	=	running
;6235	;		Mbox state	=	running
;6236	;
;6237	;	Exit conditions:
;6238	;		The PSL condition codes are set.
;6239	;		The result has been stored in the destination memory location or register.
;6240	;
;6241	;	Condition codes:
;6242	;		N <-- dst lss 0
;6243	;		Z <-- dst eql 0
;6244	;		V <-- 0 		[Integer overflow trap disabled.]
;6245	;		C <-- C
;6246	;
				;6247	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  195
; INTLOGADR.MIC 	     ROTL										      /REV=
;															     INTLOG
				;6248
				;6249	;	ROTL operation:
				;6250	;
				;6251	;		dst.wl <-- src.rl rot cnt.rb
				;6252
				;6253	ROTL..:
				;6254		;********** Hardware dispatch **********;
				;6255		[W0] <-- B [S2], LONG,			; save operand
E 138  0080,0048,048A,03E6 J 3E6;6256		SC <-- A [S1]				; move rotate count to SC
				;6257
				;6258		;---------------------------------------;
				;6259		[DST] <-- [W0] LROT (SC), LONG, 	; rotate and write result to register
				;6260		SET PSL CC.IIIP,			; set psl cc's, default map is iiip
E 3E6  0001,000A,241C,1000 L	;6261		LAST CYCLE				; decode next instruction
				;6262
;6263	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  196
; INTLOGADR.MIC 	     ASHL										      /REV=
;															     INTLOG
;6264	.TOC	"	ASHL"
;6265
;6266	;	This instruction shifts a source operand left or right and stores
;6267	;	the result in the destination operand.
;6268	;
;6269	;	Mnemonic      Opcode	Operation				Spec	AT/DL		Dispatch
;6270	;	--------      ------	---------				----	-----		--------
;6271	;	ASHL		78	dst.wl <-- src.rl shift cnt.rb		3	rrw/bll 	ASHL..
;6272	;
;6273	;	Entry conditions:
;6274	;		source queue	=	cnt.rb operand
;6275	;					src.rl operand
;6276	;		dest queue	=	dst.wl result
;6277	;		branch queue	=	none
;6278	;		field queue	=	none
;6279	;		DL		=	LONG
;6280	;		Ibox state	=	running
;6281	;		Mbox state	=	running
;6282	;
;6283	;	Exit conditions:
;6284	;		The PSL condition codes are set.
;6285	;		The result has been stored in the destination memory location or register.
;6286	;
;6287	;	Condition codes:
;6288	;		N <-- dst lss 0
;6289	;		Z <-- dst eql 0
;6290	;		V <-- overflow		[Integer overflow trap enabled.]
;6291	;		C <-- 0
;6292	;
				;6293	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  197
; INTLOGADR.MIC 	     ASHL										      /REV=
;															     INTLOG
				;6294
				;6295	;	ASHL operation:
				;6296	;
				;6297	;		dst.wl <-- src.rl shift cnt.rb
				;6298
				;6299	ASHL..:
				;6300		;********** Hardware dispatch **********;
				;6301		[W0] <-- PASSB [S2], LONG,		; test sign of, save source operand
				;6302		SC <-- A [S1],				; load shift count
E 13A  0000,804A,048A,0411 J 411;6303			sim cond [s3.sv]
				;6304
				;6305		;---------------------------------------;
				;6306		Q <-- SEXT [W0] RSH (32-SC), LONG,	; get only sign bits of source
E 411  A003,0008,2390,4570 B 470;6307		CASE [A.7-5] AT [ASHL.LEFT.0.31]	; case on shift count<7:5>
				;6308
				;6309	;= ALIGNLIST 000x	(ASHL.LEFT.0.31,	ASHL.LEFT.32.63,
				;6310	;=			 ASHL.LEFT.64.95,	ASHL.LEFT.96.127,
				;6311	;=			 ASHL.RIGHT.128.97,	ASHL.RIGHT.96.65,
				;6312	;=			 ASHL.RIGHT.64.33,	ASHL.RIGHT.32.1)
				;6313
				;6314	ASHL.LEFT.0.31:
				;6315		;---------------------------------------; 0 <= count <= 31:
				;6316		[DST] <-- [W0] LSH (SC), LONG,		; shift source operand left by count
E 470  0001,4002,241D,03E7 J 3E7;6317		SET PSL CC.IIII 			; set psl cc's, psl map is iiii
				;6318
				;6319		;---------------------------------------;
				;6320		[WBUS] <-- [SHIFT.SIGN] XOR [Q], LONG,	; compare sign of result with
				;6321							;  sign bits of source
				;6322		SET PSL CC.PPJP,			; set overflow if they are not equal
E 3E7  0600,0050,239E,9800 L	;6323		LAST CYCLE CHECK OVERFLOW		; decode next instruction
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  198
; INTLOGADR.MIC 	     ASHL										      /REV=
;															     INTLOG
				;6324
				;6325	;	ASHL, continued.
				;6326	;	Left shift out of range, result is zero.
				;6327
				;6328	;	At this point,
				;6329	;		W0	=	source operand
				;6330	;		SC	=	shift count
				;6331
				;6332	ASHL.LEFT.32.63:
				;6333		;---------------------------------------; 32 <= count <= 63:
				;6334		Q&, [DST] <-- PASSB 000000[00], LONG,	; result is zero, set shift latch
				;6335		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 472  0002,A002,240D,03E9 J 3E9;6336		GOTO [ASHL.LEFT.ZERO]			; go test for overflow
				;6337
				;6338	ASHL.LEFT.64.95:
				;6339		;---------------------------------------; 64 <= count <= 95:
				;6340		Q&, [DST] <-- PASSB 000000[00], LONG,	; result is zero, set shift latch
				;6341		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 474  0002,A002,240D,03E9 J 3E9;6342		GOTO [ASHL.LEFT.ZERO]			; go test for overflow
				;6343
				;6344	ASHL.LEFT.96.127:
				;6345		;---------------------------------------; 96 <= count <= 127:
				;6346		Q&, [DST] <-- PASSB 000000[00], LONG,	; result is zero, set shift latch
				;6347		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 476  0002,A002,240D,03E9 J 3E9;6348		GOTO [ASHL.LEFT.ZERO]			; go test for overflow
				;6349
				;6350	ASHL.LEFT.ZERO:
				;6351		;---------------------------------------;
				;6352		[WBUS] <-- [Q] XOR [W0], LONG,		; compare unshifted original with result
				;6353		SET PSL CC.PPJP,			; set overflow if they are not equal
E 3E9  0600,0008,20AE,9800 L	;6354		LAST CYCLE CHECK OVERFLOW		; decode next instruction
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  199
; INTLOGADR.MIC 	     ASHL										      /REV=
;															     INTLOG
				;6355
				;6356	;	ASHL, continued.
				;6357	;	Right shift cases.
				;6358
				;6359	;	At this point,
				;6360	;		W0	=	source operand
				;6361	;		SC	=	shift count
				;6362	;		shifter sign =	set from source
				;6363
				;6364	ASHL.RIGHT.128.97:
				;6365		;---------------------------------------; -128 <= count <= -97:
				;6366		[DST] <-- SEXT [W0] RSH [31.], LONG,	; result is sign of source
				;6367		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 478  0001,9F0A,279D,1000 L	;6368		LAST CYCLE				; decode next instruction (no overflow)
				;6369
				;6370	ASHL.RIGHT.96.65:
				;6371		;---------------------------------------; -96 <= count <= -65:
				;6372		[DST] <-- SEXT [W0] RSH [31.], LONG,	; result is sign of source
				;6373		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 47A  0001,9F0A,279D,1000 L	;6374		LAST CYCLE				; decode next instruction (no overflow)
				;6375
				;6376	ASHL.RIGHT.64.33:
				;6377		;---------------------------------------; -64 <= count <= -33:
				;6378		[DST] <-- SEXT [W0] RSH [31.], LONG,	; result is sign of source
				;6379		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 47C  0001,9F0A,279D,1000 L	;6380		LAST CYCLE				; decode next instruction (no overflow)
				;6381
				;6382	ASHL.RIGHT.32.1:
				;6383		;---------------------------------------; -32 <= count <= -1:
				;6384		[DST] <-- SEXT [W0] RSH (32-SC),	; shift right, inverting shift count
				;6385		LONG,					;
				;6386		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 47E  0001,000A,279D,1000 L	;6387		LAST CYCLE				; decode next instruction (no overflow)
				;6388
;6389	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  200
; INTLOGADR.MIC 	     ASHQ										      /REV=
;															     INTLOG
;6390	.TOC	"	ASHQ"
;6391
;6392	;	This instruction shifts a quadword source operand left or right and stores
;6393	;	the result in the destination operand.
;6394	;
;6395	;	Mnemonic      Opcode	Operation				Spec	AT/DL		Dispatch
;6396	;	--------      ------	---------				----	-----		--------
;6397	;	ASHQ		79	dst.wl <-- src.rq shift cnt.rb		3	rrw/bql 	ASHQ..
;6398	;
;6399	;	Entry conditions:
;6400	;		source queue	=	cnt.rb operand
;6401	;					src.rq operand
;6402	;		dest queue	=	dst.wl result
;6403	;		branch queue	=	none
;6404	;		field queue	=	none
;6405	;		DL		=	LONG
;6406	;		Ibox state	=	running
;6407	;		Mbox state	=	running
;6408	;
;6409	;	Exit conditions:
;6410	;		The PSL condition codes are set.
;6411	;		The result has been stored in the destination memory location or register.
;6412	;
;6413	;	Condition codes:
;6414	;		N <-- dst lss 0
;6415	;		Z <-- dst eql 0
;6416	;		V <-- overflow		[Integer overflow trap enabled.]
;6417	;		C <-- 0
;6418	;
				;6419	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  201
; INTLOGADR.MIC 	     ASHQ										      /REV=
;															     INTLOG
				;6420
				;6421	;	ASHQ operation:
				;6422	;
				;6423	;		dst.wq <-- src.rq shift cnt.rb
				;6424
				;6425	ASHQ..:
				;6426		;********** Hardware dispatch **********;
				;6427		[W0] <-- PASSB [S2], LONG,		; save low src operand
				;6428		SC <-- A [S1],				; load shift count
E 13C  0000,804A,048A,0402 J 402;6429			sim cond [s3.sv]
				;6430
				;6431		;---------------------------------------;
				;6432		VA <-- NOT 000000[00],			; set VA = -1
				;6433		Q&, [W1] <-- PASSA [S1], LONG,		; test sign of, save hi src operand
				;6434		CASE [A.7-5] AT [ASHQ.LEFT.0.31],	; case on shift count<7:5>
E 402  AD82,6003,0880,4530 B 430;6435			sim cond k s3.[0]
				;6436
				;6437	;= ALIGNLIST 000x	(ASHQ.LEFT.0.31,	ASHQ.LEFT.32.63,
				;6438	;=			 ASHQ.LEFT.64.95,	ASHQ.LEFT.96.127,
				;6439	;=			 ASHQ.RIGHT.128.97,	ASHQ.RIGHT.96.65,
				;6440	;=			 ASHQ.RIGHT.64.33,	ASHQ.RIGHT.32.1)
				;6441
				;6442	ASHQ.LEFT.0.31:
				;6443		;---------------------------------------; 0 <= count <= 31:
				;6444		[DST] <-- [W0] LSH (SC), LONG,		; shift low source operand left by count
E 430  0001,4002,241D,0361 J 361;6445		SET PSL CC.IIII 			; set psl cc's, psl map is iiii
				;6446
				;6447		;---------------------------------------;
				;6448		Q&, [DST] <-- [W1]!![W0] LSH (SC),	; shift source operand left by count
				;6449		LONG,					;
				;6450		SET PSL CC.IIIP.QUAD,			; finish psl cc's from 2nd LW
E 361  0003,000A,242E,23F0 S 3F0;6451		CALL [ASHX.RESHIFT]			; shift back, sign extending
				;6452
				;6453		;---------------------------------------;
				;6454		[WBUS] <-- [Q] XOR [W1], LONG,		; compare unshifted original with
				;6455							;  sign-extended result
				;6456		SET PSL CC.PPJP,			; set overflow if they are not equal
E 362  0600,0010,20AE,9800 L	;6457		LAST CYCLE CHECK OVERFLOW		; decode next instruction
				;6458
				;6459
				;6460	;	One line subroutine for arithmetic shifts.
				;6461
				;6462	ASHX.RESHIFT:
				;6463		;---------------------------------------;
				;6464		Q <-- SEXT [Q] RSH (SC), LONG,		; shift back, sign extending
				;6465		RETURN, 				; return to caller
E 3F0  0003,8050,2390,0800 R	;6466			sim cond k s3.[0]
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  202
; INTLOGADR.MIC 	     ASHQ										      /REV=
;															     INTLOG
				;6467
				;6468	;	ASHQ, continued.
				;6469	;	Left shift in range [32:63].
				;6470
				;6471	;	At this point,
				;6472	;		W1'W0	=	source operand
				;6473	;		SC	=	shift count
				;6474
				;6475	ASHQ.LEFT.32.63:
				;6476		;---------------------------------------; 32 <= count <= 63:
				;6477		VA <-- NOT [W1],			; complement high src for neg test
E 432  0D80,4013,2710,0511 J 511;6478		[DST] <-- PASSA [K0], LONG		; low result is zero
				;6479
				;6480		;---------------------------------------;
				;6481		Q&, [DST] <-- [W0] LSH (SC), LONG,	; high result is low src shifted left
			    p201;6482		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 511  0003,4002,241D,23F0 S 3F0;6483		CALL [ASHX.RESHIFT]			; shift back, sign extending
				;6484
				;6485		;---------------------------------------;
				;6486		[W0] <-- [Q] XOR [W0], LONG,		; low src must equal reshifted result
E 512  E600,0008,04A0,4746 B 546;6487		CASE [A31.BQA.BNZ1] AT [ASHQ.LEFT.32.63.POS]	; case on sign of result
				;6488
				;6489	;= ALIGNLIST 011x	(ASHQ.LEFT.32.63.POS,	ASHQ.LEFT.32.63.NEG)
				;6490
				;6491	ASHQ.LEFT.32.63.POS:
				;6492		;---------------------------------------; a<31> = 0:
				;6493		[WBUS] <-- [W1] OR [W0], LONG,		; and high src must be zero
				;6494		SET PSL CC.PPJP,			; set psl.v if non-zero result
E 546  0500,0008,202E,9800 L	;6495		LAST CYCLE CHECK OVERFLOW		; decode next instruction
				;6496
				;6497	ASHQ.LEFT.32.63.NEG:
				;6498		;---------------------------------------; a<31> = 1:
				;6499		[WBUS] <-- [VA] OR [W0], LONG,		; and high src must be -1
				;6500		SET PSL CC.PPJP,			; set psl.v if non-zero result
E 54E  0500,0008,20BE,9800 L	;6501		LAST CYCLE CHECK OVERFLOW		; decode next instruction
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  203
; INTLOGADR.MIC 	     ASHQ										      /REV=
;															     INTLOG
				;6502
				;6503	;	ASHQ, continued.
				;6504	;	Left shift in range [64:127].
				;6505	;	Result is zero, check for overflow.
				;6506
				;6507	;	At this point,
				;6508	;		W1'W0	=	source operand
				;6509	;		SC	=	shift count
				;6510
				;6511	ASHQ.LEFT.64.95:
				;6512		;---------------------------------------; 64 <= count <= 95:
				;6513		[DST] <-- PASSB 000000[00], LONG,	; low result is zero
				;6514		SET PSL CC.IIII,			; set psl cc's, psl map is iii
E 434  0000,A002,240D,03F1 J 3F1;6515		GOTO [ASHQ.LEFT.64.127] 		; go write high result
				;6516
				;6517	ASHQ.LEFT.96.127:
				;6518		;---------------------------------------; 96 <= count <= 127:
				;6519		[DST] <-- PASSB 000000[00], LONG,	; low result is zero
				;6520		SET PSL CC.IIII,			; set psl cc's, psl map is iii
E 436  0000,A002,240D,03F1 J 3F1;6521		GOTO [ASHQ.LEFT.64.127] 		; go write high result
				;6522
				;6523	ASHQ.LEFT.64.127:
				;6524		;---------------------------------------;
			    p202;6525		Q&, [DST] <-- PASSB 000000[00], LONG,	; high result is zero
E 3F1  0002,A002,2400,0546 J 546;6526		GOTO [ASHQ.LEFT.32.63.POS]		; go test for overflow
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  204
; INTLOGADR.MIC 	     ASHQ										      /REV=
;															     INTLOG
				;6527
				;6528	;	ASHQ, continued.
				;6529	;	Right shift in range [-33:-128].
				;6530
				;6531	;	At this point,
				;6532	;		W1'W0	=	source operand
				;6533	;		SC	=	shift count
				;6534	;		VA	=	-1
				;6535	;		shifter sign =	set from source operand
				;6536
				;6537	ASHQ.RIGHT.128.97:
				;6538		;---------------------------------------; -128 <= count <= -97:
				;6539		[DST] <-- SEXT [W1] RSH [31.], LONG,	; result is sign
				;6540		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 438  0001,9F12,279D,03F2 J 3F2;6541		GOTO [ASHQ.RIGHT.EXIT]			; go write high result
				;6542
				;6543	ASHQ.RIGHT.96.65:
				;6544		;---------------------------------------; -96 <= count <= -65:
				;6545		[DST] <-- SEXT [W1] RSH [31.], LONG,	; result is sign
				;6546		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 43A  0001,9F12,279D,03F2 J 3F2;6547		GOTO [ASHQ.RIGHT.EXIT]			; go write high result
				;6548
				;6549	ASHQ.RIGHT.64.33:
				;6550		;---------------------------------------; -64 <= count <= -33:
				;6551		[DST] <-- SEXT [W1] RSH (32-SC),	; shift high src right, inverting shift count
				;6552		LONG,					;
E 43C  0001,0012,279D,03F2 J 3F2;6553		SET PSL CC.IIII 			; set psl cc's, psl map is iiii
				;6554
				;6555	ASHQ.RIGHT.EXIT:
				;6556		;---------------------------------------;
				;6557		[DST] <-- SEXT [W1] RSH [31.], LONG,	; high result is sign of source
E 3F2  0001,9F12,2790,1000 L	;6558		LAST CYCLE				; decode next instruction (no overflow)
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  205
; INTLOGADR.MIC 	     ASHQ										      /REV=
;															     INTLOG
				;6559
				;6560	;	ASHQ, continued.
				;6561	;	Right shift in range [-32:-1].
				;6562
				;6563	;	At this point,
				;6564	;		W1'W0	=	source operand
				;6565	;		SC	=	shift count
				;6566	;		VA	=	-1
				;6567	;		shifter sign =	set from source operand
				;6568
				;6569	ASHQ.RIGHT.32.1:
				;6570		;---------------------------------------; -32 <= count <= -1:
				;6571		[DST] <-- [W1]!![W0] RSH (32-SC),	; shift low src right, inverting shift count
				;6572		LONG,					;
				;6573		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 43E  E001,000A,242D,4737 B 437;6574		CASE [A31.BQA.BNZ1] AT [ASHQ.RIGHT.32.1.POS]	; case on sign of source operand
				;6575
				;6576	;= ALIGNLIST 011x	(ASHQ.RIGHT.32.1.POS,	ASHQ.RIGHT.32.1.NEG)
				;6577
				;6578	ASHQ.RIGHT.32.1.POS:
				;6579		;---------------------------------------; a<31> = 0:
				;6580		[DST] <-- [K0]!![W1] RSH (32-SC),	; shift high src right, inverting shift count
				;6581		LONG,					;
				;6582		SET PSL CC.IIIP.QUAD,			; finish psl cc's from 2nd LW
E 437  0001,0012,271E,1000 L	;6583		LAST CYCLE				; decode next instruction (no overflow)
				;6584
				;6585	ASHQ.RIGHT.32.1.NEG:
				;6586		;---------------------------------------; a<31> = 1:
				;6587		[DST] <-- [VA]!![W1] RSH (32-SC),	; shift high src right, inverting shift count
				;6588		LONG,					;
				;6589		SET PSL CC.IIIP.QUAD,			; finish psl cc's from 2nd LW
E 43F  0001,0012,24BE,1000 L	;6590		LAST CYCLE				; decode next instruction (no overflow)
				;6591
				;6592	;= END INTLOG
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  206
;    VFIELD.MIC 	     VFIELD.MIC -- Variable-Length Bit Field Instructions				      /REV=
;
				;6593	.TOC	"VFIELD.MIC -- Variable-Length Bit Field Instructions"
				;6594	.TOC	"Revision 1.1"
				;6595
				;6596	;	Dan Miner, Bob Supnik
				;6597
;6598	.nobin
;6599	;****************************************************************************
;6600	;*									    *
;6601	;*  COPYRIGHT (c) 1987, 1988, 1989, 1990, 1991, 1992 BY 		    *
;6602	;*  DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASSACHUSETTS.		    *
;6603	;*  ALL RIGHTS RESERVED.						    *
;6604	;*									    *
;6605	;*  THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED   *
;6606	;*  ONLY IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE   *
;6607	;*  INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE OR ANY  OTHER   *
;6608	;*  COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY   *
;6609	;*  OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE IS  HEREBY   *
;6610	;*  TRANSFERRED.							    *
;6611	;*									    *
;6612	;*  THE INFORMATION IN THIS SOFTWARE IS  SUBJECT TO CHANGE WITHOUT NOTICE   *
;6613	;*  AND  SHOULD  NOT  BE  CONSTRUED AS	A COMMITMENT BY DIGITAL EQUIPMENT   *
;6614	;*  CORPORATION.							    *
;6615	;*									    *
;6616	;*  DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE  OR  RELIABILITY OF ITS   *
;6617	;*  SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.		    *
;6618	;*									    *
;6619	;****************************************************************************
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  207
;    VFIELD.MIC 	     Revision History									      /REV=
;
;6620	.TOC	"	Revision History"
;6621
;6622	; Edit	  Date	 Who	     Description
;6623	; ---- --------- ---	---------------------
;6624	;    1 28-Jan-91 GMU	Symptom: Ibox CSU deadlock can occur if the field
;6625	;				 queue is referenced before all source queue
;6626	;				 entries corresponding to earlier specifiers
;6627	;				 are referenced.
;6628	;			Cure:	 Modify the FIELD.. and INSV.. entry points to
;6629	;				 remove the source queue entries corresponding
;6630	;				 to the specifiers before the field specifier
;6631	;				 before casing on the field queue.  To avoid
;6632	;				 changing the IROM also, the original field queue
;6633	;				 entry point constraints remain in ALIGN.MIC,
;6634	;				 but are no longer used.
;6635	; (1)0 18-Jul-90 GMU	Initial production microcode.
;6636	;
;6637	; Begin version 1.0 here
;6638	;   14 17-Jul-90 GMU	Update with Bob's review comments.
;6639	;   13 05-Jun-90 GMU	Update SEQ.COND names to match implementation.
;6640	;   12 21-May-90 DGM	Fix bug in FIELD.M path - check for 2nd read incorrect
;6641	;   11 03-May-90 GMU	Reverse order of duplicate labels so that the one
;6642	;			included in an ALIGNLIST is last.
;6643	;   10 26-Apr-90 GMU	Convert '*' fill constraints to 'x' constraints.
;6644	;    9 21-Mar-90 DGM	Update comments
;6645	;    8 09-Feb-90 DGM	Remove VIELD.P type SEQ.COND from INSV
;6646	;    7 04-Feb-90 GMU	Document simultaneous reference restrictions.
;6647	;    6 30-Jan-90 DGM	Remove VIELD.P type SEQ.COND from FIELD instructions
;6648	;    5 16-Jan-90 DGM	Change field queue alignment
;6649	;    4 18-Sep-89 GMU	Correct PSL CCs for FFx which finds no bits.
;6650	;    3 24-Aug-89 GMU	Fix bad shift count for INSV.
;6651	;    2 17-Aug-89 GMU	Convert split dispatch to use field queue.
;6652	;    1	4-May-88 SDP	Fix FIELD.M bug for 0 SIZE case.  Added S1 access on exit path.
;6653	; (0)0 10-Sep-87 RMS	Trial microcode.
;6654
				;6655	.bin
				;6656	;= BEGIN VFIELD
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  208
;    VFIELD.MIC 	     Revision History									      /REV=
;															     VFIELD
				;6657
;6658	.nobin
;6659	;	This module implements the variable-length bit field class instructions.
;6660	;	The instructions in this class are:
;6661	;
;6662	;	Opcode	 Instruction							N Z V C 	Exceptions
;6663	;	------	 -----------							------- 	----------
;6664	;
;6665	;	EC	 CMPV pos.rl, size.rb, base.vb, {field.rv}, src.rl		* * 0 * 	rsv
;6666	;	ED	 CMPZV pos.rl, size.rb, base.vb, {field.rv}, src.rl		* * 0 * 	rsv
;6667	;
;6668	;	EE	 EXTV pos.rl, size.rb, base.vb, {field.rv}, dst.wl		* * 0 - 	rsv
;6669	;	EF	 EXTZV pos.rl, size.rb, base.vb, {field.rv}, dst.wl		* * 0 - 	rsv
;6670	;
;6671	;	EB	 FFC startpos.rl, size.rb, base.vb, {field.rv}, findpos.wl	0 * 0 0 	rsv
;6672	;	EA	 FFS startpos.rl, size.rb, base.vb, {field.rv}, findpos.wl	0 * 0 0 	rsv
;6673	;
;6674	;	F0	 INSV src.rl, pos.rl, size.rb, base.vb, {field.wv}		- - - - 	rsv
;6675	;
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  209
;    VFIELD.MIC 	     Revision History									      /REV=
;															     VFIELD
;6676
;6677	;					CAUTION
;6678	;					-------
;6679	;
;6680	;	Ebox microcode for any instruction whose IROM entry contains a .ax or
;6681	;	.vx specifier followed immediately by a .rx, .mx, or .vx specifier may not
;6682	;	reference the source queue entries for this pair of specifiers in the
;6683	;	same microinstruction.	This restriction is necessary to avoid getting
;6684	;	the incorrect operand data for the second specifier of the pair if the
;6685	;	first specifier of the pair is auto-increment, auto-decrement, or auto-increment
;6686	;	deferred, and the second specifier of the pair is register mode using the
;6687	;	same register specified for the first specifier of the pair.  Because the Ibox
;6688	;	must write both the address operand to the MD, and the auto-inc/dec value
;6689	;	to the GPR, the Ebox may read the old value of the GPR if both specifiers
;6690	;	are referenced in the same microword.  In addition, a simultaneous reference
;6691	;	to these specifiers may cause an infinite Ibox RXS stall if the source
;6692	;	queue retire for the second GPR specifier arrives at the Ibox before
;6693	;	the scoreboard is incremented.
;6694	;
;6695	;	This restriction does not apply if, by context, it is known that the
;6696	;	second specifier of the pair is not register mode.
;6697	;
;6698	;	Several of the instructions processed by this module are affected by this
;6699	;	restriction.  The following table lists the restriction for each instruction using
;6700	;	the notation [spec n; spec n+1] to denote a restriction in referencing the
;6701	;	source queue entries for these two specifiers in the same microinstruction.
;6702	;
;6703	;	Entry Point   Opcode   Mnemonic 		   Restriction
;6704	;	-----------   ------   -------- 	----------------------------------
;6705	;	FIELD.. 	EA	 FFS		none
;6706	;			EB	 FFC		none
;6707	;			EC	 CMPV		[spec 3; spec 4]
;6708	;			ED	 CMPZV		[spec 3; spec 4]
;6709	;			EE	 EXTV		none
;6710	;			EF	 EXTZV		none
;6711	;
;6712	;	INSV..		F0	 INSV		none
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  210
;    VFIELD.MIC 	     FFS, FFC, CMPV, CMPZV, EXTV, EXTZV 						      /REV=
;															     VFIELD
;6713	.TOC	"	FFS, FFC, CMPV, CMPZV, EXTV, EXTZV"
;6714
;6715	;	These instructions find the first set/clear bit in, compare an operand to, or
;6716	;	extract, a variable-length bit field.
;6717	;
;6718	;	Mnemonic      Opcode	Operation				Spec	AT/DL			Dispatch
;6719	;	--------      ------	---------				----	-----			--------
;6720	;	FFS		EA	dst.wl <-- first one in 		4	rrv{r2}w/lbbl		FIELD..
;6721	;					field(pos.rl, size.rb, base.vb)
;6722	;	FFC		EB	dst.wl <-- first zero in		4	rrv{r2}w/lbbl		FIELD..
;6723	;					field(pos.rl, size.rb, base.vb)
;6724	;
;6725	;	CMPV		EC	sext{field(pos.rl, size.rb, base.vb)} - 4	rrv{r2}r/lbbl		FIELD..
;6726	;					src2.rl
;6727	;	CMPZV		ED	zext{field(pos.rl, size.rb, base.vb)} - 4	rrv{r2}r/lbbl		FIELD..
;6728	;					src2.rl
;6729	;
;6730	;	EXTV		EE	dst.wl <--				4	rrv{r2}w/lbbl		FIELD..
;6731	;					sext{field(pos.rl, size.rb, base.vb)}
;6732	;	EXTZV		EF	dst.wl <--				4	rrv{r2}w/lbbl		FIELD..
;6733	;					zext{field(pos.rl, size.rb, base.vb)}
;6734	;
;6735	;	Entry conditions:		(CMPV, CMPZV)				(FFS, FFC, EXTV, EXTZV)
;6736	;		source queue	=	pos.rl operand				pos.rl operand
;6737	;					size.rb operand 			size.rb operand
;6738	;					base.rq operand, if register or 	base.rq operand, if register or
;6739	;					base.ab operand, if memory		base.ab operand, if memory
;6740	;					src2.rl
;6741	;		dest queue	=	none					dst.wl
;6742	;		branch queue	=	none
;6743	;		field queue	=	one valid entry for third operand
;6744	;		DL		=	BYTE
;6745	;		Ibox state	=	running
;6746	;		Mbox state	=	stopped
;6747	;
;6748	;	Exit conditions (EXTV, EXTZV, FFS, FFC):
;6749	;		The PSL condition codes are set.
;6750	;		The result has been stored in the destination memory location or register.
;6751	;	Exit conditions (CMPV, CMPZV):
;6752	;		The PSL condition codes are set.
;6753	;
;6754	;	Condition codes:
;6755	;		(FFS, FFC)		(CMPV, CMPZV)		(EXTV, EXTZV)
;6756	;		N <-- 0 		N <-- field LSS src2	N <-- dst LSS 0
;6757	;		Z <-- {bit not found}	Z <-- field EQL src2	Z <-- dst EQL 0
;6758	;		V <-- 0 		V <-- 0 		V <-- 0 	[Integer overflow trap disabled.]
;6759	;		C <-- 0 		C <-- field LSSU src2	C <-- C
;6760	;
;6761	;	Notes:
;6762	;		1.  Memory management:	The source list is emptied (except for CMPxV src2) before
;6763	;		    the field is accessed.
;6764	;		2.  The IROM sets DL to BYTE for the FIELD dispatches.
;6765	;
				;6766	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  211
;    VFIELD.MIC 	     FFS, FFC, CMPV, CMPZV, EXTV, EXTZV 						      /REV=
;															     VFIELD
				;6767
				;6768	;	FFS, FFC operation:
				;6769	;
				;6770	;		dst.wl <-- pos of first one (zero) bit in field(pos.rl, size.rb, base.vb)
				;6771
				;6772	;	CMPV, CMPZV operation:
				;6773	;
				;6774	;		sext (zext){field(pos.rl, size.rb, base.vb)} - src2.rl
				;6775
				;6776	;	EXTV, EXTZV operation:
				;6777	;
				;6778	;		dst.wl <-- sext (zext){field(pos.rl, size.rb, base.vb)}
				;6779	;
				;6780	;	Note: In pass 1 microcode, the microcode case on the field queue entry
				;6781	;	is done at the entry point of this instruction, and the field queue
				;6782	;	alignment constraints are done in ALIGN.MIC.  In pass 2 microcode, the
				;6783	;	field queue case is moved into the body of the instruction itself.
				;6784	;	To avoid having to change the IROM, the original field queue constraint
				;6785	;	was not removed from ALIGN.MIC.
				;6786	;
				;6787	;	CAUTION: Do not change the order of reference to the
				;6788	;	source queue in the entry point below without
				;6789	;	reading the explanation at the beginning of this module.
				;6790	;
				;6791	;	The following simultaneous reference restriction exists for
				;6792	;	this entry point: [spec 3; spec 4].
				;6793
				;6794	FIELD..:
				;6795		;********** Hardware dispatch **********; obsolete fq.vr constraint in ALIGN.MIC
				;6796		[W2] <-- B [S2], LEN(DL),		; [1] save zext(size)
E 266  0082,404C,0C80,059E J 59E;6797		Q <-- PASSA [S1]			; save position
				;6798
				;6799	;= ALIGNLIST 100x	(FIELD.MEM,		FIELD.RMODE,
				;6800	;=					,	FIELD.INVALID)
				;6801
				;6802	FIELD.INVALID:
				;6803		;---------------------------------------; fq.vr = 11 (invalid)
			    p214;6804		[WBUS] <-- [W2], LEN(DL),		; [2] re-test size for zero
E 59E  4000,0004,2030,5298 B 598;6805		CASE [FQ.VR] AT [FIELD.MEM]		; wait for field queue to
				;6806							; indicate register or memory
				;6807
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  212
;    VFIELD.MIC 	     FFS, FFC, CMPV, CMPZV, EXTV, EXTZV 						      /REV=
;															     VFIELD
				;6808
				;6809	;	Field in registers.
				;6810
				;6811	;	NOTE: DL is set to BYTE for this flow
				;6812
				;6813	FIELD.RMODE:
				;6814		;---------------------------------------; fq.vr = 01 (valid, register)
				;6815		[WBUS] <-- [W2] - 000000[33.], LONG,	; [3] test size > 32
E 59A  0A80,2108,2034,8022 J 022;6816		RESTART MBOX				; resume operand processing
				;6817
				;6818		;---------------------------------------;
				;6819		VA <-- [Q] ANDNOT 000000[1F], LONG,	; [4] test pos > 31
				;6820		[W0] <-- PASSA [Q],			; save pos
				;6821		SC <-- A [Q],				; load position into SC
E 022  2480,60FB,04AA,415B B 05B;6822		CASE [ALU.NZV] AT [FIELD.R.SIZE.NOT.ZERO] ; case on size = 0 from [2]
				;6823
				;6824	;= ALIGNLIST 10xx	(FIELD.R.SIZE.NOT.ZERO, FIELD.R.SIZE.ZERO)
				;6825	;  ALU.NZVC set by move --> V = C = 0
				;6826
				;6827	FIELD.R.SIZE.NOT.ZERO:
				;6828		;---------------------------------------; alu.z = 0 (size not zero)
				;6829		[W4] <-- [S2]!![S1] RSH (SC), LONG,	; [5] right justify source field,
			    p213;6830							;     sc = position
E 05B  2001,8042,1490,4136 B 036;6831		CASE [ALU.NZV] AT [FIELD.R.SIZE.TOO.BIG] ; case on size > 32 from [3]
				;6832							; >> no [spec 3; spec 4] reference
				;6833	;= ALIGNLIST 011x	(FIELD.R.SIZE.TOO.BIG,	FIELD.R.SIZE.OK)
				;6834
				;6835	FIELD.R.SIZE.OK:
				;6836		;---------------------------------------; alu.n = 1 (size <= 32)
				;6837		SC <-- A [W2],				; [6] load size as shift count
			    p213;6838		[SC] <-- 000000[32.] - [W2], LONG,	; load 32-size as DEFERRED shif count
E 03E  2A00,2100,D43A,4169 B 069;6839		CASE [ALU.NZV] AT [FIELD.R.POS.TOO.BIG] ; case on pos > 31 from [4]
				;6840
				;6841	;= ALIGNLIST 10xx	(FIELD.R.POS.TOO.BIG,	FIELD.R.POS.OK)
				;6842	;  ALU.NZVC set by ANDNOT --> V = 0
				;6843
				;6844	FIELD.R.POS.OK:
				;6845		;---------------------------------------; alu.z = 1 (pos <= 31)
				;6846		[W4] <-- [W4] RROT (SC), LONG,		; [7] left justify field,
			    p216;6847							;     sc = size
E 06D  8001,802A,1450,4CD0 B 0D0;6848		CASE [OPCODE.2-0] AT [FIELD.DATA.CASE]	; case on opcode
				;6849
				;6850
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  213
;    VFIELD.MIC 	     FFS, FFC, CMPV, CMPZV, EXTV, EXTZV 						      /REV=
;															     VFIELD
				;6851
				;6852	;	Field in registers, continued.
				;6853	;	These are the special cases for field in register.
				;6854
				;6855	FIELD.R.SIZE.ZERO:
				;6856		;---------------------------------------; alu.z = 1 (size = 0)
				;6857		ACCESS A [S1], ACCESS B [S2],		; [5] chuck source operand
			    p221;6858		[W4] <-- 0, LONG,			; extracted field is zero
E 05F  8000,C04A,1480,4C33 B 033;6859		CASE [OPCODE.2-0] AT [FIELD.ZERO.CASE]	; case on opcode
				;6860
				;6861	FIELD.R.SIZE.TOO.BIG:
			    p127;6862		;---------------------------------------; alu.n = 0 (size > 32)
E 036  0000,0000,2000,003C J 03C;6863		RESERVED OPERAND FAULT			; reserved operand fault
				;6864
				;6865	FIELD.R.POS.TOO.BIG:
				;6866		;---------------------------------------; alu.z = 0 (pos > 31)
			    p127;6867							; pos > 31, size > 0, size <= 32:
E 069  0000,0000,2000,003C J 03C;6868		RESERVED OPERAND FAULT			; reserved operand fault
				;6869
				;6870
				;6871	;	These are the special cases for field in memory.
				;6872
				;6873	FIELD.M.SIZE.TOO.BIG:
			    p127;6874		;---------------------------------------; alu.c = 0 (size > 32)
E 04D  0000,0000,2000,003C J 03C;6875		RESERVED OPERAND FAULT			; reserved operand fault
				;6876
				;6877	FIELD.M.SIZE.ZERO:
				;6878		;---------------------------------------; alu.z = 1 (size = 0)
				;6879		[W4] <-- 000000[00], LONG,		; [5] extracted field is zero
				;6880		ACCESS A [S1],				; chuck base operand
			    p221;6881		RESTART MBOX,				; resume operand processing
E 07D  8080,2000,1484,CC33 B 033;6882		CASE [OPCODE.2-0] AT [FIELD.ZERO.CASE]	; field is zero, case on opcode
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  214
;    VFIELD.MIC 	     FFS, FFC, CMPV, CMPZV, EXTV, EXTZV 						      /REV=
;															     VFIELD
				;6883
				;6884	;	Field in memory.
				;6885
				;6886	;	NOTE: DL is set to BYTE for this flow
				;6887
				;6888	FIELD.MEM:
				;6889		;---------------------------------------; fq.vr = 00 (valid, memory)
E 598  0A00,2100,1830,0031 J 031;6890		[W5] <-- 000000[32.] - [W2], LONG	; [3] test size > 32
				;6891
				;6892		;---------------------------------------;
				;6893		[W0] <-- B [Q], LONG,			; [4] save position
				;6894		Q <-- SEXT [Q] RSH [3], 		; calc byte position
E 031  2083,8350,0790,4179 B 079;6895		CASE [ALU.NZV] AT [FIELD.M.SIZE.NOT.ZERO] ; case on size = 0 from [2]
				;6896
				;6897	;= ALIGNLIST 10xx	(FIELD.M.SIZE.NOT.ZERO, FIELD.M.SIZE.ZERO)
				;6898	;  ALU.NZVC set by move --> V = C = 0
				;6899
				;6900	FIELD.M.SIZE.NOT.ZERO:
				;6901		;---------------------------------------; alu.z = 0 (size not zero)
				;6902		[W3] <-- [S1] + [Q], LONG,		; [5] calc, save base + sext byte position
				;6903		Q <-- [S1] LSH [3],			; calc base * 8
			    p213;6904							; >> no [spec 3; spec 4] reference
E 079  4883,4350,1080,424D B 04D;6905		CASE [ALU.NZC] AT [FIELD.M.SIZE.TOO.BIG] ; case on size > 32 from [3]
				;6906
				;6907	;= ALIGNLIST 110x	(FIELD.M.SIZE.TOO.BIG,	FIELD.M.SIZE.OK)
				;6908
				;6909	FIELD.M.SIZE.OK:
				;6910		;---------------------------------------; alu.c = 1 (size <= 32)
				;6911		VA <-- [W3] ANDNOT 000000[03],		; [6] calc longword aligned base address
			    p215;6912		[W4] <-- MEM (VA), LONG,		; read field surround
E 04F  04C0,2019,1440,0262 J 262;6913			sim addr [field]
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  215
;    VFIELD.MIC 	     FFS, FFC, CMPV, CMPZV, EXTV, EXTZV 						      /REV=
;															     VFIELD
				;6914
				;6915	;	Field in memory, continued.
				;6916	;	Continue field extraction.
				;6917
				;6918	;	At this point,
				;6919	;		W0	=	position
				;6920	;		W2	=	zext size
				;6921	;		W3	=	base + sext byte position
				;6922	;		W4	=	low longword of field surround
				;6923	;		W5	=	32 - size
				;6924	;		Q	=	base * 8
				;6925	;		VA	=	field address, longword aligned
				;6926
				;6927	FIELD.R:					; Dummy label
				;6928		;---------------------------------------; obsolete fq.vr constraint in ALIGN.MIC
E 262  0880,0008,08A0,0260 J 260;6929		[W1] <-- [Q] + [W0], LONG		; [7] base * 8 + pos
				;6930
				;6931	FIELD.M:					; Dummy label
				;6932		;---------------------------------------; obsolete fq.vr constraint in ALIGN.MIC
E 260  0400,20F8,0820,0026 J 026;6933		[W1] <-- [W1] AND 000000[1F], LONG	; [8] base * 8 + pos mod 32 = aligned pos
				;6934
				;6935		;---------------------------------------;
			    p276;6936		[W1] <-- [W5] - [W1], LONG,		; [9] 32-size-pos = 32-(pos+size)
E 026  0A80,0010,0860,2497 S 497;6937		CALL [WAIT.ONE.CYCLE]			; [10] wait for alu cc's
				;6938
				;6939		;---------------------------------------;
				;6940		SC <-- A [W1],				; [11] load 32-(pos+size) as shift count
			    p216;6941		[SC] <-- B [W5], LONG,			; load 32-size as DEFERRED shift count
E 027  4080,0030,D42A,424C B 04C;6942		CASE [ALU.NZC] AT [FIELD.M.2]		; case on pos + size <= 32 from [9]
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  216
;    VFIELD.MIC 	     FFS, FFC, CMPV, CMPZV, EXTV, EXTZV 						      /REV=
;															     VFIELD
				;6943
				;6944	;	Field in memory, continued.
				;6945	;	First longword read, read second if required, left align field.
				;6946
				;6947	;	At this point,
				;6948	;		W0	=	position
				;6949	;		W1	=	32-(pos+size)
				;6950	;		W2	=	zext size
				;6951	;		W4	=	low longword of field
				;6952	;		W5	=	32-size
				;6953	;		VA	=	field address, longword aligned
				;6954	;		SC	=	32-(pos+size) in first cycle, 32-size in second cycle
				;6955
				;6956	;= ALIGNLIST 110x	(FIELD.M.2,		FIELD.M.1)
				;6957
				;6958	;	Field in single aligned longword
				;6959
				;6960	FIELD.M.1:
				;6961		;---------------------------------------; alu.c = 1 (pos + size <= 32)
				;6962		[W4] <-- [W4] LSH (SC), LONG,		; [12] left justify field for single word case
				;6963							;      sc = 32-(pos+size)
				;6964		RESTART MBOX,				; resume operand processing
E 04E  8001,4002,1454,CCD0 B 0D0;6965		CASE [OPCODE.2-0] AT [FIELD.DATA.CASE]	; case on opcode
				;6966
				;6967	;	Field in two adjacent aligned longwords
				;6968
				;6969	FIELD.M.2:
				;6970		;---------------------------------------; alu.c = 0 (pos + size > 32)
				;6971		VA <-- [VA] + 4,			; [12] point to next longword
				;6972		[W5] <-- MEM (VA), LONG,		; read next longword
E 04C  0C42,8031,18B0,03F3 J 3F3;6973		Q <-- PASSB [W5]			; save 32-size
				;6974
				;6975		;---------------------------------------;
				;6976		SC <-- A [W1], LONG,			; [13] load 32-(pos+size) as shift count
E 3F3  0080,0050,D42A,00D0 J 0D0;6977		[SC] <-- B [Q]				; load 32-size as DEFERRED shift count
				;6978
				;6979	FIELD.DATA.CASE:				; dummy label
				;6980		;---------------------------------------;
				;6981		[W4] <-- [W5]!![W4] LSH (SC), LONG,	; [14] left align field
				;6982							;      sc = 32-(pos+size)
				;6983		RESTART MBOX,				; resume operand processing
E 0D0  8001,002A,1464,CCD0 B 0D0;6984		CASE [OPCODE.2-0] AT [FIELD.DATA.CASE]	; case on opcode
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  217
;    VFIELD.MIC 	     FFS, FFC, CMPV, CMPZV, EXTV, EXTZV 						      /REV=
;															     VFIELD
				;6985
				;6986	;	Zero length field.
				;6987	;	Finish instruction and exit.
				;6988
				;6989	;	At this point,
				;6990	;		W0	=	position
				;6991	;		W4	=	extracted field (zero)
				;6992	;		S1	=	fourth source operand (CMPXV)
				;6993
				;6994	;= ALIGNLIST 001x	(FIELD.ZERO.CASE,	FFX.0,
				;6995	;=			 CMPXV.0,		EXTXV.0)
				;6996
				;6997	FFX.0:
				;6998		;---------------------------------------; FFx:
E 037  0000,0000,2410,03F4 J 3F4;6999		[DST] <-- [W0], LONG			; write position to destination
				;7000
				;7001	FFX.0.EXIT:
				;7002		;---------------------------------------;
				;7003		[WBUS] <-- [K0], LONG,			; set alu z bit
				;7004		SET PSL CC.IIII,			; and PSL CCs
E 3F4  0000,0000,231D,1000 L	;7005		LAST CYCLE				; decode next instruction
				;7006
				;7007	CMPXV.COMPARE:
				;7008	CMPXV.0:
				;7009		;---------------------------------------; CMPxV:
				;7010		[WBUS] <-- [W4] - [S1], LONG,		; compare field to source operand
				;7011		SET PSL CC.JIZJ,			; set psl cc's, psl map is jizj
E 03B  0A80,0040,205C,9000 L	;7012		LAST CYCLE				; decode next instruction
				;7013
				;7014	EXTXV.0:
				;7015		;---------------------------------------; EXTxV:
				;7016		[DST] <-- 000000[00], LONG,		; field is zero
				;7017		SET PSL CC.IIIP,			; set psl cc's, default map is iiip
E 03F  0080,2000,240C,1000 L	;7018		LAST CYCLE				; decode next instruction.
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  218
;    VFIELD.MIC 	     FFS, FFC, CMPV, CMPZV, EXTV, EXTZV 						      /REV=
;															     VFIELD
				;7019
				;7020	;	Non-zero length field.
				;7021	;	CMPV, CMPZV completion.
				;7022
				;7023	;	At this point,
				;7024	;		W0	=	position
				;7025	;		W2	=	zext size
				;7026	;		W4	=	left justified field
				;7027	;		SC	=	32 - size
				;7028	;		shifter sign =	set from left justified field
				;7029
				;7030	;	To complete CMPV, CMPZV:
				;7031	;		sign/zero extend field,
				;7032	;		compare, set condition codes, and decode.
				;7033
				;7034	;= ALIGNLIST 000x	(FIELD.DATA.CASE,	,
				;7035	;=			 FFS,			 FFC,
				;7036	;=			 CMPV,			 CMPZV,
				;7037	;=			 EXTV,			 EXTZV)
				;7038
				;7039	CMPV:
				;7040		;---------------------------------------; opcode<2:0> = 100:
			    p217;7041		[W4] <-- SEXT [W4] RSH (SC), LONG,	; right justify and sign extend field
E 0D8  0001,802A,1790,003B J 03B;7042		GOTO [CMPXV.COMPARE]			; go finish compare
				;7043
				;7044	CMPZV:
				;7045		;---------------------------------------; opcode<2:0> = 101:
			    p217;7046		[W4] <-- ZEXT [W4] RSH (SC), LONG,	; right justify and zero extend field
E 0DA  0001,C02A,1400,003B J 03B;7047		GOTO [CMPXV.COMPARE]			; go finish compare
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  219
;    VFIELD.MIC 	     FFS, FFC, CMPV, CMPZV, EXTV, EXTZV 						      /REV=
;															     VFIELD
				;7048
				;7049	;	EXTV, EXTZV completion.
				;7050
				;7051	;	At this point,
				;7052	;		W0	=	position
				;7053	;		W2	=	zext size
				;7054	;		W4	=	left justified field
				;7055	;		SC	=	32 - size
				;7056	;		shifter sign =	set from left justified field
				;7057	;
				;7058	;	To complete EXTV, EXTZV:
				;7059	;		sign/zero extend field,
				;7060	;		write field to dst.wl and decode.
				;7061
				;7062	EXTV:
				;7063		;---------------------------------------; opcode<2:0> = 110:
				;7064		[DST] <-- SEXT [W4] RSH (SC), LONG,	; right justify and sign extend field
				;7065		SET PSL CC.IIIP,			; set psl cc's, default map is iiip
E 0DC  0001,802A,279C,1000 L	;7066		LAST CYCLE				; decode next instruction
				;7067
				;7068	EXTZV:
				;7069		;---------------------------------------; opcode<2:0> = 111:
				;7070		[DST] <-- ZEXT [W4] RSH (SC), LONG,	; right justify and zero extend field
				;7071		SET PSL CC.IIIP,			; set psl cc's, default map is iiip
E 0DE  0001,C02A,240C,1000 L	;7072		LAST CYCLE				; decode next instruction
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  220
;    VFIELD.MIC 	     FFS, FFC, CMPV, CMPZV, EXTV, EXTZV 						      /REV=
;															     VFIELD
				;7073
				;7074	;	FFS, FFC completion.
				;7075
				;7076	;	At this point,
				;7077	;		W0	=	position
				;7078	;		W2	=	zext size
				;7079	;		W4	=	left justified field
				;7080	;		SC	=	32 - size
				;7081	;		shifter sign =	set from left justified field
				;7082	;
				;7083	;	To complete FFS, FFC:
				;7084	;		if FFC, invert field so can use FFS algorithm,
				;7085	;		zero extend field,
				;7086	;		if field is zero, calculate answer and write result,
				;7087	;		otherwise, find first one bit in field, write result.
				;7088
				;7089	FFC:
				;7090		;---------------------------------------; opcode<2:0> = 010:
E 0D6  0D80,0028,1400,00D4 J 0D4;7091		[W4] <-- NOT [W4], LONG 		; complement 1's and 0's
				;7092
				;7093	FFS:
				;7094		;---------------------------------------; opcode<2:0> = 011:
E 0D4  0001,C02A,0800,03F5 J 3F5;7095		[W1] <-- ZEXT [W4] RSH (SC), LONG	; right justify and zero extend field
				;7096
				;7097	;	The upcoming bit search can only fail if (FFS) field = 00..00 (FFC) field = 11..11.
				;7098	;	In FFC, the field is complemented BEFORE right shifting.  Garbage to the right of
				;7099	;	the field is shifted off, and zeros are shifting in, causing the zero test to work.
				;7100
				;7101		;---------------------------------------;
E 3F5  0003,5000,2020,0522 J 522;7102		Q <-- [W1] LSH [16.], LONG		; shift field <13:0> to <29:16> for MPU
				;7103
				;7104		;---------------------------------------;
				;7105		[W3] <-- [W1] LSH [2.], LONG,		; shift field <27:14> to <29:16> for MPU
			    p221;7106		MPU <-- B.29..16 [Q],			; load MPU with field <13:0>
E 522  E001,4252,102A,CF9B B 59B;7107		CASE [SHF.NZ.INT] AT [FF.NOT.ZERO]	; if field not zero, go find first set bit
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  221
;    VFIELD.MIC 	     FFS, FFC, CMPV, CMPZV, EXTV, EXTZV 						      /REV=
;															     VFIELD
				;7108
				;7109	;	FFx, continued.
				;7110	;	Prepare to search field.
				;7111
				;7112	;	At this point,
				;7113	;		W0	=	position
				;7114	;		W1	=	field
				;7115	;		W2	=	size (zero extended)
				;7116	;		W3	=	field left shifted 2
				;7117	;		MPU	=	field<13:0>, not yet testable
				;7118
				;7119	;= ALIGNLIST 101x	(FF.NOT.ZERO,	FF.ZERO)
				;7120
				;7121	FF.ZERO:
				;7122		;---------------------------------------; shf.z = 1:
			    p217;7123		[DST] <-- [W0] + [W2], LONG,		; position is initial position + size
E 59F  0880,0018,2410,03F4 J 3F4;7124		GOTO [FFX.0.EXIT]			; go set psl.z, decode next instruction
				;7125
				;7126	FF.NOT.ZERO:
				;7127		;---------------------------------------; alu.z = 0:
				;7128		[W4] <-- [K1]!![W1] RSH [12.], LONG,	; shift field <31:28> to <19:16> for MPU
				;7129							; add guard 1 for paranoia
E 59B  0001,8C12,172D,0033 J 033;7130		SET PSL CC.IIII 			; set psl cc's, psl map is iiii
				;7131
				;7132	FIELD.ZERO.CASE:				; dummy label
				;7133		;---------------------------------------;
			    p222;7134		MPU <-- B.29..16 [W3],			; load MPU with field <27:14>
E 033  0000,0020,200A,C8C0 B 0C0;7135		CASE [MPU.0-6] AT [FF.0_6.0]		; case on previous mask<6:0>
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  222
;    VFIELD.MIC 	     FFS, FFC, CMPV, CMPZV, EXTV, EXTZV 						      /REV=
;															     VFIELD
				;7136
				;7137	;	FFx, continued.
				;7138	;	Search field 14 bits at a time to find set bit.
				;7139
				;7140	;	At this point,
				;7141	;		W0	=	position
				;7142	;		W4	=	1'field<31:28> in <20:16>
				;7143	;		MPU	=	field <27:14>, not yet testable for 2 cycles
				;7144
				;7145	;= ALIGNLIST 000x	(FF.0_6.0,	FF.0_6.1,	FF.0_6.2,	FF.0_6.3,
				;7146	;=			 FF.0_6.4,	FF.0_6.5,	FF.0_6.6,	FF.0_6.NEXT)
				;7147
				;7148	FF.0_6.0:
				;7149		;---------------------------------------; mask<0> = 1:
				;7150		[DST] <-- [W0] + 000000[00], LONG,	; store result = position + 0
E 0C0  0880,2000,2410,1000 L	;7151		LAST CYCLE				; decode next instruction
				;7152
				;7153	FF.0_6.1:
				;7154		;---------------------------------------; mask<1> = 1:
				;7155		[DST] <-- [W0] + 000000[01], LONG,	; store result = position + 1
E 0C2  0880,2008,2410,1000 L	;7156		LAST CYCLE				; decode next instruction
				;7157
				;7158	FF.0_6.2:
				;7159		;---------------------------------------; mask<2> = 1:
				;7160		[DST] <-- [W0] + 000000[02], LONG,	; store result = position + 2
E 0C4  0880,2010,2410,1000 L	;7161		LAST CYCLE				; decode next instruction
				;7162
				;7163	FF.0_6.3:
				;7164		;---------------------------------------; mask<3> = 1:
				;7165		[DST] <-- [W0] + 000000[03], LONG,	; store result = position + 3
E 0C6  0880,2018,2410,1000 L	;7166		LAST CYCLE				; decode next instruction
				;7167
				;7168	FF.0_6.4:
				;7169		;---------------------------------------; mask<4> = 1:
				;7170		[DST] <-- [W0] + 000000[04], LONG,	; store result = position + 4
E 0C8  0880,2020,2410,1000 L	;7171		LAST CYCLE				; decode next instruction
				;7172
				;7173	FF.0_6.5:
				;7174		;---------------------------------------; mask<5> = 1:
				;7175		[DST] <-- [W0] + 000000[05], LONG,	; store result = position + 5
E 0CA  0880,2028,2410,1000 L	;7176		LAST CYCLE				; decode next instruction
				;7177
				;7178	FF.0_6.6:
				;7179		;---------------------------------------; mask<6> = 1:
				;7180		[DST] <-- [W0] + 000000[06], LONG,	; store result = position + 6
E 0CC  0880,2030,2410,1000 L	;7181		LAST CYCLE				; decode next instruction
				;7182
				;7183	FF.0_6.NEXT:
				;7184		;---------------------------------------; mask<6:0> = 0:
			    p223;7185		[W0] <-- [W0] + 000000[14.], LONG,	; assume search continues
E 0CE  2880,2070,0410,49C1 B 0C1;7186		CASE [MPU.7-13] AT [FF.7_13.7]		; case on prev mask<13:7>
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  223
;    VFIELD.MIC 	     FFS, FFC, CMPV, CMPZV, EXTV, EXTZV 						      /REV=
;															     VFIELD
				;7187
				;7188	;	FFx, continued.
				;7189	;	Case on second three bit group in current six.
				;7190
				;7191	;	At this point,
				;7192	;		W0	=	position + 14
				;7193	;		W4	=	1'field<31:28> in <20:16>
				;7194	;		MPU	=	field <27:16>, not yet testable
				;7195
				;7196	;= ALIGNLIST 000x	(FF.7_13.7,	FF.7_13.8,	FF.7_13.9,	FF.7_13.10,
				;7197	;=			 FF.7_13.11,	FF.7_13.12,	FF.7_13.13,	FF.7_13.NEXT)
				;7198
				;7199	FF.7_13.7:
				;7200		;---------------------------------------; mask<7> = 1:
				;7201		[DST] <-- [W0] - 000000[07], LONG,	; store result = position + 14 - 7
E 0C1  0A80,2038,2410,1000 L	;7202		LAST CYCLE				; decode next instruction
				;7203
				;7204	FF.7_13.8:
				;7205		;---------------------------------------; mask<8> = 1:
				;7206		[DST] <-- [W0] - 000000[06], LONG,	; store result = position + 14 - 6
E 0C3  0A80,2030,2410,1000 L	;7207		LAST CYCLE				; decode next instruction
				;7208
				;7209	FF.7_13.9:
				;7210		;---------------------------------------; mask<9> = 1:
				;7211		[DST] <-- [W0] - 000000[05], LONG,	; store result = position + 14 - 5
E 0C5  0A80,2028,2410,1000 L	;7212		LAST CYCLE				; decode next instruction
				;7213
				;7214	FF.7_13.10:
				;7215		;---------------------------------------; mask<10> = 1:
				;7216		[DST] <-- [W0] - 000000[04], LONG,	; store result = position + 14 - 4
E 0C7  0A80,2020,2410,1000 L	;7217		LAST CYCLE				; decode next instruction
				;7218
				;7219	FF.7_13.11:
				;7220		;---------------------------------------; mask<11> = 1:
				;7221		[DST] <-- [W0] - 000000[03], LONG,	; store result = position + 14 - 3
E 0C9  0A80,2018,2410,1000 L	;7222		LAST CYCLE				; decode next instruction
				;7223
				;7224	FF.7_13.12:
				;7225		;---------------------------------------; mask<12> = 1:
				;7226		[DST] <-- [W0] - 000000[02], LONG,	; store result = position + 14 - 2
E 0CB  0A80,2010,2410,1000 L	;7227		LAST CYCLE				; decode next instruction
				;7228
				;7229	FF.7_13.13:
				;7230		;---------------------------------------; mask<13> = 1:
				;7231		[DST] <-- [W0] - 000000[01], LONG,	; store result = position + 14 - 1
E 0CD  0A80,2008,2410,1000 L	;7232		LAST CYCLE				; decode next instruction
				;7233
				;7234	FF.7_13.NEXT:
				;7235		;---------------------------------------; mask<13:7> = 0:
				;7236		MPU <-- B.29..16 [W4],			; load MPU with 1'field<31:28>
			    p222;7237							; MPU prev had field<27:14>
E 0CF  0000,0028,200A,C8C0 B 0C0;7238		CASE [MPU.0-6] AT [FF.0_6.0]		; case on prev mask<6:0>
				;7239
;7240	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  224
;    VFIELD.MIC 	     INSV										      /REV=
;															     VFIELD
;7241	.TOC	"	INSV"
;7242
;7243	;	This instruction inserts a source operand into a variable-length bit field.
;7244	;
;7245	;	Mnemonic      Opcode	Operation				Spec	AT/DL			Dispatch
;7246	;	--------      ------	---------				----	-----			--------
;7247	;	INSV		F0	field(pos.rl, size.rb, base.vb) 	4o	rrrv{m2}/llbb		INSV..
;7248	;					<-- src.rl
;7249	;
;7250	;	Entry conditions:
;7251	;		source queue	=	src.rl operand
;7252	;					pos.rl operand
;7253	;					size.rb operand
;7254	;					base.rq operand, if register or
;7255	;					base.ab operand, if memory
;7256	;		dest queue	=	dst.wq, if register
;7257	;					none, if memory
;7258	;		branch queue	=	none
;7259	;		field queue	=	one valid entry for fourth operand
;7260	;		DL		=	BYTE
;7261	;		Ibox state	=	running
;7262	;		Mbox state	=	stopped
;7263	;
;7264	;	Exit conditions:
;7265	;		The source has been inserted into the specified bit field.
;7266	;
;7267	;	Condition codes:
;7268	;		N <-- N
;7269	;		Z <-- Z
;7270	;		V <-- V 		[Integer overflow trap disabled.]
;7271	;		C <-- C
;7272	;
;7273	;	Notes:
;7274	;		1.  Memory management:	If size = 0, source list is drained and dest list is discarded.
;7275	;		2.  Memory management:	Source list is emptied before field is accessed or destination is written.
;7276	;		3.  Memory management:	For field in memory, the field reads are done with write check.  Thus, the
;7277	;		    reads force memory management errors to be made visible before instruction completion.
;7278	;
				;7279	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  225
;    VFIELD.MIC 	     INSV										      /REV=
;															     VFIELD
				;7280
				;7281	;	INSV operation:
				;7282	;
				;7283	;		field(pos.rl, size.rb, base.vb) <-- src.rl
				;7284	;
				;7285	;	Note: In pass 1 microcode, the microcode case on the field queue entry
				;7286	;	is done at the entry point of this instruction, and the field queue
				;7287	;	alignment constraints are done in ALIGN.MIC.  In pass 2 microcode, the
				;7288	;	field queue case is moved into the body of the instruction itself.
				;7289	;	To avoid having to change the IROM, the original field queue constraint
				;7290	;	was not removed from ALIGN.MIC.
				;7291
				;7292	INSV..:
				;7293		;********** Hardware dispatch **********; obsolete fq.vr constraint in ALIGN.MIC
				;7294		[W0] <-- B [S1], LONG,			; [1] save source
				;7295		Q <-- PASSA [S2],			; save position, set sign for shift
				;7296		SC <-- A [S2],				; set shift count to position for rmode
E 26E  0082,4040,049A,03F6 J 3F6;7297			sim cond [s3.v.ps]
				;7298
				;7299		;---------------------------------------;
E 3F6  0400,27F8,1080,05AE J 5AE;7300		[W3] <-- [S1] AND 000000[0FF], LONG	; [2] zext size
				;7301
				;7302	;= ALIGNLIST 100x	(INSV.MEM,		INSV.RMODE,
				;7303	;=					,	INSV.INVALID)
				;7304
				;7305	INSV.INVALID:
				;7306		;---------------------------------------; fq.vr = 11 (invalid)
			    p230;7307		[W2] <-- [W3], LONG,			; [3] copy size for mem case, test = zero
E 5AE  4000,0000,0C40,52A8 B 5A8;7308		CASE [FQ.VR] AT [INSV.MEM]		; wait for field queue to
				;7309							; indicate register or memory
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  226
;    VFIELD.MIC 	     INSV										      /REV=
;															     VFIELD
				;7310
				;7311	;	Field in registers.
				;7312	;	At this point,
				;7313	;		W0	=	source
				;7314	;		Q	=	position
				;7315	;		SC	=	shift count set from position
				;7316	;		W3	=	zext (size)
				;7317
				;7318	INSV.RMODE:
				;7319		;---------------------------------------; fq.vr = 01 (valid, register)
				;7320		[W2] <-- 000000[32.] - [W3], LONG,	; [4] calc 32-size, test size > 32
E 5AA  0A00,2100,0C44,8423 J 423;7321		RESTART MBOX				; resume operand processing
				;7322
				;7323		;---------------------------------------;
				;7324		[W4] <-- [W2] - [Q],			; [5] calc 32-size-pos = 32-(pos+size)
				;7325							; position will be validated later
E 423  2A80,0050,1430,4131 B 431;7326		CASE [ALU.NZV] AT [INSV.R.SIZE.NOT.ZERO] ; case on size = 0 from [3]
				;7327
				;7328	;= ALIGNLIST x0xx	(INSV.R.SIZE.NOT.ZERO,	INSV.R.SIZE.ZERO)
				;7329	;  ALU.NZVC set by LONGWORD AND with mask<31> = 0  --> N = V = C = 0
				;7330
				;7331	INSV.R.SIZE.NOT.ZERO:
				;7332		;---------------------------------------; alu.z = 0 (size not zero)
			    p227;7333		[W1] <-- [S1] RROT (SC), LONG,		; [6] left justify low surround
E 431  4001,8042,0880,42AC B 4AC;7334		CASE [ALU.NZC] AT [INSV.R.SIZE.TOO.BIG] ; case on size > 32 from [4]
				;7335
				;7336	;= ALIGNLIST 110x	(INSV.R.SIZE.TOO.BIG,	INSV.R.SIZE.OK)
				;7337
				;7338	INSV.R.SIZE.OK:
				;7339		;---------------------------------------; alu.c = 1 (size < 32)
				;7340		[W5] <-- [S1],				; [7] get high field surround
			    p229;7341		NODST <-- ZEXT [Q] RSH [5.], LONG,	; test position > 31
E 4AE  4001,C550,1880,42AD B 4AD;7342		CASE [ALU.NZC] AT [INSV.R.2]		; case on pos+size : 32 from [5]
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  227
;    VFIELD.MIC 	     INSV										      /REV=
;															     VFIELD
				;7343
				;7344	;	INSV register mode, continued.
				;7345	;	These are the special cases for INSV in register.
				;7346
				;7347	INSV.R.SIZE.ZERO:
				;7348		;---------------------------------------; alu.z = 1 (size = 0)
				;7349		[DST] <-- [S1], LONG,			; [6] copy source operand 1 to itself
			    p174;7350		Q <-- PASSB [S2],			; get source operand 2
E 435  0002,8048,2480,0376 J 376;7351		GOTO [WRITE.QW] 			; go write source operand 2 to itself
				;7352
				;7353	INSV.R.SIZE.TOO.BIG:
			    p127;7354		;---------------------------------------; alu.c = 0 (size > 32)
E 4AC  0000,0000,2000,003C J 03C;7355		RESERVED OPERAND FAULT			; reserved operand fault
				;7356
				;7357	INSV.R.1.POS.TOO.BIG:
			    p127;7358		;---------------------------------------; shf.z = 0 (pos > 31)
E 193  0000,0000,2000,003C J 03C;7359		RESERVED OPERAND FAULT			; reserved operand fault
				;7360
				;7361	INSV.R.2.POS.TOO.BIG:
			    p127;7362		;---------------------------------------; shf.z = 0 (pos > 31)
E 1E2  0000,0000,2000,003C J 03C;7363		RESERVED OPERAND FAULT			; reserved operand fault
				;7364
				;7365
				;7366	;	These are the special cases for INSV in memory.
				;7367
				;7368	INSV.M.SIZE.ZERO:
				;7369		;---------------------------------------; alu.z = 1 (size = 0)
				;7370		ACCESS A [S1],				; discard base operand
				;7371		RESTART MBOX,				; resume operand processing
E 43D  0000,0000,2084,9000 L	;7372		LAST CYCLE				; decode next instruction
				;7373
				;7374	INSV.M.SIZE.TOO.BIG:
			    p127;7375		;---------------------------------------; alu.c = 0 (size > 32)
E 4BD  0000,0000,2000,003C J 03C;7376		RESERVED OPERAND FAULT			; reserved operand fault
				;7377
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  228
;    VFIELD.MIC 	     INSV										      /REV=
;															     VFIELD
				;7378
				;7379	;	INSV register mode, continued.
				;7380	;	Field extract for one longword field.  (size + position <= 32)
				;7381	;
				;7382	;	Field surround is:  aaaaaa aazzbb
				;7383	;	Source is: xxxxnn
				;7384	;	where:	aaaaaa aa is the left part of the field surround
				;7385	;		zz	  is the part of the field to be replaced
				;7386	;		bb	  is the right part of the field surround
				;7387	;		nn	  is the field to be inserted
				;7388	;		xxxx	  is unused bits
				;7389	;
				;7390	;	At this point,
				;7391	;		W0	=	source (xxxxnn)
				;7392	;		W1	=	low field surround rotated by position (bbaazz <-- aazzbb)
				;7393	;		W2	=	32 - size
				;7394	;		W3	=	zext size
				;7395	;		W4	=	32 - (position + size)
				;7396	;		W5	=	high longword of field surround (aaaaaa)
				;7397	;		Q = SC	=	position
				;7398
				;7399	;= ALIGNLIST 110x	(INSV.R.2,		INSV.R.1)
				;7400
				;7401	INSV.R.1:
				;7402		;---------------------------------------; alu.n = 1 (size + position <= 32)
				;7403		SC <-- A [W2], LONG,			; [8] load 32-size as shift count
E 4AF  0080,0028,D43A,0167 J 167;7404		[SC] <-- B [W4] 			; load 32-(pos+size) as DEFERRED shift count
				;7405
				;7406		;---------------------------------------;		 --W0--  --W1--
				;7407		[W1] <-- [W0]!![W1] RSH (32-SC), LONG,	; [9] nnbbaa <-- xxxxnn!!bbaazz
			    p227;7408							;     sc = 32-size --> eff sc = size
E 167  E001,0012,0810,4F93 B 193;7409		CASE [SHF.NZ.INT] AT [INSV.R.1.POS.TOO.BIG] ; case on pos > 31 from [7]
				;7410
				;7411	;= ALIGNLIST	x01x	(INSV.R.1.POS.TOO.BIG,	INSV.R.1.POS.OK)
				;7412	;  SHF.NZ set by ZEXT right shift --> N = 0
				;7413
				;7414	INSV.R.1.POS.OK:
				;7415		;---------------------------------------; shf.z = 1	  --W5--
E 197  0001,8012,2420,03F7 J 3F7;7416		[DST] <-- [W1] RROT (SC), LONG		; [10] aannbb <-- nnbbaa
				;7417							;      sc = 32-(pos+size)
				;7418
				;7419		;---------------------------------------;
				;7420		[DST] <-- [W5], LONG,			; [11] write second register to itself
E 3F7  0000,0000,2460,1000 L	;7421		LAST CYCLE				; decode next instruction
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  229
;    VFIELD.MIC 	     INSV										      /REV=
;															     VFIELD
				;7422
				;7423	;	INSV register mode, continued.
				;7424	;	Field extract for two longword field.  (size + position > 32)
				;7425	;
				;7426	;	Field surround is:  aaaayy zzbbbb
				;7427	;	Source is: xxnnmm
				;7428	;	where:	aaaa  is the left part of the field surround
				;7429	;		yy zz is the part of the field to be replaced
				;7430	;		bbbb  is the right part of the field surround
				;7431	;		nn mm is the field to be inserted
				;7432	;		xx    is unused bits
				;7433	;
				;7434	;	At this point,
				;7435	;		W0	=	source
				;7436	;		W1	=	low field surround rotated by position (bbbbzz <-- zzbbbb)
				;7437	;		W2	=	32 - size
				;7438	;		W3	=	zext size
				;7439	;		W4	=	32 - (position + size)
				;7440	;		W5	=	high longword of field surround (aaaaaa)
				;7441	;		Q = SC	=	position
				;7442
				;7443	INSV.R.2:
				;7444		;---------------------------------------; alu.n = 0 (size + position > 32)
				;7445							;		 --W0--  --W1--
E 4AD  0001,0012,0810,0171 J 171;7446		[W1] <-- [W0]!![W1] RSH (32-SC), LONG	; [8] mmbbbb <-- xxnnmm!!bbbbzz
				;7447							;     sc = pos --> eff sc = 32-pos
				;7448
				;7449		;---------------------------------------;		 --W0--
				;7450		[W0] <-- [W4]!![W0] RSH (32-SC), LONG,	; [9] xxxxnn <-- xxnnmm
				;7451							;     sc = pos --> eff sc = 32-pos
			    p227;7452		SC <-- A [W4],				; load 32-(pos+size) as shift count
E 171  E001,000A,045A,4FE2 B 1E2;7453		CASE [SHF.NZ.INT] AT [INSV.R.2.POS.TOO.BIG] ; case on pos > 31 from [7]
				;7454
				;7455	;= ALIGNLIST	x01x	(INSV.R.2.POS.TOO.BIG,	INSV.R.2.POS.OK)
				;7456	;  SHF.NZ set by ZEXT right shift --> N = 0
				;7457
				;7458	INSV.R.2.POS.OK:
				;7459		;---------------------------------------; shf.z = 1:
E 1E6  0000,0000,2420,026A J 26A;7460		[DST] <-- [W1], LONG			; [10] store low result
				;7461
				;7462	INSV.R: 					; Dummy label
				;7463		;---------------------------------------;		 --W0--  ---Q--
E 26A  0001,0032,0C10,03F9 J 3F9;7464		[W2] <-- [W0]!![W5] LSH (SC), LONG	; [11] nnaaaa <-- xxxxnn!!aaaayy
				;7465							;      sc = 32-(pos+size)
				;7466
				;7467		;---------------------------------------;		 --W2--
				;7468		[DST] <-- [W2] RROT (SC), LONG, 	; [12] aaaann <-- nnaaaa
				;7469							;      sc = 32-(pos+size)
E 3F9  0001,801A,2430,1000 L	;7470		LAST CYCLE				; decode next instruction
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  230
;    VFIELD.MIC 	     INSV										      /REV=
;															     VFIELD
				;7471
				;7472	;	INSV, field in memory.
				;7473	;	At this point,
				;7474	;		W0	=	source
				;7475	;		Q	=	position
				;7476	;		SC	=	shift count set from position
				;7477	;		W2	=	zext (size)
				;7478	;		shifter sign set from position
				;7479
				;7480	INSV.MEM:
				;7481		;---------------------------------------; fq.vr = 00 (valid, memory)
E 5A8  0A00,2100,1830,0426 J 426;7482		[W5] <-- 000000[32.] - [W2], LONG	; [4] test size > 32
				;7483
				;7484		;---------------------------------------;
				;7485		[W4] <-- B [Q], LONG,			; [5] save position
				;7486		Q <-- SEXT [Q] RSH [3], 		; calc sext pos rsh 3
E 426  2083,8350,1790,4139 B 439;7487		CASE [ALU.NZV] AT [INSV.M.SIZE.NOT.ZERO] ; case on size = 0 from [3]
				;7488
				;7489	;= ALIGNLIST x0xx	(INSV.M.SIZE.NOT.ZERO,	INSV.M.SIZE.ZERO)
				;7490	;  ALU.NZVC set by LONGWORD AND with bit<31> = 0 --> N = V = 0
				;7491
				;7492	INSV.M.SIZE.NOT.ZERO:
				;7493		;---------------------------------------; alu.z = 0 (size not zero)
				;7494		[W3] <-- [S1] + [Q], LONG,		; [6] calc, save base + sext byte position
			    p227;7495		Q <-- [S1] LSH [3],			; calc base * 8
E 439  4883,4350,1080,42BD B 4BD;7496		CASE [ALU.NZC] AT [INSV.M.SIZE.TOO.BIG] ; case on size > 32 from [4]
				;7497
				;7498	;= ALIGNLIST 110x	(INSV.M.SIZE.TOO.BIG,	INSV.M.SIZE.OK)
				;7499
				;7500	INSV.M.SIZE.OK:
				;7501		;---------------------------------------; alu.c = 1 (size <= 32)
			    p231;7502		VA <-- [W3] ANDNOT 000000[03],		; [7] calc longword aligned base address
E 4BF  04C4,2019,0840,03FB J 3FB;7503		[W1] <-- MEM.WCHK (VA), LONG		; read field surround
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  231
;    VFIELD.MIC 	     INSV										      /REV=
;															     VFIELD
				;7504
				;7505	;	INSV memory mode, continued.
				;7506	;	Continue field extraction.
				;7507
				;7508	;	At this point,
				;7509	;		W0	=	source
				;7510	;		W1	=	field surround
				;7511	;		W2	=	zext size
				;7512	;		W3	=	base + sext byte position
				;7513	;		W4	=	position
				;7514	;		W5	=	32 - size
				;7515	;		Q	=	base * 8
				;7516	;		VA	=	longword aligned base address
				;7517
				;7518		;---------------------------------------;
E 3FB  0880,0028,10A0,0268 J 268;7519		[W3] <-- [Q] + [W4], LONG		; [8] base * 8 + pos = bit offset
				;7520
				;7521	INSV.M: 					; Dummy label
				;7522		;---------------------------------------;
E 268  0400,20F8,1040,0444 J 444;7523		[W3] <-- [W3] AND 000000[1F], LONG	; [9] base * 8 + pos mod 32 = aligned pos
				;7524
				;7525		;---------------------------------------;
				;7526		[W4] <-- (-[W3] + [W5]), LONG,		; [10] (32-size)-aligned pos = 32-(pos+size)
E 444  0A00,0030,144A,0445 J 445;7527		SC <-- A [W3]				; load aligned position to SC
				;7528
				;7529		;---------------------------------------;		 --W1--
E 445  0001,8012,0820,0523 J 523;7530		[W1] <-- [W1] RROT (SC), LONG		; [11] bbaazz <-- aazzbb
				;7531							;      sc = aligned pos
				;7532
				;7533		;---------------------------------------;
				;7534		SC <-- A [W5],				; [12] set 32-size as shift count
			    p233;7535		[SC] <-- B [W4], LONG,			; set 32-(pos+size) as DEFERRED shift count
E 523  4080,0028,D46A,42AD B 5AD;7536		CASE [ALU.NZC] AT [INSV.M.2]		; case on pos + size <= 32 from [10]
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  232
;    VFIELD.MIC 	     INSV										      /REV=
;															     VFIELD
				;7537
				;7538	;	INSV memory mode, continued.
				;7539	;	Field in one longword, insert data into field.
				;7540	;
				;7541	;	Field surround is:  aazzbb
				;7542	;	Source is: xxxxnn
				;7543	;	where:	aa   is the left part of the field surround
				;7544	;		zz   is the part of the field to be replaced
				;7545	;		bb   is the right part of the field surround
				;7546	;		nn   is the field to be inserted
				;7547	;		xxxx is unused bits
				;7548	;
				;7549	;	At this point,
				;7550	;		W0	=	source (xxxxnn)
				;7551	;		W1	=	low field surround rotated by position (bbaazz <-- aazzbb)
				;7552	;		W2	=	zext size
				;7553	;		W3	=	longword aligned position
				;7554	;		W4	=	32 - (position + size)
				;7555	;		W5	=	32 - size
				;7556	;		VA	=	longword aligned field address
				;7557	;		SC	=	32-size  (then 32-(pos+size) in next cycle)
				;7558
				;7559	;= ALIGNLIST	110x	(INSV.M.2,		INSV.M.1)
				;7560
				;7561	INSV.M.1:
				;7562		;---------------------------------------; alu.c = 1	  --W0--  --W1--
E 5AF  0001,0012,0410,0446 J 446;7563		[W0] <-- [W0]!![W1] RSH (32-SC), LONG	; [13] nnbbaa <-- xxxxnn!!bbaazz
				;7564							;      sc = 32-size --> eff sc = size
				;7565
				;7566		;---------------------------------------;		 --W0--
				;7567		MEM (VA)&, [WBUS] <-- [W0] RROT (SC),	; [14] aannbb <-- nnbbaa
				;7568							;      sc = 32-(pos+size)
				;7569		LONG,					; write result to memory
				;7570		RESTART MBOX,				; resume operand processing
E 446  0065,800A,2014,9000 L	;7571		LAST CYCLE				; decode next instruction
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  233
;    VFIELD.MIC 	     INSV										      /REV=
;															     VFIELD
				;7572
				;7573	;	INSV memory mode, continued.
				;7574	;	Field in two longwords, insert data into field.
				;7575	;
				;7576	;	Field surround is:  aaaayy zzbbbb
				;7577	;	Source is: xxnnmm
				;7578	;	where:	aaaa  is the left part of the field surround
				;7579	;		yy zz is the part of the field to be replaced
				;7580	;		bbbb  is the right part of the field surround
				;7581	;		nn mm is the field to be inserted
				;7582	;		xx    is unused bits
				;7583	;
				;7584	;	At this point,
				;7585	;		W0	=	source (xxnnmm)
				;7586	;		W1	=	low field surround rotated by position (bbaazz <-- aazzbb)
				;7587	;		W2	=	zext size
				;7588	;		W3	=	longword aligned position
				;7589	;		W4	=	32 - (position + size)
				;7590	;		W5	=	32 - size
				;7591	;		VA	=	longword aligned field address
				;7592	;		SC	=	32-size  (then 32-(pos+size) in next cycle)
				;7593
				;7594	INSV.M.2:
				;7595		;---------------------------------------; pos+size > 32:
				;7596		VA <-- [VA] + 4,			; [13] point to next longword
E 5AD  0C44,0001,0CB0,0447 J 447;7597		[W2] <-- MEM.WCHK (VA), LONG		; read next longword
				;7598
				;7599		;---------------------------------------;
E 447  0000,0000,204A,0449 J 449;7600		SC <-- A [W3]				; [14] reload SC with position
				;7601
				;7602		;---------------------------------------;		  --W0--  --W1--
E 449  0001,0012,0810,044B J 44B;7603		[W1] <-- [W0]!![W1] RSH (32-SC), LONG	; [15] mmbbbb <-- xxnnmm!!bbbbzz
				;7604							;      sc = pos --> eff sc = 32-pos
				;7605
				;7606		;---------------------------------------;		  --W0--
				;7607		[W5] <-- [W4]!![W0] RSH (32-SC), LONG,	; [16] xxxxnn <-- xxnnmm
				;7608							;      sc = pos --> eff sc = 32-pos
E 44B  0001,000A,185A,044D J 44D;7609		SC <-- A [W4]				; load 32-(pos+size) as shift count
				;7610
				;7611		;---------------------------------------;		  --W5--  --W2--
E 44D  0001,001A,0460,0450 J 450;7612		[W0] <-- [W5]!![W2] LSH (SC), LONG	; [17] nnaaaa <-- xxxxnn!!aaaayy
				;7613							;      sc = 32-(pos+size)
				;7614
				;7615		;---------------------------------------;		  --W0--
				;7616		MEM (VA)&, [WBUS] <-- [W0] RROT (SC),	; [18] aaaann <-- nnaaaa
				;7617							;      sc = 32-(pos+size)
E 450  0065,800A,2010,0452 J 452;7618		LONG					;
				;7619
				;7620		;---------------------------------------;
				;7621		VA <-- [VA] - 4,			; [19] go back to previous word
				;7622		MEM (VA)&, [WBUS] <-- PASSB [W1], LONG, ; write first result
				;7623		RESTART MBOX,				; resume operand processing
E 452  0CE4,8013,20B4,9000 L	;7624		LAST CYCLE				; decode next instruction
				;7625
				;7626	;= END VFIELD
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  234
;      CTRL.MIC 	     CTRL.MIC -- Control Instructions							      /REV=
;
				;7627	.TOC	"CTRL.MIC -- Control Instructions"
				;7628	.TOC	"Revision 1.0"
				;7629
				;7630	;	Bob Supnik, Mike Uhler
				;7631
;7632	.nobin
;7633	;****************************************************************************
;7634	;*									    *
;7635	;*  COPYRIGHT (c) 1987, 1988, 1989, 1990, 1991, 1992 BY 		    *
;7636	;*  DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASSACHUSETTS.		    *
;7637	;*  ALL RIGHTS RESERVED.						    *
;7638	;*									    *
;7639	;*  THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED   *
;7640	;*  ONLY IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE   *
;7641	;*  INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE OR ANY  OTHER   *
;7642	;*  COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY   *
;7643	;*  OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE IS  HEREBY   *
;7644	;*  TRANSFERRED.							    *
;7645	;*									    *
;7646	;*  THE INFORMATION IN THIS SOFTWARE IS  SUBJECT TO CHANGE WITHOUT NOTICE   *
;7647	;*  AND  SHOULD  NOT  BE  CONSTRUED AS	A COMMITMENT BY DIGITAL EQUIPMENT   *
;7648	;*  CORPORATION.							    *
;7649	;*									    *
;7650	;*  DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE  OR  RELIABILITY OF ITS   *
;7651	;*  SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.		    *
;7652	;*									    *
;7653	;****************************************************************************
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  235
;      CTRL.MIC 	     Revision History									      /REV=
;
;7654	.TOC	"	Revision History"
;7655
;7656	; Edit	  Date	 Who	     Description
;7657	; ---- --------- ---	---------------------
;7658	; (1)0 20-Jul-90 GMU	Initial production microcode.
;7659	;
;7660	; Begin version 1.0 here
;7661	;    9 05-Jun-90 GMU	Update SEQ.COND names to match implementation.
;7662	;    8 28-May-90 GMU	Do not sync with branch queue in BBxC and BBxS until
;7663	;			all source queue entries have been referenced.	This
;7664	;			prevents deadlock if one of the specifiers is in
;7665	;			I/O space.
;7666	;    7 30-Apr-90 GMU	Sync with Mbox after LOAD PC.
;7667	;    6 26-Apr-90 GMU	Convert '*' fill constraints to 'x' constraints.
;7668	;    5 21-Mar-90 DGM	Update comments
;7669	;    4	8-Jan-90 DGM	Remove all ALU SEXT and ZEXT functions	(In CASEx flow)
;7670	;			Also change field queue alignment.
;7671	;    3 17-Aug-89 GMU	Convert split dispatches to field queue.
;7672	;    2 12-Jan-89 GMU	Update to reflect current design.
;7673	;    1 23-Aug-88 GMU	Add PM hook for CASEx.
;7674	; (0)0 16-Jul-87 RMS	Trial microcode.
;7675
				;7676	.bin
				;7677	;= BEGIN CTRL
;7678	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  236
;      CTRL.MIC 	     Revision History									      /REV=
;															       CTRL
;7679
;7680	;	This module implements the control class instructions.
;7681	;	The instructions in this class are:
;7682	;
;7683	;	Opcode	 Instruction							N Z V C 	Exceptions
;7684	;	------	 -----------							------- 	----------
;7685	;
;7686	;	9D	 ACBB limit.rb, add.rb, index.mb, displ.bw			* * * - 	iov
;7687	;	F1	 ACBL limit.rl, add.rl, index.ml, displ.bw			* * * - 	iov
;7688	;	3D	 ACBW limit.rw, add.rw, index.mw, displ.bw			* * * - 	iov
;7689	;
;7690	;	F3	 AOBLEQ limit.rl, index.ml, displ.bb				* * * - 	iov
;7691	;	F2	 AOBLSS limit.rl, index.ml, displ.bb				* * * - 	iov
;7692	;
;7693	;	1E	 BCC{=BGEQU} displ.bb						- - - -
;7694	;	1F	 BCS{=BLSSU} displ.bb						- - - -
;7695	;	13	 BEQL{=BEQLU} displ.bb						- - - -
;7696	;	18	 BGEQ displ.bb							- - - -
;7697	;	14	 BGTR displ.bb							- - - -
;7698	;	1A	 BGTRU displ.bb 						- - - -
;7699	;	15	 BLEQ displ.bb							- - - -
;7700	;	1B	 BLEQU displ.bb 						- - - -
;7701	;	19	 BLSS displ.bb							- - - -
;7702	;	12	 BNEQ{=BNEQU} displ.bb						- - - -
;7703	;	1C	 BVC displ.bb							- - - -
;7704	;	1D	 BVS displ.bb							- - - -
;7705	;
;7706	;	E1	 BBC pos.rl, base.vb, displ.bb, {field.rv}			- - - - 	rsv
;7707	;	E0	 BBS pos.rl, base.vb, displ.bb, {field.rv}			- - - - 	rsv
;7708	;
;7709	;	E5	 BBCC pos.rl, base.vb, displ.bb, {field.mv}			- - - - 	rsv
;7710	;	E3	 BBCS pos.rl, base.vb, displ.bb, {field.mv}			- - - - 	rsv
;7711	;	E4	 BBSC pos.rl, base.vb, displ.bb, {field.mv}			- - - - 	rsv
;7712	;	E2	 BBSS pos.rl, base.vb, displ.bb, {field.mv}			- - - - 	rsv
;7713	;
;7714	;	E7	 BBCCI pos.rl, base.vb, displ.bb, {field.mv}			- - - - 	rsv
;7715	;	E6	 BBSSI pos.rl, base.vb, displ.bb, {field.mv}			- - - - 	rsv
;7716	;
;7717	;	E9	 BLBC src.rl, displ.bb						- - - -
;7718	;	E8	 BLBS src.rl, displ.bb						- - - -
;7719	;
;7720	;	11	 BRB displ.bb							- - - -
;7721	;	31	 BRW displ.bw							- - - -
;7722	;
;7723	;	10	 BSBB displ.bb, {-(SP).wl}					- - - -
;7724	;	30	 BSBW displ.bw, {-(SP).wl}					- - - -
;7725	;
;7726	;	8F	 CASEB selector.rb, base.rb, limit.rb, displ.bw-list		* * 0 *
;7727	;	CF	 CASEL selector.rl, base.rl, limit.rl, displ.bw-list		* * 0 *
;7728	;	AF	 CASEW selector.rw, base.rw, limit.rw, displ.bw-list		* * 0 *
;7729	;
;7730	;	17	 JMP dst.ab							- - - -
;7731	;
;7732	;	16	 JSB dst.ab, {-(SP).wl} 					- - - -
;7733	;
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  237
;      CTRL.MIC 	     Revision History									      /REV=
;															       CTRL
;7734	;	05	 RSB {(SP)+.rl} 						- - - -
;7735	;
;7736	;	F4	 SOBGEQ index.ml, displ.bb					* * * - 	iov
;7737	;	F5	 SOBGTR index.ml, displ.bb					* * * - 	iov
;7738	;
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  238
;      CTRL.MIC 	     BRx, Bxx, JMP									      /REV=
;															       CTRL
;7739	.TOC	"	BRx, Bxx, JMP"
;7740
;7741	;	The branch instructions perform unconditional or conditional branches.
;7742	;	The JMP instruction performs an unconditional JMP.
;7743	;
;7744	;	Mnemonic      Opcode	Operation				Spec	AT/DL		Dispatch	BCOND
;7745	;	--------      ------	---------				----	-----		--------	-----
;7746	;	BRB		11	PC <-- PC + sext(displ.bb)		0	--		BRX..		--
;7747	;	BRW		31	PC <-- PC + sext(displ.bw)		0	--		BRX..		--
;7748	;
;7749	;	BNEQ, BNEQU	12	if Z eql 0, PC <-- PC + sext(displ.bb)	0	--		BXX..		PSL.~Z
;7750	;	BEQL, BEQLU	13	if Z eql 1, PC <-- PC + sext(displ.bb)	0	--		BXX..		PSL.Z
;7751	;	BGTR		14	if {N or Z} eql 0,			0	--		BXX..		PSL.~(N+Z)
;7752	;					PC <-- PC + sext(displ.bb)
;7753	;	BLEQ		15	if {N or Z} eql 1,			0	--		BXX..		PSL.(N+Z)
;7754	;					PC <-- PC + sext(displ.bb)
;7755	;	BGEQ		18	if N eql 0, PC <-- PC + sext(displ.bb)	0	--		BXX..		PSL.~N
;7756	;	BLSS		19	if N eql 1, PC <-- PC + sext(displ.bb)	0	--		BXX..		PSL.N
;7757	;	BGTRU		1A	if {C or Z} eql 0,			0	--		BXX..		PSL.~(C+Z)
;7758	;					PC <-- PC + sext(displ.bb)
;7759	;	BLEQU		1B	if {C or Z} eql 1,			0	--		BXX..		PSL.(C+Z)
;7760	;					PC <-- PC + sext(displ.bb)
;7761	;	BVC		1C	if V eql 0, PC <-- PC + sext(displ.bb)	0	--		BXX..		PSL.~V
;7762	;	BVS		1D	if V eql 1, PC <-- PC + sext(displ.bb)	0	--		BXX..		PSL.V
;7763	;	BGEQU, BCC	1E	if C eql 0, PC <-- PC + sext(displ.bb)	0	--		BXX..		PSL.~C
;7764	;	BLSSU, BCS	1F	if C eql 1, PC <-- PC + sext(displ.bb)	0	--		BXX..		PSL.C
;7765	;
;7766	;	JMP		17	PC <-- src.ab				1	a/b		BRX..		--
;7767	;
;7768	;	Entry conditions (Bxx):
;7769	;		source queue	=	none
;7770	;		dest queue	=	none
;7771	;		branch queue	=	conditional branch entry, including prediction
;7772	;		field queue	=	none
;7773	;		DL		=	BYTE
;7774	;		Ibox state	=	running, has updated the PC with predicted address
;7775	;		Mbox state	=	running
;7776	;		The PSL has the branch condition, if any.
;7777	;
;7778	;	Entry conditions (BRx):
;7779	;		source queue	=	none
;7780	;		dest queue	=	none
;7781	;		branch queue	=	unconditional branch entry
;7782	;		field queue	=	none
;7783	;		DL		=	BYTE
;7784	;		Ibox state	=	running, has updated the PC with new address
;7785	;		Mbox state	=	running
;7786	;
;7787	;	Entry conditions (JMP):
;7788	;		source queue	=	src.ab operand
;7789	;		dest queue	=	none
;7790	;		branch queue	=	none
;7791	;		field queue	=	none
;7792	;		DL		=	BYTE
;7793	;		Ibox state	=	running, has updated the PC with new address
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  239
;      CTRL.MIC 	     BRx, Bxx, JMP									      /REV=
;															       CTRL
;7794	;		Mbox state	=	running
;7795	;
;7796	;	Exit conditions:
;7797	;		The prediction state is evaluated and sent to the Ibox and a microtrap is generated
;7798	;		if the prediction is wrong (Bxx).
;7799	;		The branch queue entry is retired (Bxx and BRx).
;7800	;
;7801	;	Condition codes:
;7802	;		N <-- N
;7803	;		Z <-- Z
;7804	;		V <-- V 		[Integer overflow trap disabled.]
;7805	;		C <-- C
;7806	;
				;7807	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  240
;      CTRL.MIC 	     BRx, Bxx, JMP									      /REV=
;															       CTRL
				;7808
				;7809	;	Branch operation:
				;7810	;
				;7811	;		if branch condition satisfied then PC <-- PC + sext(displ.bx)
				;7812
				;7813	;	Jump operation:
				;7814	;
				;7815	;			PC <-- src.ab
				;7816
				;7817	BXX..:
				;7818		;********** Hardware dispatch **********;
				;7819		RETIRE COND BQ ENTRY,			; wait for valid bdisp, test
				;7820							; prediction and trap if wrong,
				;7821							; retire BQE
E 15A  000C,0000,2000,1000 L	;7822		LAST CYCLE				; decode next instruction
				;7823
				;7824	BRX..:
				;7825		;********** Hardware dispatch **********;
				;7826		RETIRE UNCOND BQ ENTRY, 		; wait until displacement is valid,
E 158  0008,0000,2000,1000 L	;7827		LAST CYCLE				; decode next instruction
				;7828							; retire BQE
				;7829
				;7830	JMP..:
				;7831		;********** Hardware dispatch **********;
				;7832		ACCESS A [S1],				; throw away source queue
E 15E  0000,0000,2080,1000 L	;7833		LAST CYCLE				; decode next instruction
				;7834
;7835	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  241
;      CTRL.MIC 	     BSBB, BSBW, JSB									      /REV=
;															       CTRL
;7836	.TOC	"	BSBB, BSBW, JSB"
;7837
;7838	;	These instructions call local subroutines.
;7839	;
;7840	;	Mnemonic      Opcode	Operation				Spec	AT/DL		Dispatch
;7841	;	--------      ------	---------				----	-----		--------
;7842	;	BSBB		10	-(SP) <-- PC, PC <-- PC + sext(displ.bb) 0	--		BSBX..
;7843	;	BSBW		30	-(SP) <-- PC, PC <-- PC + sext(displ.bw) 0	--		BSBX..
;7844	;
;7845	;	JSB		16	-(SP) <-- PC, PC <-- src.ab		1	a/b		JSB..
;7846	;
;7847	;	Entry conditions (BSBx):
;7848	;		source queue	=	(implicit specifier) current PC
;7849	;		dest queue	=	address from implicit -(sp) specifier
;7850	;		branch queue	=	unconditional branch entry
;7851	;		field queue	=	none
;7852	;		DL		=	BYTE
;7853	;		Ibox state	=	running, has updated the PC with new address
;7854	;		Mbox state	=	running
;7855	;
;7856	;	Entry conditions (JSB):
;7857	;		source queue	=	dst.ab new PC operand
;7858	;					(implicit specifier) current PC
;7859	;		dest queue	=	address from implicit -(sp) specifier
;7860	;		branch queue	=	none
;7861	;		field queue	=	none
;7862	;		DL		=	BYTE
;7863	;		Ibox state	=	running, has updated the PC with new address
;7864	;		Mbox state	=	running
;7865	;
;7866	;	Exit conditions:
;7867	;		The PC has been pushed on the stack.
;7868	;		The branch queue entry is retired (BSBx).
;7869	;
;7870	;	Condition codes:
;7871	;		N <-- N
;7872	;		Z <-- Z
;7873	;		V <-- V 		[Integer overflow trap disabled.]
;7874	;		C <-- C
;7875	;
;7876	;	Notes:
;7877	;		1.  Performance:  The implied specifier allows the Ibox to continue without suspending.
;7878	;
				;7879	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  242
;      CTRL.MIC 	     BSBB, BSBW, JSB									      /REV=
;															       CTRL
				;7880
				;7881	;	BSBB, BSBW operation:
				;7882	;
				;7883	;		-(SP) <-- PC, PC <-- PC + sext(displ.bx)
				;7884
				;7885	BSBX..:
				;7886		;********** Hardware dispatch **********;
				;7887		[DST] <-- B [S1], LONG, 		; push PC on stack
				;7888		RETIRE UNCOND BQ ENTRY, 		; wait until displacement is valid,
				;7889							; retire BQE
E 150  0088,0040,2400,1000 L	;7890		LAST CYCLE				; decode next instruction
				;7891
				;7892
				;7893	;	JSB operation:
				;7894	;
				;7895	;		-(SP) <-- PC, PC <-- src.ab
				;7896
				;7897	JSB..:
				;7898		;********** Hardware dispatch **********;
				;7899		[DST] <-- B [S2], LONG, 		; push PC on stack
				;7900		ACCESS A [S1],				; access destination address
E 152  0080,0048,2480,1000 L	;7901		LAST CYCLE				; decode next instruction
				;7902
;7903	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  243
;      CTRL.MIC 	     RSB										      /REV=
;															       CTRL
;7904	.TOC	"	RSB"
;7905
;7906	;	This instruction returns control from a subroutine called by BSBB, BSBW, or JSB.
;7907	;
;7908	;	Mnemonic      Opcode	Operation				Spec	AT/DL		Dispatch
;7909	;	--------      ------	---------				----	-----		--------
;7910	;	RSB		05	PC <-- (SP)+				0	--		RSB..
;7911	;
;7912	;	Entry conditions:
;7913	;		source queue	=	(implicit specifier) new PC
;7914	;		dest queue	=	none
;7915	;		branch queue	=	none
;7916	;		field queue	=	none
;7917	;		DL		=	BYTE
;7918	;		Ibox state	=	running, has read the new PC and updated the SP and PC.
;7919	;		Mbox state	=	running
;7920	;
;7921	;	Exit conditions:
;7922	;		None.
;7923	;
;7924	;	Condition codes:
;7925	;		N <-- N
;7926	;		Z <-- Z
;7927	;		V <-- V 		[Integer overflow trap disabled by default iiip map.]
;7928	;		C <-- C
;7929	;
;7930	;	Notes:
;7931	;		1.  Performance:  The implied specifier allows the Ibox to continue without suspending.
;7932	;
				;7933	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  244
;      CTRL.MIC 	     RSB										      /REV=
;															       CTRL
				;7934
				;7935	;	RSB operation:
				;7936	;
				;7937	;		PC <-- (SP)+
				;7938
				;7939	RSB..:
				;7940		;********** Hardware dispatch **********;
				;7941		ACCESS A [S1],				; throw away source queue
E 154  0000,0000,2080,1000 L	;7942		LAST CYCLE				; decode next instruction
				;7943
;7944	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  245
;      CTRL.MIC 	     CASEx										      /REV=
;															       CTRL
;7945	.TOC	"	CASEx"
;7946
;7947	;	These instructions implement multiway case branching on an input selector.
;7948	;
;7949	;	Mnemonic      Opcode	Operation				Spec	AT/DL		Dispatch
;7950	;	--------      ------	---------				----	-----		--------
;7951	;	CASEB		8F	(see below)				3	rrr/bbb 	CASEX..
;7952	;	CASEW		AF	(see below)				3	rrr/www 	CASEX..
;7953	;	CASEL		CF	(see below)				3	rrr/lll 	CASEX..
;7954	;
;7955	;	The case operation is as follows:
;7956	;		tmp <-- selector.rx - base.rx
;7957	;		PC <-- PC + if (tmp LEQU limit.rx) then {sext(displ.bw[tmp])} else {2 + 2*zext(limit.rx))
;7958	;
;7959	;	Entry conditions from specifier flows:
;7960	;		source queue	=	selector.rx operand
;7961	;					base.rx operand
;7962	;					limit.rx operand
;7963	;					(implicit specifier) current PC
;7964	;		dest queue	=	none
;7965	;		branch queue	=	none
;7966	;		field queue	=	none
;7967	;		DL		=	data type of limit.rx operand
;7968	;		Ibox state	=	stopped
;7969	;		Mbox state	=	running
;7970	;
;7971	;	Exit conditions:
;7972	;		The PSL condition codes are set.
;7973	;		The PC has been updated and the Ibox is restarted.
;7974	;
;7975	;	Condition codes:
;7976	;		N <-- selector - base LSS limit
;7977	;		Z <-- selector - base EQL limit
;7978	;		V <-- 0 				[Integer overflow trap disabled.]
;7979	;		C <-- selector - base LSSU limit
;7980	;
;7981	;	Notes:
;7982	;		1.  Performance:  Omitting the SEXT alu function adds one cycle to this instruction.
;7983	;		2.  Memory management:	The source queue is emptied (except for the implicit current
;7984	;		    PC specifier, which cannot fault) before the start of Ebox I/O.
;7985	;
				;7986	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  246
;      CTRL.MIC 	     CASEx										      /REV=
;															       CTRL
				;7987
				;7988	;	CASEx operation:
				;7989	;
				;7990	;		tmp <-- selector.rx - base.rx
				;7991	;		PC <-- PC + if (tmp LEQU limit.rx) then {sext(displ.bw[tmp])}
				;7992	;						   else {2 + 2*zext(limit.rx))}
				;7993
				;7994	CASEX..:
				;7995		;********** Hardware dispatch **********;
E 156  0A80,004C,0480,0454 J 454;7996		[W0] <-- [S1] - [S2], LEN(DL)		; [1] compute zext(selector - base)
				;7997
				;7998		;---------------------------------------;
				;7999		[WBUS] <-- [W0] - [S1], LEN(DL),	; [2] compare with limit (to Wbus for cc's)
				;8000		Q <-- PASSB [S1],			; save limit
				;8001		SET PSL CC.JIZJ,			; set psl cc's, map is jizj
E 454  0A82,8044,201C,8456 J 456;8002			sim cond [s4.casex]
				;8003
				;8004		;---------------------------------------;
				;8005		[W1] <-- B [Q], LEN(DL),		; [3] zext and save limit
E 456  0083,4154,0810,0513 J 513;8006		Q <-- [W0] LSH [1.]			; compute displacement from PC
				;8007
				;8008		;---------------------------------------;
				;8009		[W1] <-- [W1] + [W1] + 1, LONG, 	; [4] compute zext(limit) * 2 + 1
			    p247;8010		DL <-- WORD,				; set dl = word for read
E 513  4900,0010,0822,C249 B 549;8011		CASE [ALU.NZC] AT [CASEX.IN.RANGE.1]	; case on in-range from [2]
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  247
;      CTRL.MIC 	     CASEx										      /REV=
;															       CTRL
				;8012
				;8013	;	CASEx, continued.
				;8014	;	Case range checked.  Compute new PC
				;8015
				;8016	;	At this point,
				;8017	;		W1	=	zext(limit) * 2 + 1
				;8018	;		Q	=	zext(selector - base) * 2
				;8019
				;8020	;= ALIGNLIST 100x	(CASEX.IN.RANGE.1,	CASEX.OUT.RANGE,
				;8021	;=					 ,	CASEX.IN.RANGE.2)
				;8022
				;8023	CASEX.OUT.RANGE:
				;8024		;---------------------------------------; alu.zc = 01:
				;8025		[WBUS] <-- [W1] + [S1] + 1, LONG,	; [5] PC + zext(limit*2) + 2
				;8026		LOAD PC,				; load new PC, restart prefetching
				;8027							; >> LOAD PC: queues must be empty
			    p481;8028							; >> LOAD PC: sync required before exit
E 54B  0924,0040,2020,0572 J 572;8029		GOTO [SYNC.RESTART.IBOX]		; go resume instruction parsing
				;8030
				;8031	CASEX.IN.RANGE.1:
				;8032		;---------------------------------------; alu.zc = 00:
				;8033		VA <-- [Q] + [S1],			; [5] PC + zext(selector-base)*2
				;8034		Q <-- PASSB [S1],			; save current PC
				;8035		[W1] <-- MEM (VA), LEN(DL),		; read displacement
				;8036		GOTO [CASEX.IN.RANGE.COMMON],		; join common flow
E 549  08C2,8045,08A0,0458 J 458;8037			sim addr [case]
				;8038
				;8039	CASEX.IN.RANGE.2:
				;8040		;---------------------------------------; alu.zc = 11:
				;8041		VA <-- [Q] + [S1],			; [5] PC + zext(selector-base)*2
				;8042		Q <-- PASSB [S1],			; save current PC
				;8043		[W1] <-- MEM (VA), LEN(DL),		; read displacement
E 54F  08C2,8045,08A0,0458 J 458;8044			sim addr [case]
				;8045
				;8046	CASEX.IN.RANGE.COMMON:
				;8047		;---------------------------------------;
E 458  0001,5002,0820,045A J 45A;8048		[W1] <-- [W1] LSH [16.], LONG		; [6] set shifter sign to sign of displacement
				;8049
				;8050		;---------------------------------------;
E 45A  0001,9012,0B90,0460 J 460;8051		[W1] <-- SEXT [W1] RSH [16.], LONG	; [7] sign extend displacement to longword
				;8052
				;8053		;---------------------------------------;
				;8054		[WBUS] <-- [Q] + [W1], LONG,		; [8] PC + sext(displ)
				;8055		LOAD PC,				; load new PC, restart prefetching
				;8056							; >> LOAD PC: queues must be empty
			    p481;8057							; >> LOAD PC: sync required before exit
E 460  08A4,0010,20A0,0572 J 572;8058		GOTO [SYNC.RESTART.IBOX]		; go resume instruction parsing
				;8059
;8060	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  248
;      CTRL.MIC 	     SOBGTR, SOBGEQ									      /REV=
;															       CTRL
;8061	.TOC	"	SOBGTR, SOBGEQ"
;8062
;8063	;	These instructions decrement an index and test it against zero.
;8064	;
;8065	;	Mnemonic      Opcode	Operation				Spec	AT/DL		Dispatch	BCOND
;8066	;	--------      ------	---------				----	-----		--------	-----
;8067	;	SOBGEQ		F4	index.ml <-- index.ml - 1		1	m/l		SOBGXX..	ALU.~N
;8068	;					if (index geq 0) then PC <-- PC + sext(displ.bb)
;8069	;	SOBGTR		F5	index.ml <-- index.ml - 1		1	m/l		SOBGXX..	ALU.~(N+Z)
;8070	;					if (index gtr 0) then PC <-- PC + sext(displ.bb)
;8071	;
;8072	;	Entry conditions:
;8073	;		source queue	=	index.ml operand
;8074	;		dest queue	=	index.ml result pointer
;8075	;		branch queue	=	conditional branch entry, including prediction
;8076	;		field queue	=	none
;8077	;		DL		=	LONG
;8078	;		Ibox state	=	running, has updated the PC with predicted address
;8079	;		Mbox state	=	running
;8080	;
;8081	;	Exit conditions:
;8082	;		The prediction state is evaluated and sent to the Ibox and a microtrap is generated
;8083	;		if the prediction is wrong.
;8084	;		The branch queue entry is retired.
;8085	;		The PSL condition codes are set.
;8086	;		The modified index has been stored in the destination memory location or register.
;8087	;
;8088	;	Condition codes:
;8089	;		N <-- index LSS 0
;8090	;		Z <-- index EQL 0
;8091	;		V <-- overflow		[Integer overflow trap enabled.]
;8092	;		C <-- C
;8093	;
				;8094	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  249
;      CTRL.MIC 	     SOBGTR, SOBGEQ									      /REV=
;															       CTRL
				;8095
				;8096	;	SOBGEQ, SOBGTR operation:
				;8097	;
				;8098	;		index.ml <-- index.ml - 1
				;8099	;		if (index geq, gtr 0) then PC <-- PC + sext(displ.bb)
				;8100
				;8101	SOBGXX..:
				;8102		;********** Hardware dispatch **********;
				;8103		[DST] <-- [S1] - 1, LONG,		; decrement index
				;8104		SET PSL CC.IIIP,			; set psl cc's, map is iiip
				;8105		RETIRE COND BQ ENTRY,			; wait for valid bdisp, test
				;8106							; prediction and trap if wrong,
				;8107							; retire BQE
E 140  0B0C,0000,248C,1800 L	;8108		LAST CYCLE CHECK OVERFLOW		; decode next instruction
				;8109
;8110	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  250
;      CTRL.MIC 	     AOBLSS, AOBLEQ									      /REV=
;															       CTRL
;8111	.TOC	"	AOBLSS, AOBLEQ"
;8112
;8113	;	These instructions increment an index and test it against a limit.
;8114	;
;8115	;	Mnemonic      Opcode	Operation				Spec	AT/DL		Dispatch	BCOND
;8116	;	--------      ------	---------				----	-----		--------	-----
;8117	;	AOBLSS		F2	index.ml <-- index.ml + 1		2	rm/ll		AOBLXX..	ALU.LSS
;8118	;					if (index lss limit) then PC <-- PC + sext(displ.bb)
;8119	;	AOBLEQ		F3	index.ml <-- index.ml + 1		2	rm/ll		AOBLXX..	ALU.LEQ
;8120	;					if (index leq limit) then PC <-- PC + sext(displ.bb)
;8121	;
;8122	;	Entry conditions:
;8123	;		source queue	=	limit.rl operand
;8124	;				=	index.ml operand
;8125	;		dest queue	=	index.ml result pointer
;8126	;		branch queue	=	conditional branch entry, including prediction
;8127	;		field queue	=	none
;8128	;		DL		=	LONG
;8129	;		Ibox state	=	running, has updated the PC with predicted address
;8130	;		Mbox state	=	running
;8131	;
;8132	;	Exit conditions:
;8133	;		The prediction state is evaluated and sent to the Ibox and a microtrap is generated
;8134	;		if the prediction is wrong.
;8135	;		The branch queue entry is retired.
;8136	;		The PSL condition codes are set.
;8137	;		The modified index has been stored in the destination memory location or register.
;8138	;
;8139	;	Condition codes:
;8140	;		N <-- index LSS 0
;8141	;		Z <-- index EQL 0
;8142	;		V <-- overflow		[Integer overflow trap enabled.]
;8143	;		C <-- C
;8144	;
				;8145	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  251
;      CTRL.MIC 	     AOBLSS, AOBLEQ									      /REV=
;															       CTRL
				;8146
				;8147	;	AOBLSS, AOBLEQ operation:
				;8148	;
				;8149	;		index.ml <-- index.ml + 1
				;8150	;		if (index lss, leq limit) then PC <-- PC + sext(displ.bb)
				;8151
				;8152	AOBLXX..:
				;8153		;********** Hardware dispatch **********;
				;8154		[W1] <-- [S2] + 1, LONG,		; compute result
				;8155		Q <-- PASSB [S1],			; save limit
E 142  0802,8040,089C,0462 J 462;8156		SET PSL CC.IIIP 			; set psl cc's, map is iiip
				;8157
				;8158		;---------------------------------------;
				;8159		NODST <-- [W1] - [Q], LONG,		; compare result with limit
				;8160		[DST] <-- PASSA [W1],			; store result
				;8161		RETIRE COND BQ ENTRY,			; wait for valid bdisp, test
				;8162							; prediction and trap if wrong,
				;8163							; retire BQE
E 462  0A8C,4052,2420,1800 L	;8164		LAST CYCLE CHECK OVERFLOW		; decode next instruction
				;8165
;8166	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  252
;      CTRL.MIC 	     ACBx										      /REV=
;															       CTRL
;8167	.TOC	"	ACBx"
;8168
;8169	;	These instructions add a value to an index and test the result against a limit.
;8170	;
;8171	;	Mnemonic      Opcode	Operation				Spec	AT/DL		Dispatch	BCOND
;8172	;	--------      ------	---------				----	-----		--------	-----
;8173	;	ACBB		9D	index.mb <-- index.mb + add.rb		3	rrm/bbb 	ACBB..		ALU.LEQ
;8174	;					if (add geq 0 and index leq limit) then PC <-- PC + sext(displ.bw)
;8175	;					if (add lss 0 and index geq limit) then PC <-- PC + sext(displ.bw)
;8176	;	ACBW		3D	index.mw <-- index.mw + add.rw		3	rrm/www 	ACBW..		ALU.LEQ
;8177	;					if (add geq 0 and index leq limit) then PC <-- PC + sext(displ.bw)
;8178	;					if (add lss 0 and index geq limit) then PC <-- PC + sext(displ.bw)
;8179	;	ACBL		F1	index.ml <-- index.ml + add.rl		3	rrm/lll 	ACBL..		ALU.LEQ
;8180	;					if (add geq 0 and index leq limit) then PC <-- PC + sext(displ.bw)
;8181	;					if (add lss 0 and index geq limit) then PC <-- PC + sext(displ.bw)
;8182	;
;8183	;	Entry conditions:
;8184	;		source queue	=	limit.rx operand
;8185	;				=	add.rx operand
;8186	;				=	index.mx operand
;8187	;		dest queue	=	index.mx result pointer
;8188	;		branch queue	=	conditional branch entry, including prediction
;8189	;		field queue	=	none
;8190	;		DL		=	data type of index.mx operand
;8191	;		Ibox state	=	running, has updated the PC with predicted address
;8192	;		Mbox state	=	running
;8193	;
;8194	;	Exit conditions:
;8195	;		The prediction state is evaluated and sent to the Ibox and a microtrap is generated
;8196	;		if the prediction is wrong.
;8197	;		The branch queue entry is retired.
;8198	;		The PSL condition codes are set.
;8199	;		The modified index has been stored in the destination memory location or register.
;8200	;
;8201	;	Condition codes:
;8202	;		N <-- index LSS 0
;8203	;		Z <-- index EQL 0
;8204	;		V <-- overflow		[Integer overflow trap enabled.]
;8205	;		C <-- C
;8206	;
				;8207	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  253
;      CTRL.MIC 	     ACBx										      /REV=
;															       CTRL
				;8208
				;8209	;	ACBx operation:
				;8210	;
				;8211	;		index.mx <-- index.mx + add.rx
				;8212	;			if (add geq 0 and index leq limit) then PC <-- PC + sext(displ.bb)
				;8213	;			if (add lss 0 and index geq limit) then PC <-- PC + sext(displ.bb)
				;8214
				;8215	ACBB..:
				;8216		;********** Hardware dispatch **********;
				;8217		[W0] <-- [S2], LEN(DL), 		; [1] test sign of add operand, save
				;8218		Q <-- PASSB [S1],			; save limit
E 148  0002,8044,0490,042D J 42D;8219			sim cond [s3.acbx]
				;8220
				;8221		;---------------------------------------;
				;8222		[W1] <-- [W0] + [S1], LEN(DL),		; [2] index <-- add + index
			    p254;8223		SET PSL CC.IIIP,			; set psl cc's, map is iiip
E 42D  A880,0044,081C,45C6 B 4C6;8224		CASE [A.7-5] AT [ACBI.GEQ]		; case on add<msb>
				;8225
				;8226	ACBW..:
				;8227		;********** Hardware dispatch **********;
				;8228		[W0] <-- [S2], LEN(DL), 		; [1] test sign of add operand, save
				;8229		Q <-- PASSB [S1],			; save limit
E 14A  0002,8044,0490,0433 J 433;8230			sim cond [s3.acbx]
				;8231
				;8232		;---------------------------------------;
				;8233		[W1] <-- [W0] + [S1], LEN(DL),		; [2] index <-- add + index
			    p254;8234		SET PSL CC.IIIP,			; set psl cc's, map is iiip
E 433  C880,0044,081C,46C6 B 4C6;8235		CASE [A.15-12] AT [ACBI.GEQ]		; case on add<msb>
				;8236
				;8237	ACBL..:
				;8238		;********** Hardware dispatch **********;
				;8239		[W0] <-- [S2], LEN(DL), 		; [1] test sign of add operand, save
				;8240		Q <-- PASSB [S1],			; save limit
E 14C  0002,8044,0490,043B J 43B;8241			sim cond [s3.acbx]
				;8242
				;8243		;---------------------------------------;
				;8244		[W1] <-- [W0] + [S1], LEN(DL),		; [2] index <-- add + index
			    p254;8245		SET PSL CC.IIIP,			; set psl cc's, map is iiip
E 43B  E880,0044,081C,47C6 B 4C6;8246		CASE [A31.BQA.BNZ1] AT [ACBI.GEQ]	; case on add<msb>
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  254
;      CTRL.MIC 	     ACBx										      /REV=
;															       CTRL
				;8247
				;8248	;	ACBi, continued.
				;8249	;
				;8250	;	At this point,
				;8251	;		W1	=	New index value
				;8252	;		Q	=	limit value
				;8253
				;8254	;= ALIGNLIST 011x	(ACBI.GEQ,	ACBI.LSS)
				;8255
				;8256	ACBI.GEQ:
				;8257		;---------------------------------------; add<msb> = 0:
				;8258		NODST <-- [W1] - [Q], LEN(DL),		; [3] compute index - limit
				;8259		[DST] <-- PASSA [W1],			; store result
				;8260		RETIRE COND BQ ENTRY,			; wait for valid bdisp, test
				;8261							; prediction and trap if wrong,
				;8262							; retire BQE
E 4C6  0A8C,4056,2420,1800 L	;8263		LAST CYCLE CHECK OVERFLOW		; decode next instruction
				;8264
				;8265	ACBI.LSS:
				;8266		;---------------------------------------; add<msb> = 1:
				;8267		NODST <-- [Q] - [W1], LEN(DL),		; [3] compute limit - index
				;8268		[DST] <-- PASSB [W1],			; store result
				;8269		RETIRE COND BQ ENTRY,			; wait for valid bdisp, test
				;8270							; prediction and trap if wrong,
				;8271							; retire BQE
E 4CE  0A8C,8016,24A0,1800 L	;8272		LAST CYCLE CHECK OVERFLOW		; decode next instruction
				;8273
;8274	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  255
;      CTRL.MIC 	     BBx, BBxS, BBxC, BBxxI								      /REV=
;															       CTRL
;8275	.TOC	"	BBx, BBxS, BBxC, BBxxI"
;8276
;8277	;	These instructions test, or test and alter, a one-bit field.
;8278	;
;8279	;	Mnemonic      Opcode	Operation				Spec	AT/DL		Dispatch	BCOND
;8280	;	--------      ------	---------				----	-----		--------	-----
;8281	;	BBS		E0	if bit(pos.rl, base.vb) eql 1		2	rv{r1}/lb	BBX..		SHF<0>
;8282	;					then PC <-- PC + sext(displ.bb)
;8283	;	BBC		E1	if bit(pos.rl, base.vb) eql 0		2	rv{r1}/lb	BBX..		~SHF<0>
;8284	;					then PC <-- PC + sext(displ.bb)
;8285	;
;8286	;	BBSS		E2	if bit(pos.rl, base.vb) eql 1		2	rv{m1}/lb	BBXS..		SHF<0>
;8287	;					then PC <-- PC + sext(displ.bb)
;8288	;					bit(pos.rl, base.vb) <-- 1
;8289	;	BBCS		E3	if bit(pos.rl, base.vb) eql 0		2	rv{m1}/lb	BBXS..		~SHF<0>
;8290	;					then PC <-- PC + sext(displ.bb)
;8291	;					bit(pos.rl, base.vb) <-- 1
;8292	;
;8293	;	BBSC		E4	if bit(pos.rl, base.vb) eql 1		2	rv{m1}/lb	BBXC..		SHF<0>
;8294	;					then PC <-- PC + sext(displ.bb)
;8295	;					bit(pos.rl, base.vb) <-- 0
;8296	;	BBCC		E5	if bit(pos.rl, base.vb) eql 0		2	rv{m1}/lb	BBXC..		~SHF<0>
;8297	;					then PC <-- PC + sext(displ.bb)
;8298	;					bit(pos.rl, base.vb) <-- 0
;8299	;
;8300	;	BBSSI		E6	if bit(pos.rl, base.vb) eql 1		2	rv{m1}/lb	BBXS..		SHF<0>
;8301	;					then PC <-- PC + sext(displ.bb)
;8302	;					bit(pos.rl, base.vb) <-- 1 INTERLOCKED
;8303	;	BBCCI		E7	if bit(pos.rl, base.vb) eql 0		2	rv{m1}/lb	BBXC..		~SHF<0>
;8304	;					then PC <-- PC + sext(displ.bb)
;8305	;					bit(pos.rl, base.vb) <-- 0 INTERLOCKED
;8306	;
;8307	;	Entry conditions:
;8308	;		source queue	=	pos.rl operand
;8309	;				=	register value (if register), or address of base operand (if memory)
;8310	;		dest queue	=	register result pointer (BBxy or BBxxI, register only)
;8311	;		branch queue	=	conditional branch entry, including prediction
;8312	;		field queue	=	none
;8313	;		DL		=	BYTE
;8314	;		Ibox state	=	running, has updated the PC with predicted address
;8315	;		Mbox state	=	stopped
;8316	;
;8317	;	Exit conditions:
;8318	;		The prediction state is evaluated and sent to the Ibox and a microtrap is generated
;8319	;		if the prediction is wrong.
;8320	;		The branch queue entry is retired.
;8321	;		If not BBx, the selected bit has been updated.
;8322	;		Mbox operand processing is resumed.
;8323	;
;8324	;	Condition codes:
;8325	;		N <-- N
;8326	;		Z <-- Z
;8327	;		V <-- V 		[Integer overflow trap disabled.]
;8328	;		C <-- C
;8329	;
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  256
;      CTRL.MIC 	     BBx, BBxS, BBxC, BBxxI								      /REV=
;															       CTRL
;8330	;	Notes:
;8331	;		1.  Performance:   In memory flows, SC <-- A<2:0> and built in sext right shift would save a cycle.
;8332	;		3.  Memory management:	The memory reads with modify intent are done with write checking.  Thus,
;8333	;		    the writes force memory management errors to be made visible before instruction completion.
;8334	;
				;8335	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  257
;      CTRL.MIC 	     BBx, BBxS, BBxC, BBxxI								      /REV=
;															       CTRL
				;8336
				;8337	;	BBx operation:
				;8338	;
				;8339	;		if bit(pos.rl, base.vb) eql x then PC <-- PC + sext(displ.bb)
				;8340
				;8341	;	BBxy operation:
				;8342	;
				;8343	;		if bit(pos.rl, base.vb) eql x then PC <-- PC + sext(displ.bb)
				;8344	;		bit(pos.rl, base.vb) <-- y
				;8345
				;8346	;	BBxxI operation:
				;8347	;
				;8348	;		if bit(pos.rl, base.vb) eql x then PC <-- PC + sext(displ.bb)
				;8349	;		bit(pos.rl, base.vb) <-- x INTERLOCKED
				;8350	;
				;8351	;	Note: Constraints for BBX.., BBX.R, and BBX.M are
				;8352	;	done in ALIGN.MIC.
				;8353
				;8354	BBX..:
			    p260;8355		;********** Hardware dispatch **********; fq.vr = 11 (invalid)
E 24E  4000,0000,2000,5248 B 248;8356		CASE [FQ.VR] AT [BBX.M] 		; [1] wait for field queue to
				;8357							; indicate register or memory
				;8358
				;8359	BBX.R:
				;8360		;---------------------------------------; fq.vr = 01 (valid, register)
				;8361		VA <-- [S1] ANDNOT 000000[1F], LONG,	; [2] test position <= 31
				;8362		SC <-- A [S1],				; load shift count with position
E 24A  0480,20F9,208A,2464 S 464;8363		CALL [BBX.GET.SRC.RESTART.MBOX] 	; [3] get source operand in w0, restart mbox
				;8364
				;8365		;---------------------------------------;
				;8366		NOP,					; [4] nothing to do
E 24B  2000,0000,2000,411B B 21B;8367		CASE [ALU.NZV] AT [BBX.R.RSRV]		; case on position <= 31
				;8368
				;8369	;= ALIGNLIST 10xx	(BBX.R.RSRV,		BBX.R.TEST)
				;8370	; ALU.NZV set from ANDNOT --> V = C = 0
				;8371
				;8372	BBX.R.RSRV:
			    p127;8373		;---------------------------------------; alu.z = 0 --> pos > 31:
E 21B  0000,0000,2000,003C J 03C;8374		RESERVED OPERAND FAULT			; reserved operand fault
				;8375
				;8376	BBX.R.TEST:
				;8377		;---------------------------------------; alu.z = 1 --> pos <= 31:
				;8378		Q <-- ZEXT [W0] RSH (SC), LONG, 	; [5] shift selected bit to <0>
				;8379		RETIRE COND BQ ENTRY,			; wait for valid bdisp, test
				;8380							; prediction and trap if wrong,
				;8381							; retire BQE
E 21F  000F,C008,2000,1000 L	;8382		LAST CYCLE				; decode next instruction
				;8383
				;8384	; One line subroutine to save source operand in W0 and restart Mbox
				;8385
				;8386	BBX.GET.SRC.RESTART.MBOX:
				;8387		;---------------------------------------;
				;8388		[W0] <-- [S1], LONG,			; get source operand
				;8389		RESTART MBOX,				; resume operand processing
E 464  0000,0000,0484,8800 R	;8390		RETURN					; return to caller
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  258
;      CTRL.MIC 	     BBx, BBxS, BBxC, BBxxI								      /REV=
;															       CTRL
				;8391
				;8392	;	BBxS or BBSSI, field in register.
				;8393	;
				;8394	;	Note: Constraints for BBXS.., BBXS.R, and BBXS.M are
				;8395	;	done in ALIGN.MIC.
				;8396
				;8397	BBXS..:
			    p261;8398		;********** Hardware dispatch **********; fq.vr = 11 (invalid)
E 256  4000,0000,2000,5250 B 250;8399		CASE [FQ.VR] AT [BBXS.M]		; [1] wait for field queue to
				;8400							; indicate register or memory
				;8401
				;8402	BBXS.R:
				;8403		;---------------------------------------; fq.vr = 01 (valid, register)
				;8404		VA <-- [S1] ANDNOT 000000[1F], LONG,	; [2] test position <= 31
			    p257;8405		SC <-- A [S1],				; load shift count with position
E 252  0480,20F9,208A,2464 S 464;8406		CALL [BBX.GET.SRC.RESTART.MBOX] 	; [3] get source operand in w0, restart mbox
				;8407
				;8408		;---------------------------------------;
				;8409		[W1] <-- [K1] LSH (SC), LONG,		; [4] form mask from position
E 253  2001,4002,0B20,4149 B 249;8410		CASE [ALU.NZV] AT [BBXS.R.RSRV] 	; case on position <= 31
				;8411
				;8412	;= ALIGNLIST 10xx	(BBXS.R.RSRV,		BBXS.R.TEST)
				;8413	; ALU.NZV set from ANDNOT --> V = C = 0
				;8414
				;8415	BBXS.R.RSRV:
			    p127;8416		;---------------------------------------; alu.z = 0 --> pos > 31:
E 249  0000,0000,2000,003C J 03C;8417		RESERVED OPERAND FAULT			; reserved operand fault
				;8418
				;8419	BBXS.R.TEST:
				;8420		;---------------------------------------; alu.z = 1 --> pos <= 31:
				;8421		[DST] <-- [W1] OR [W0], LONG,		; [5] set selected bit
				;8422		Q <-- ZEXT [W0] RSH (SC),		; shift selected bit to <0>
				;8423		RETIRE COND BQ ENTRY,			; wait for valid bdisp, test
				;8424							; prediction and trap if wrong,
				;8425							; retire BQE
E 24D  050F,C008,2420,1000 L	;8426		LAST CYCLE				; decode next instruction
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  259
;      CTRL.MIC 	     BBx, BBxS, BBxC, BBxxI								      /REV=
;															       CTRL
				;8427
				;8428	;	BBxC or BBCCI, field in register.
				;8429	;
				;8430	;	Note: Constraints for BBXC.., BBXC.R, and BBXC.M are
				;8431	;	done in ALIGN.MIC.
				;8432
				;8433	BBXC..:
			    p262;8434		;********** Hardware dispatch **********; fq.vr = 11 (invalid)
E 25E  4000,0000,2000,5258 B 258;8435		CASE [FQ.VR] AT [BBXC.M]		; [1] wait for field queue to
				;8436							; indicate register or memory
				;8437
				;8438	BBXC.R:
				;8439		;---------------------------------------; fq.vr = 01 (valid, register)
				;8440		VA <-- [S1] ANDNOT 000000[1F], LONG,	; [2] test position <= 31
			    p257;8441		SC <-- A [S1],				; load shift count with position
E 25A  0480,20F9,208A,2464 S 464;8442		CALL [BBX.GET.SRC.RESTART.MBOX] 	; [3] get source operand in w0, restart mbox
				;8443
				;8444		;---------------------------------------;
				;8445		[W1] <-- [K1] LSH (SC), LONG,		; [4] form mask from position
E 25B  2001,4002,0B20,4159 B 259;8446		CASE [ALU.NZV] AT [BBXC.R.RSRV] 	; case on position <= 31
				;8447
				;8448	;= ALIGNLIST 10xx	(BBXC.R.RSRV,		BBXC.R.TEST)
				;8449	; ALU.NZV set from ANDNOT --> V = C = 0
				;8450
				;8451	BBXC.R.RSRV:
			    p127;8452		;---------------------------------------; alu.z = 0 --> pos > 31:
E 259  0000,0000,2000,003C J 03C;8453		RESERVED OPERAND FAULT			; reserved operand fault
				;8454
				;8455	BBXC.R.TEST:
				;8456		;---------------------------------------; alu.z = 1 --> pos <= 31:
				;8457		[DST] <-- NOT [W1] AND [W0], LONG,	; [5] clear selected bit
				;8458		Q <-- ZEXT [W0] RSH (SC),		; shift selected bit to <0>
				;8459		RETIRE COND BQ ENTRY,			; wait for valid bdisp, test
				;8460							; prediction and trap if wrong,
				;8461							; retire BQE
E 25D  068F,C008,2420,1000 L	;8462		LAST CYCLE				; decode next instruction
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  260
;      CTRL.MIC 	     BBx, BBxS, BBxC, BBxxI								      /REV=
;															       CTRL
				;8463
				;8464	;	BBx, field in memory.
				;8465
				;8466	BBX.M:
				;8467		;---------------------------------------; fq.vr = 00 (valid, memory)
				;8468		[SC] <-- [S1] AND 000000[07], LONG,	; [2] position in byte to SC
E 248  0402,6038,D480,0468 J 468;8469		Q <-- PASSA [S1]			; position to shift latch
				;8470
				;8471		;---------------------------------------;
E 468  0001,8352,0B90,046A J 46A;8472		[W1] <-- SEXT [Q] RSH [3], LONG 	; [3] convert position to signed byte offset
				;8473
				;8474		;---------------------------------------;
				;8475		VA <-- [S1] + [W1],			; [4] calculate addr of selected byte
				;8476		[W0] <-- MEM (VA), LEN(DL),		; read selected byte
				;8477		RESTART MBOX,				; resume operand processing
			    p257;8478		GOTO [BBX.R.TEST],			; go test selected byte
E 46A  08C0,0015,0484,821F J 21F;8479			sim addr [field]
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  261
;      CTRL.MIC 	     BBx, BBxS, BBxC, BBxxI								      /REV=
;															       CTRL
				;8480
				;8481	;	BBxS, field in memory.
				;8482	;
				;8483	;	Note: All source queue entries must be referenced before the branch
				;8484	;	queue entry to prevent deadlock if one of the specifiers is in
				;8485	;	I/O space.
				;8486
				;8487	BBXS.M:
				;8488		;---------------------------------------; fq.vr = 00 (valid, memory)
				;8489		[SC] <-- [S1] AND 000000[07], LONG,	; [2] position in byte to SC
E 250  0402,6038,D480,0440 J 440;8490		Q <-- PASSA [S1]			; position to shift latch
				;8491
				;8492		;---------------------------------------;
				;8493		[W1] <-- SEXT [Q] RSH [3], LONG,	; [3] convert position to signed byte offset
E 440  8001,8352,0B90,4CC7 B 4C7;8494		CASE [OPCODE.2-0] AT [BBXS.M.READ]	; case on normal vs interlocked
				;8495
				;8496	;= ALIGNLIST 011x	(BBXS.M.READ,		BBSSI.M.READ)
				;8497
				;8498	BBXS.M.READ:
				;8499		;---------------------------------------; BBxS:
				;8500		VA <-- [S1] + [W1],			; [4] calculate addr of selected byte
				;8501		[W0] <-- MEM.WCHK (VA), LEN(DL),	; read selected byte, check write
			    p263;8502		CALL [BBX.MAKE.MASK.WAIT.BDISP],	; [5] form mask in W1, wait for displacement
E 4C7  08C4,0015,0480,2471 S 471;8503			sim addr [field]
				;8504
				;8505	;	Note: Write must not be done until displacement is known to
				;8506	;	be accessable
				;8507
				;8508		;---------------------------------------;
				;8509		MEM (VA)&, [WBUS] <-- [W1] OR [W0],	; [6] set bit, write result
				;8510		LEN(DL),				;
			    p257;8511		RESTART MBOX,				; resume operand processing
E 4C8  0564,000C,2024,821F J 21F;8512		GOTO [BBX.R.TEST]			; go test selected bit
				;8513
				;8514	;	Note: Read lock must not be done until displacement is known to
				;8515	;	be accessable
				;8516
				;8517	BBSSI.M.READ:
				;8518		;---------------------------------------; BBSSI:
				;8519		VA <-- [S1] + [W1],			; [4] calculate addr of selected byte
				;8520		WAIT BDISP VALID,			; wait until displacement is valid
				;8521		CALL [BBX.RDLK.MAKE.MASK],		; [5-6] Read interlocked data to W0, form
			    p263;8522							; mask in W1
E 4CF  0884,0011,2080,246C S 46C;8523			sim addr [field]
				;8524
				;8525		;---------------------------------------;
				;8526		MEM.UNLOCK (VA)&, [WBUS] <-- [W1] OR [W0], ; [7] set bit, write result, unlock
				;8527		LEN(DL),				;
			    p257;8528		RESTART MBOX,				; resume operand processing
E 4C0  056C,000C,2024,821F J 21F;8529		GOTO [BBX.R.TEST]			; go test selected bit
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  262
;      CTRL.MIC 	     BBx, BBxS, BBxC, BBxxI								      /REV=
;															       CTRL
				;8530
				;8531	;	BBxC, continued.
				;8532	;
				;8533	;	Note: All source queue entries must be referenced before the branch
				;8534	;	queue entry to prevent deadlock if one of the specifiers is in
				;8535	;	I/O space.
				;8536
				;8537	BBXC.M:
				;8538		;---------------------------------------; fq.vr = 00 (valid, memory)
				;8539		[SC] <-- [S1] AND 000000[07], LONG,	; [2] position in byte to SC
E 258  0402,6038,D480,0441 J 441;8540		Q <-- PASSA [S1]			; position to shift latch
				;8541
				;8542		;---------------------------------------;
				;8543		[W1] <-- SEXT [Q] RSH [3], LONG,	; [3] convert position to signed byte offset
E 441  8001,8352,0B90,4CDA B 4DA;8544		CASE [OPCODE.2-0] AT [BBXC.M.READ]	; case on normal vs interlocked
				;8545
				;8546	;= ALIGNLIST 101x	(BBXC.M.READ,	BBCCI.M.READ)
				;8547
				;8548	BBXC.M.READ:
				;8549		;---------------------------------------; BBxC:
				;8550		VA <-- [S1] + [W1],			; [4] calculate addr of selected byte
				;8551		[W0] <-- MEM.WCHK (VA), LEN(DL),	; read selected byte, check write
			    p263;8552		CALL [BBX.MAKE.MASK.WAIT.BDISP],	; [5] form mask in W1, wait for displacement
E 4DA  08C4,0015,0480,2471 S 471;8553			sim addr [field]
				;8554
				;8555	;	Note: Write must not be done until displacement is known to
				;8556	;	be accessable
				;8557
				;8558		;---------------------------------------;
				;8559		MEM (VA)&, [WBUS] <-- NOT [W1] AND [W0], ; [6] clear bit, write result
				;8560		LEN(DL),				;
			    p257;8561		RESTART MBOX,				; resume operand processing
E 4DB  06E4,000C,2024,821F J 21F;8562		GOTO [BBX.R.TEST]			; go test selected bit
				;8563
				;8564	;	Note: Read lock must not be done until displacement is known to
				;8565	;	be accessable
				;8566
				;8567	BBCCI.M.READ:
				;8568		;---------------------------------------; BBCCI:
				;8569		VA <-- [S1] + [W1],			; [4] calculate addr of selected byte
				;8570		WAIT BDISP VALID,			; wait until displacement is valid
				;8571		CALL [BBX.RDLK.MAKE.MASK],		; [5-6] Read interlocked data to W0, form
			    p263;8572							; mask in W1
E 4DE  0884,0011,2080,246C S 46C;8573			sim addr [field]
				;8574
				;8575		;---------------------------------------;
				;8576		MEM.UNLOCK (VA)&, [WBUS] <-- NOT [W1] AND [W0], ; [7] clear bit, write result, unlock
				;8577		LEN(DL),				;
			    p257;8578		RESTART MBOX,				; resume operand processing
E 4DF  06EC,000C,2024,821F J 21F;8579		GOTO [BBX.R.TEST]			; go test selected bit
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  263
;      CTRL.MIC 	     BBx, BBxS, BBxC, BBxxI								      /REV=
;															       CTRL
				;8580
				;8581	;	Subroutine to interlock read the selected byte and form
				;8582	;	a mask of the selected bit.
				;8583	;
				;8584	;	Entry conditions:
				;8585	;		VA	=	Address of byte
				;8586	;		DL	=	Byte
				;8587	;		SC	=	Position of bit within longword
				;8588	;
				;8589	;	Exit conditions:
				;8590	;		W0	=	Interlocked byte from memory
				;8591	;		W1	=	Mask
				;8592	;
				;8593	;	Note:  A second WAIT BDISP VALID is done for BBSSI and BBCCI, but
				;8594	;	this command has no side effects if the first succeeded.
				;8595
				;8596	BBX.RDLK.MAKE.MASK:
				;8597		;---------------------------------------;
				;8598		[W0] <-- MEM.LOCK (VA), LEN(DL),	; read selected byte
E 46C  004C,0004,0400,0471 J 471;8599		GOTO [BBX.MAKE.MASK.WAIT.BDISP] 	; form mask, return to caller
				;8600
				;8601
				;8602	;	Subroutine to form a mask of the selected bit.
				;8603	;
				;8604	;	Entry conditions:
				;8605	;		SC	=	Position of bit within longword
				;8606	;
				;8607	;	Exit conditions:
				;8608	;		W1	=	Mask
				;8609
				;8610	BBX.MAKE.MASK.WAIT.BDISP:
				;8611		;---------------------------------------;
				;8612		[W1] <-- [K1] LSH (SC), LONG,		; form mask from position
				;8613		WAIT BDISP VALID,			; wait until displacement is valid
E 471  0005,4002,0B20,0800 R	;8614		RETURN					; return to caller
				;8615
;8616	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  264
;      CTRL.MIC 	     BLBx										      /REV=
;															       CTRL
;8617	.TOC	"	BLBx"
;8618
;8619	;	These instructions test the low order bit of the source operand.
;8620	;
;8621	;	Mnemonic      Opcode	Operation				Spec	AT/DL		Dispatch	BCOND
;8622	;	--------      ------	---------				----	-----		--------	-----
;8623	;	BLBS		E8	if src.rl<0> eql 1			1	r/l		BLBX..		SHF<0>
;8624	;					then PC <-- PC + sext(displ.bb)
;8625	;	BLBC		E9	if src.rl<0> eql 0			1	r/l		BLBX..		~SHF<0>
;8626	;					then PC <-- PC + sext(displ.bb)
;8627	;
;8628	;	Entry conditions:
;8629	;		source queue	=	src.rl operand
;8630	;		dest queue	=	none
;8631	;		branch queue	=	conditional branch entry, including prediction
;8632	;		field queue	=	none
;8633	;		DL		=	LONG
;8634	;		Ibox state	=	running, has updated the PC with predicted address
;8635	;		Mbox state	=	running
;8636	;
;8637	;	Exit conditions:
;8638	;		The prediction state is evaluated and sent to the Ibox and a microtrap is generated
;8639	;		if the prediction is wrong.
;8640	;		The branch queue entry is retired.
;8641	;
;8642	;	Condition codes:
;8643	;		N <-- N
;8644	;		Z <-- Z
;8645	;		V <-- V 		[Integer overflow trap disabled.]
;8646	;		C <-- C
;8647	;
				;8648	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  265
;      CTRL.MIC 	     BLBx										      /REV=
;															       CTRL
				;8649
				;8650	;	BLBx operation:
				;8651	;
				;8652	;		if (src.rl<0> eql x) then PC <-- PC + sext(displ.bb)
				;8653
				;8654	BLBX..:
				;8655		;********** Hardware dispatch **********;
				;8656		Q <-- PASSA [S1], LONG, 		; test low bit in shifter
				;8657		RETIRE COND BQ ENTRY,			; wait for valid bdisp, test
				;8658							; prediction and trap if wrong,
				;8659							; retire BQE
E 15C  000E,4000,2080,1000 L	;8660		LAST CYCLE				; decode next instruction
				;8661
				;8662	;= END CTRL
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  266
;    MULDIV.MIC 	     MULDIV.MIC -- Multiply and Divide Instructions					      /REV=
;
				;8663	.TOC	"MULDIV.MIC -- Multiply and Divide Instructions"
				;8664	.TOC	"Revision 1.2"
				;8665
				;8666	;	Dan Miner, Bob Supnik
				;8667
;8668	.nobin
;8669	;****************************************************************************
;8670	;*									    *
;8671	;*  COPYRIGHT (c) 1987, 1988, 1989, 1990, 1991, 1992 BY 		    *
;8672	;*  DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASSACHUSETTS.		    *
;8673	;*  ALL RIGHTS RESERVED.						    *
;8674	;*									    *
;8675	;*  THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED   *
;8676	;*  ONLY IN  ACCORDANCE WITH  THE  TERMS  OF  SUCH  LICENSE  AND WITH THE   *
;8677	;*  INCLUSION OF THE ABOVE COPYRIGHT NOTICE.  THIS SOFTWARE OR ANY  OTHER   *
;8678	;*  COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY   *
;8679	;*  OTHER PERSON.  NO TITLE TO AND OWNERSHIP OF  THE  SOFTWARE IS  HEREBY   *
;8680	;*  TRANSFERRED.							    *
;8681	;*									    *
;8682	;*  THE INFORMATION IN THIS SOFTWARE IS  SUBJECT TO CHANGE WITHOUT NOTICE   *
;8683	;*  AND  SHOULD  NOT  BE  CONSTRUED AS	A COMMITMENT BY DIGITAL EQUIPMENT   *
;8684	;*  CORPORATION.							    *
;8685	;*									    *
;8686	;*  DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE  OR  RELIABILITY OF ITS   *
;8687	;*  SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL.		    *
;8688	;*									    *
;8689	;****************************************************************************
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  267
;    MULDIV.MIC 	     Revision History									      /REV=
;
;8690	.TOC	"	Revision History"
;8691
;8692	; Edit	  Date	 Who	     Description
;8693	; ---- --------- ---	---------------------
;8694	;    2 08-Mar-91 GMU	Symptom: Warm MULLx instructions set PSL<V> incorrectly
;8695	;				 when the signs of the operands are different.
;8696	;				 This was caused by a microbranch on the sign
;8697	;				 bit of the multiplier when the multiplicand
;8698	;				 was actually being tested.
;8699	;			Cure:	 At MULL.WARM, pass the multiplier on the A
;8700	;				 bus and the multiplicand on the B bus to
;8701	;				 correctly setup the test on multiplier sign.
;8702	;    1 13-Nov-90 GMU	Symptom: Ibox enters infinite RXS stall on an EDIV
;8703	;				 whose final two specifiers are auto-xcrement
;8704	;				 and GPR, with identical register values.  The
;8705	;				 stall is due to a simultaneous reference of
;8706	;				 these two specifiers by the microcode, which
;8707	;				 causes the Ibox to see a source queue retire
;8708	;				 for the GPR before the scoreboard is incremented,
;8709	;				 which causes the scoreboard to decrement below
;8710	;				 zero.
;8711	;			Cure:	 Separate the queue references for the final
;8712	;				 two specifiers such that they are in different
;8713	;				 microinstructions.
;8714	; (1)0 20-Jul-90 GMU	Initial production microcode.
;8715	;
;8716	; Begin version 1.0 here
;8717	;   15 19-Jul-90 GMU	Update with Bob's review comments.
;8718	;   14 05-Jun-90 GMU	Update SEQ.COND names to match implementation.
;8719	;   13 26-Apr-90 GMU	Convert '*' fill constraints to 'x' constraints.
;8720	;   12 21-Mar-90 DGM	Update comments
;8721	;   11 03-Feb-90 GMU	Document simultaneous reference restriction for EDIV.
;8722	;   10 18-Jan-90 DGM	Fix uCode restriction violation (cannot read Q after SMUL/UDIV)
;8723	;			  and rename FBOX.DISABLE to FBOX.CONDITION
;8724	;    9 16-Jan-90 DGM	Change field queue alignment
;8725	;    8 11-Jan-90 DGM	Fix bug in EDIV
;8726	;    7 28-Nov-89 DGM	Optimize MULx and DIVx flows.  Also fixed bug in EDIV
;8727	;    6 26-Sep-89 DGM	Fix MULBn overflow and EDIV divide by zero
;8728	;    5 21-Sep-89 GMU	Create INT.MUL.LONG entry point to be shared with INDEX.
;8729	;    4 28-Aug-89 DGM	Fix multiple bugs in EDIV & one in multiply code
;8730	;    3 17-Aug-89 GMU	convert split dispatch to use field queue for EDIV.
;8731	;    2 22-Jun-89 DGM	Add warm MUL & DIV microcode
;8732	;    1	2-Dec-88 DB	Add FBOX DEST CHECK -- for new Fbox interface
;8733	; (0)0	3-Dec-87 RMS	Trial microcode.
;8734
				;8735	.bin
				;8736	;= BEGIN MULDIV
;8737	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  268
;    MULDIV.MIC 	     Revision History									      /REV=
;															     MULDIV
;8738
;8739	;	This module implements integer multiply and divide.
;8740	;	The instructions implemented here are:
;8741	;
;8742	;	Opcode	 Instruction							N Z V C 	Exceptions
;8743	;	------	 -----------							------- 	----------
;8744	;
;8745	;	86	 DIVB2 divr.rb, quo.mb						* * * 0 	iov, idvz
;8746	;	C6	 DIVL2 divr.rl, quo.ml						* * * 0 	iov, idvz
;8747	;	A6	 DIVW2 divr.rw, quo.mw						* * * 0 	iov, idvz
;8748	;
;8749	;	87	 DIVB3 divr.rb, divd.rb, quo.wb 				* * * 0 	iov, idvz
;8750	;	C7	 DIVL3 divr.rl, divd.rl, quo.wl 				* * * 0 	iov, idvz
;8751	;	A7	 DIVW3 divr.rw, divd.rw, quo.ww 				* * * 0 	iov, idvz
;8752	;
;8753	;	7B	 EDIV divr.rl, divd.rq, quo.wl, rem.wl				* * * 0 	iov, idvz
;8754	;
;8755	;	7A	 EMUL mulr.rl, muld.rl, add.rl, prod.wq 			* * 0 0
;8756	;
;8757	;	84	 MULB2 mulr.rb, prod.mb 					* * * 0 	iov
;8758	;	C4	 MULL2 mulr.rl, prod.ml 					* * * 0 	iov
;8759	;	A4	 MULW2 mulr.rw, prod.mw 					* * * 0 	iov
;8760	;
;8761	;	85	 MULB3 mulr.rb, muld.rb, prod.wb				* * * 0 	iov
;8762	;	C5	 MULL3 mulr.rl, muld.rl, prod.wl				* * * 0 	iov
;8763	;	A5	 MULW3 mulr.rw, muld.rw, prod.ww				* * * 0 	iov
;8764	;
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  269
;    MULDIV.MIC 	     Revision History									      /REV=
;															     MULDIV
;8765
;8766	;					CAUTION
;8767	;					-------
;8768	;
;8769	;	Ebox microcode for any instruction whose IROM entry contains a .ax or
;8770	;	.vx specifier followed immediately by a .rx, .mx, or .vx specifier may not
;8771	;	reference the source queue entries for this pair of specifiers in the
;8772	;	same microinstruction.	This restriction is necessary to avoid getting
;8773	;	the incorrect operand data for the second specifier of the pair if the
;8774	;	first specifier of the pair is auto-increment, auto-decrement, or auto-increment
;8775	;	deferred, and the second specifier of the pair is register mode using the
;8776	;	same register specified for the first specifier of the pair.  Because the Ibox
;8777	;	must write both the address operand to the MD, and the auto-inc/dec value
;8778	;	to the GPR, the Ebox may read the old value of the GPR if both specifiers
;8779	;	are referenced in the same microword.  In addition, a simultaneous reference
;8780	;	to these specifiers may cause an infinite Ibox RXS stall if the source
;8781	;	queue retire for the second GPR specifier arrives at the Ibox before
;8782	;	the scoreboard is incremented.
;8783	;
;8784	;	This restriction does not apply if, by context, it is known that the
;8785	;	second specifier of the pair is not register mode.
;8786	;
;8787	;	One instruction processed by this module is affected by this
;8788	;	restriction.  The following table lists the restriction for each instruction using
;8789	;	the notation [spec n; spec n+1] to denote a restriction in referencing the
;8790	;	source queue entries for these two specifiers in the same microinstruction.
;8791	;
;8792	;	Entry Point   Opcode   Mnemonic 		   Restriction
;8793	;	-----------   ------   -------- 	----------------------------------
;8794	;	EDIV..		7B	EDIV		[spec 3; spec 4]
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  270
;    MULDIV.MIC 	     MULBn, MULWn, MULLn								      /REV=
;															     MULDIV
;8795	.TOC	"	MULBn, MULWn, MULLn"
;8796
;8797	;	These instructions multiply two integers.
;8798	;
;8799	;	Mnemonic      Opcode	Operation				Spec	AT/DL		Dispatch
;8800	;	--------      ------	---------				----	-----		--------
;8801	;	MULB2		84	prod.mb <-- mulr.rb * prod.mb		2	rm/bb		MULBN..
;8802	;	MULW2		A4	prod.mw <-- mulr.rw * prod.mw		2	rm/ww		MULWN..
;8803	;	MULL2		C4	prod.ml <-- mulr.rl * prod.ml		2	rm/ll		MULLN..
;8804	;
;8805	;	MULB3		85	prod.wb <-- mulr.rb * muld.rb		3	rrw/bbb 	MULBN..
;8806	;	MULW3		A5	prod.ww <-- mulr.rw * muld.rw		3	rrw/www 	MULWN..
;8807	;	MULL3		C5	prod.wl <-- mulr.rl * muld.rl		3	rrw/lll 	MULLN..
;8808	;
;8809	;	Entry conditions:		(2 operand)	(3 operand)
;8810	;		source queue	=	mulr.rx 	mulr.rx   operand
;8811	;					prod.mx 	muld.rx   operand
;8812	;		dest queue	=	prod.mx 	prod.wx   result
;8813	;		branch queue	=	none
;8814	;		field queue	=	none
;8815	;		DL		=	data type of last (prod) operand
;8816	;		Ibox state	=	running
;8817	;		Mbox state	=	running
;8818	;
;8819	;	Exit conditions:
;8820	;		The PSL condition codes are set.
;8821	;		The result has been written to the destination memory location or register.
;8822	;
;8823	;	Condition codes:
;8824	;		N <-- product LSS 0
;8825	;		Z <-- product EQL 0
;8826	;		V <-- overflow			[Integer overflow trap enabled.]
;8827	;		C <-- 0
;8828	;
				;8829	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  271
;    MULDIV.MIC 	     MULBn, MULWn, MULLn								      /REV=
;															     MULDIV
				;8830
				;8831	;	MULBn operation:
				;8832	;
				;8833	;		dst.mb <-- src.rb * dst.mb	(2 operands)
				;8834	;		dst.wb <-- src1.rb * src2.rb	(3 operands)
				;8835
				;8836	MULBN..:
				;8837		;********** Hardware dispatch **********;
				;8838		Q <-- PASSA [S1], LONG, 		; get first operand (multiplier)
E 160  0082,6000,0880,0442 J 442;8839		[W1] <-- 000000[00]			; clear high-order result
				;8840
				;8841		;---------------------------------------;
				;8842		[W0] <-- [S1] LSH [24.], LONG,		; left justify second operand (multiplicand)
E 442  A001,5802,0480,45E6 B 4E6;8843		CASE [A.7-5] AT [MULBN.MULR.POS]	; break out on sign of multiplier
				;8844
				;8845	;= ALIGNLIST	011x	(MULBN.MULR.POS,	MULBN.MULR.NEG)
				;8846
				;8847	MULBN.MULR.NEG:
				;8848		;---------------------------------------; a<7> = 1:
			    p277;8849		[W1] <-- [W1] SMUL [W0], LONG,		; do first multiply step
E 4EE  0E02,0008,0820,22A2 S 2A2;8850		CALL [INT.MULT.7.STEPS] 		; W1<31:16> <-- Q<7:0> * W0<31:24>
				;8851							; >> No Q write last cycle
				;8852
				;8853		;---------------------------------------;
				;8854		[W1] <-- [W1] - [W0], LONG,		; adjust result for negative multiplier
				;8855							; >> No Q read this cycle
E 4EF  0A80,0008,0820,04E7 J 4E7;8856		GOTO [MULBN.CONT]			; join common flow
				;8857
				;8858	MULBN.MULR.POS:
				;8859		;---------------------------------------; a<7> = 0:
			    p277;8860		[W1] <-- [W1] SMUL [W0], LONG,		; do first multiply step
E 4E6  0E02,0008,0820,22A2 S 2A2;8861		CALL [INT.MULT.7.STEPS] 		; W1<31:16> <-- Q<7:0> * W0<31:24>
				;8862							; >> No Q write last cycle
				;8863
				;8864	MULBN.CONT:
				;8865		;---------------------------------------;
				;8866		Q&, [DST] <-- ZEXT [W1] RSH [16.],	; write byte result, save in Q
E 4E7  0003,D016,2400,0473 J 473;8867		LEN(DL) 				; Q & VA are written as long despite len(dl)
				;8868							; >> No Q read this cycle
				;8869
				;8870		;---------------------------------------;
E 473  0001,D812,0800,0475 J 475;8871		[W1] <-- ZEXT [W1] RSH [24.], LONG	; get result extension
				;8872
				;8873		;---------------------------------------;
				;8874		[WBUS] <-- [Q] LSH [24.], LEN(DL),	; set shifter sign to sign of result
			    p273;8875		SET PSL CC.IIII,			; set psl cc's
E 475  0001,5806,20AD,0481 J 481;8876		GOTO [MULX.CHECK.OVERFLOW]		; check overflow and exit
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  272
;    MULDIV.MIC 	     MULBn, MULWn, MULLn								      /REV=
;															     MULDIV
				;8877
				;8878	;	MULWn operation:
				;8879	;
				;8880	;		dst.mw <-- src.rw * dst.mw	(2 operands)
				;8881	;		dst.ww <-- src1.rw * src2.rw	(3 operands)
				;8882
				;8883	MULWN..:
				;8884		;********** Hardware dispatch **********;
				;8885		Q <-- PASSA [S1], LONG, 		; get first operand (multiplier)
E 162  0082,6000,0880,0443 J 443;8886		[W1] <-- 000000[00]			; clear high-order result
				;8887
				;8888		;---------------------------------------;
				;8889		[W0] <-- [S1] LSH [16.], LONG,		; left justify second operand (multiplicand)
E 443  C001,5002,0480,46F6 B 4F6;8890		CASE [A.15-12] AT [MULWN.MULR.POS]	; break out on sign of multiplier
				;8891
				;8892	;= ALIGNLIST	011x	(MULWN.MULR.POS,	MULWN.MULR.NEG)
				;8893
				;8894	MULWN.MULR.NEG:
				;8895		;---------------------------------------; a<15> = 1:
			    p277;8896		[W1] <-- [W1] SMUL [W0], LONG,		; do first multiply step
E 4FE  0E02,0008,0820,22A1 S 2A1;8897		CALL [INT.MULT.15.STEPS]		; W1<31:0> <-- Q<15:0> * W0<31:16>
				;8898							; >> No Q write last cycle
				;8899
				;8900		;---------------------------------------;
				;8901		[W1] <-- [W1] - [W0], LONG,		; adjust result for negative multiplier
				;8902							; >> No Q read this cycle
E 4FF  0A80,0008,0820,04F7 J 4F7;8903		GOTO [MULWN.CONT]			; join common flow
				;8904
				;8905	MULWN.MULR.POS:
				;8906		;---------------------------------------; a<15> = 0:
			    p277;8907		[W1] <-- [W1] SMUL [W0], LONG,		; do first multiply step
E 4F6  0E02,0008,0820,22A1 S 2A1;8908		CALL [INT.MULT.15.STEPS]		; W1<31:0> <-- Q<15:0> * W0<31:16>
				;8909							; >> No Q write last cycle
				;8910
				;8911	MULWN.CONT:
				;8912		;---------------------------------------;
				;8913		VA <-- B [W1],				; save result
E 4F7  0081,D013,0800,0477 J 477;8914		[W1] <-- ZEXT [W1] RSH [16.], LONG	; extract extended result
				;8915							; >> No Q read last cycle
				;8916
				;8917		;---------------------------------------;
				;8918		[DST] <-- [VA], LEN(DL),		; write word result
				;8919		Q <-- [VA] LSH [16.],			; set shifter sign to sign of result
				;8920							; Q is written as long despite len(dl)
			    p273;8921		SET PSL CC.IIII,			; set psl cc's
E 477  0003,5004,24BD,0481 J 481;8922		GOTO [MULX.CHECK.OVERFLOW]		; check overflow and exit
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  273
;    MULDIV.MIC 	     MULBn, MULWn, MULLn								      /REV=
;															     MULDIV
				;8923
				;8924	;	MULLn operation:
				;8925	;
				;8926	;		dst.ml <-- src.rl * dst.ml	(2 operands)
				;8927	;		dst.wl <-- src1.rl * src2.rl	(3 operands)
				;8928
				;8929	MULLN..:
				;8930		;********** Hardware dispatch **********;
				;8931		NOP NODEST, MULL,			; tell E-box this instr may still
				;8932							; execute even if F-box is disabled
E 164  2000,0000,0000,D11D B 11D;8933		CASE [FBOX.CONDITION] AT [MULL.HOT]	; case on F-box disabled
				;8934
				;8935	;= ALIGNLIST 110x	(MULL.HOT,		MULL.WARM)
				;8936
				;8937	MULL.HOT:
				;8938		;---------------------------------------;
				;8939		FBOX OPERAND A[S1] B[S2], LONG, 	; send operands to F-box
				;8940		FBOX DEST CHECK,			; update F-box scoreboard
E 11D  1002,4348,0080,1000 L	;8941		LAST CYCLE NO RETIRE			; decode next instruction
				;8942
				;8943	MULL.WARM:
				;8944		;---------------------------------------;
				;8945		Q <-- PASSA [S1], LONG, 		; get first operand (multiplier)
E 11F  0082,4048,0480,0415 J 415;8946		[W0] <-- B [S2] 			; get second operand (multiplicand)
				;8947
				;8948		;---------------------------------------;
			    p276;8949		[W1] <-- 0,				; clear W1 for multiply
E 415  E000,C002,0800,6796 C 496;8950		CALL CASE [A31.BQA.BNZ1] AT [INT.MULT.LONG.POS] ; case on sign of multiplier
				;8951							; W<31:0>'Q<31:0> <-- Q<31:0> * W0<31:0>
				;8952							; >> no Q write this cycle
				;8953							; >> call requires all 6 microstack locations
				;8954
				;8955		;---------------------------------------;
				;8956		[DST] <-- PASSA [Q], LONG,		; write longword result, set shifter sign
				;8957		VA <-- [Q],				; pass result through ALU for correct CC's
E 416  0000,4003,24AD,0481 J 481;8958		SET PSL CC.IIII 			; set psl.nz
				;8959
				;8960	MULX.CHECK.OVERFLOW:
				;8961		;---------------------------------------;
				;8962		[WBUS] <-- [SHIFT.SIGN] XOR [W1], LEN(DL), ; check extended result = sign ext of result
				;8963		SET PSL CC.PPJP,			; set psl.v on mismatch
E 481  0600,0014,239E,9800 L	;8964		LAST CYCLE CHECK OVERFLOW		; decode next instruction
				;8965
;8966	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  274
;    MULDIV.MIC 	     EMUL										      /REV=
;															     MULDIV
;8967	.TOC	"	EMUL"
;8968
;8969	;	This instruction multiplies two integers to produce a quadword.
;8970	;
;8971	;	Mnemonic      Opcode	Operation				Spec	AT/DL		Dispatch
;8972	;	--------      ------	---------				----	-----		--------
;8973	;	EMUL		7A	prod.wq <-- mulr.rl * muld.rl + 	4     rrrw/lllq 	EMUL..
;8974	;					    sext(add.rl)
;8975	;
;8976	;	Entry conditions:
;8977	;		source queue	=	mulr.rl operand
;8978	;					muld.rl operand
;8979	;					add.rl	operand
;8980	;		dest queue	=	prod.wq result
;8981	;		branch queue	=	none
;8982	;		field queue	=	none
;8983	;		DL		=	QUAD
;8984	;		Ibox state	=	running
;8985	;		Mbox state	=	running
;8986	;
;8987	;	Exit conditions:
;8988	;		The PSL condition codes are set.
;8989	;		The result has been written to the destination memory location or register.
;8990	;
;8991	;	Condition codes:
;8992	;		N <-- product LSS 0
;8993	;		Z <-- product EQL 0
;8994	;		V <-- 0 			[Integer overflow trap disabled.]
;8995	;		C <-- 0
;8996	;
				;8997	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  275
;    MULDIV.MIC 	     EMUL										      /REV=
;															     MULDIV
				;8998
				;8999	;	EMUL operation:
				;9000	;
				;9001	;		prod.wq <-- mulr.rl * muld.rl + sext(add.rl)
				;9002
				;9003	EMUL..:
				;9004		;********** Hardware dispatch **********;
				;9005		Q <-- PASSA [S1], LONG, 		; get first operand (multiplier)
E 166  0082,4048,0480,0421 J 421;9006		[W0] <-- B [S2] 			; get second operand (multiplicand)
				;9007
				;9008		;---------------------------------------;
			    p276;9009		[W1] <-- [S1], LONG,			; get third operand (addend)
E 421  E000,0000,0880,6796 C 496;9010		CALL CASE [A31.BQA.BNZ1] AT [INT.MULT.LONG.POS] ; case on sign of multiplier
				;9011							; W1<31:0>'Q<31:0> <-- Q<31:0> * W0<31:0>
				;9012							;			       + W1<31:0>
				;9013							; >> no Q write this cycle
				;9014							; >> call requires all 6 microstack locations
				;9015
				;9016		;---------------------------------------;
				;9017		[DST] <-- [Q], LONG,			; write lower longword result
E 422  0000,0000,24AD,0482 J 482;9018		SET PSL CC.IIII 			; set psl.nz
				;9019
				;9020		;---------------------------------------;
				;9021		[DST] <-- [W1], LONG,			; write upper longword result
				;9022		SET PSL CC.IIIP.QUAD,			; set psl cc's based on 2nd LW
E 482  0000,0000,242E,1000 L	;9023		LAST CYCLE				; decode next instruction
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  276
;    MULDIV.MIC 	     EMUL										      /REV=
;															     MULDIV
				;9024
				;9025	;	Subroutine to perform a longword multiply
				;9026	;
				;9027	;	Entry conditions:
				;9028	;		Q	=	multiplier
				;9029	;		W0	=	multiplicand
				;9030	;		W1	=	0 or addend
				;9031	;		Q not written in the calling microword
				;9032	;		Call case on sign of multiplier
				;9033	;
				;9034	;	Exit conditions:
				;9035	;		W1'Q	=	product, adjusted for sign
				;9036	;		Q not readable by return microword
				;9037	;
				;9038	;	*******************************************************************
				;9039	;	* WARNING: THIS SUBROUTINE REQUIRES ALL SIX MICROSTACK LOCATIONS, *
				;9040	;	* AND MAY NOT BE CALLED FROM A SUBROUTINE.			  *
				;9041	;	*******************************************************************
				;9042
				;9043	;= ALIGNLIST	011x	(INT.MULT.LONG.POS,	INT.MULT.LONG.NEG)
				;9044
				;9045	INT.MULT.LONG.POS:
				;9046		;---------------------------------------; a<31> = 0:
			    p277;9047		[W1] <-- [W1] SMUL [W0], LONG,		; do first multiply step
E 496  0E02,0008,0820,22A0 S 2A0;9048		CALL [INT.MULT.31.STEPS]		; W1<31:0>'Q<31:0> <-- Q<31:0> * W0<31:0>
				;9049							; >> No Q write last cycle
				;9050
				;9051	WAIT.ONE.CYCLE: 				; Single-cycle routine to wait
				;9052		;---------------------------------------; one cycle
E 497  0000,0000,2000,0800 R	;9053		RETURN					; >> No Q read this cycle
				;9054
				;9055	INT.MULT.LONG.NEG:
				;9056		;---------------------------------------; a<31> = 1:
			    p277;9057		[W1] <-- [W1] SMUL [W0], LONG,		; do first multiply step
E 49E  0E02,0008,0820,22A0 S 2A0;9058		CALL [INT.MULT.31.STEPS]		; W1<31:0>'Q<31:0> <-- Q<31:0> * W0<31:0>
				;9059							; >> No Q write last cycle
				;9060
				;9061		;---------------------------------------;
				;9062		[W1] <-- [W1] - [W0], LONG,		; adjust result for negative multiplier
E 49F  0A80,0008,0820,0800 R	;9063		RETURN					; return to caller
				;9064							; >> No Q read this cycle
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  277
;    MULDIV.MIC 	     EMUL										      /REV=
;															     MULDIV
				;9065
				;9066	;	Subroutines to perform 31, 15, 7, 3, or 1 multiply steps.
				;9067	;
				;9068	;	Entry conditions:
				;9069	;		Q	=	multiplier
				;9070	;		W0	=	multiplicand
				;9071	;		W1	=	0 or addend
				;9072	;		Q not written in the calling microword
				;9073	;
				;9074	;	Exit conditions:
				;9075	;		W1'Q	=	product, unadjusted for sign
				;9076	;		Q not readable by return microword
				;9077	;
				;9078	;	************************************************************************
				;9079	;	* WARNING: INT.MULT.31.STEPS REQUIRES 5 OF THE 6 MICROSTACK LOCATIONS, *
				;9080	;	* AND MAY NOT BE CALLED WHILE NESTED MORE THAN 1 LEVEL. 	       *
				;9081	;	************************************************************************
				;9082
				;9083	INT.MULT.31.STEPS:
				;9084		;---------------------------------------;
				;9085		[W1] <-- [W1] SMUL [W0], LONG,		; do signed multiply step
E 2A0  0E02,0008,0820,22A1 S 2A1;9086		CALL [INT.MULT.15.STEPS]		; call subroutine to do 15 steps
				;9087
				;9088	INT.MULT.15.STEPS:
				;9089		;---------------------------------------;
				;9090		[W1] <-- [W1] SMUL [W0], LONG,		; do signed multiply step
E 2A1  0E02,0008,0820,22A2 S 2A2;9091		CALL [INT.MULT.7.STEPS] 		; call subroutine to do 7 steps
				;9092							; fall through to do 7 more steps
				;9093
				;9094	INT.MULT.7.STEPS:
				;9095		;---------------------------------------;
				;9096		[W1] <-- [W1] SMUL [W0], LONG,		; do signed multiply step
E 2A2  0E02,0008,0820,22A3 S 2A3;9097		CALL [INT.MULT.3.STEPS] 		; call subroutine to do 3 steps
				;9098							; fall through to do 3 more steps
				;9099
				;9100	INT.MULT.3.STEPS:
				;9101		;---------------------------------------;
				;9102		[W1] <-- [W1] SMUL [W0], LONG,		; do signed multiply step
E 2A3  0E02,0008,0820,22A4 S 2A4;9103		CALL [INT.MULT.1.STEP]			; call subroutine to do 1 step
				;9104							; fall through to do 1 more step
				;9105
				;9106	INT.MULT.1.STEP:
				;9107		;---------------------------------------;
				;9108		[W1] <-- [W1] SMUL [W0], LONG,		; do signed multiply step
E 2A4  0E02,0008,0820,0800 R	;9109		RETURN
				;9110
;9111	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  278
;    MULDIV.MIC 	     DIVBn, DIVWn, DIVLn								      /REV=
;															     MULDIV
;9112	.TOC	"	DIVBn, DIVWn, DIVLn"
;9113
;9114	;	These instructions divide two integers and return the quotient.
;9115	;
;9116	;	Mnemonic      Opcode	Operation				Spec	AT/DL		Dispatch
;9117	;	--------      ------	---------				----	-----		--------
;9118	;	DIVB2		86	quo.mb <-- quo.mb / divr.rb		2	rm/bb		DIVBN..
;9119	;	DIVW2		A6	quo.mw <-- quo.mw / divr.rw		2	rm/ww		DIVWN..
;9120	;	DIVL2		C6	quo.ml <-- quo.ml / divr.rl		2	rm/ll		DIVLN..
;9121	;
;9122	;	DIVB3		87	quo.wb <-- divd.rb / divr.rb		3	rrw/bbb 	DIVBN..
;9123	;	DIVW3		A7	quo.ww <-- divd.rw / divr.rw		3	rrw/www 	DIVWN..
;9124	;	DIVL3		C7	quo.wl <-- divd.rl / divr.rl		3	rrw/lll 	DIVLN..
;9125	;
;9126	;	Entry conditions:		(2 operand)	(3 operand)
;9127	;		source queue	=	divr.rx 	divr.rx   operand
;9128	;					quo.mx		divd.rx   operand
;9129	;		dest queue	=	quo.mx		quo.wx	  result
;9130	;		branch queue	=	none
;9131	;		field queue	=	none
;9132	;		DL		=	data type of last (quo) operand
;9133	;		Ibox state	=	running
;9134	;		Mbox state	=	running
;9135	;
;9136	;	Exit conditions:
;9137	;		The PSL condition codes are set.
;9138	;		The result has been written to the destination memory location or register.
;9139	;
;9140	;	Condition codes:
;9141	;		N <-- product LSS 0
;9142	;		Z <-- product EQL 0
;9143	;		V <-- overflow or divide by zero	[Integer overflow trap enabled.]
;9144	;		C <-- 0
;9145	;
;9146	;	Notes:
;9147	;	    1)	Performance:  After the UDIV steps are finished, there is a NOP cycle
;9148	;		inserted before Q is read to meet a microcode restriction.  (Q is not
;9149	;		readable in the cycle immediately after a SMUL/UDIV instruction.)
;9150	;
				;9151	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  279
;    MULDIV.MIC 	     DIVBn, DIVWn, DIVLn								      /REV=
;															     MULDIV
				;9152
				;9153	;	DIVBn operation:
				;9154	;
				;9155	;		quo.mb <-- quo.mb / divr.rb	(2 operand)
				;9156	;		quo.wb <-- divd.rb / divr.rb	(3 operand)
				;9157
				;9158	DIVBN..:
				;9159		;********** Hardware dispatch **********;
				;9160		[W0] <-- B [S1], LEN(DL),		; get divisor, zero ext, test cc's
				;9161		Q <-- PASSA [S2],			; get dividend, test msb
E 168  0082,4044,0490,0232 J 232;9162			sim cond [s34.000]
				;9163
				;9164		;---------------------------------------;
				;9165		[W2] <-- [Q], LEN(DL),			; save dividend, zero ext
			    p284;9166		Q <-- [Q] LSH [24.],			; left justify dividend
E 232  A003,5804,0CA0,6557 C 257;9167		CALL CASE [A.7-5] AT [IDIV.SETUP]	; case on divd sign to start divide
				;9168							;   get absolute value of divd and divr
				;9169							;   also save signs in state bits
				;9170
				;9171		;---------------------------------------;
			    p281;9172		[W3] <-- [W3] UDIV [W0], LONG,		; do divide step
E 233  0E82,0008,1040,040A J 40A;9173		GOTO [IDIV.8.STEPS]			; go do remaining 8 steps
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  280
;    MULDIV.MIC 	     DIVBn, DIVWn, DIVLn								      /REV=
;															     MULDIV
				;9174
				;9175	;	DIVWn operation:
				;9176	;
				;9177	;		quo.mw <-- quo.mw / divr.rw	(2 operand)
				;9178	;		quo.ww <-- divd.rw / divr.rw	(3 operand)
				;9179
				;9180	DIVWN..:
				;9181		;********** Hardware dispatch **********;
				;9182		[W0] <-- B [S1], LEN(DL),		; get divisor, zero ext, test cc's
				;9183		Q <-- PASSA [S2],			; get dividend, test msb
E 16A  0082,4044,0490,0243 J 243;9184			sim cond [s34.000]
				;9185
				;9186		;---------------------------------------;
				;9187		[W2] <-- [Q], LEN(DL),			; save dividend, zero ext
			    p284;9188		Q <-- [Q] LSH [16.],			; left justify dividend
E 243  C003,5004,0CA0,6657 C 257;9189		CALL CASE [A.15-12] AT [IDIV.SETUP]	; case on divd sign to start divide
				;9190							;   get absolute value of divd and divr
				;9191							;   also save signs in state bits
				;9192
				;9193		;---------------------------------------;
			    p281;9194		[W3] <-- [W3] UDIV [W0], LONG,		; do divide step
E 244  0E82,0008,1040,0409 J 409;9195		GOTO [IDIV.16.STEPS]			; go do remaining 16 steps
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  281
;    MULDIV.MIC 	     DIVBn, DIVWn, DIVLn								      /REV=
;															     MULDIV
				;9196
				;9197	;	DIVLn operation:
				;9198	;
				;9199	;		quo.ml <-- quo.ml / divr.rl	(2 operand)
				;9200	;		quo.wl <-- divd.rl / divr.rl	(3 operand)
				;9201
				;9202	DIVLN..:
				;9203		;********** Hardware dispatch **********;
				;9204		[W0] <-- B [S1], LEN(DL),		; get divisor, zero ext, test cc's
				;9205		Q <-- PASSA [S2],			; get dividend msb
E 16C  0082,4044,0490,0254 J 254;9206			sim cond [s34.000]
				;9207
				;9208		;---------------------------------------;
			    p284;9209		[W2] <-- [Q], LEN(DL),			; save dividend, zero ext
E 254  E000,0004,0CA0,6757 C 257;9210		CALL CASE [A31.BQA.BNZ1] AT [IDIV.SETUP] ; case on divd sign to start divide
				;9211							;   get absolute value of divd and divr
				;9212							;   also save signs in state bits
				;9213
				;9214		;---------------------------------------;
E 255  0E82,0008,1040,0408 J 408;9215		[W3] <-- [W3] UDIV [W0], LONG		; do divide step
				;9216
				;9217		;---------------------------------------;
			    p299;9218		[W3] <-- [W3] UDIV [W0], LONG,		; do divide step
E 408  0E82,0008,1040,22A6 S 2A6;9219		CALL [DIVIDE.15.STEPS]			; do 15 divide steps
				;9220
				;9221	; Enter here from DIVWn flow
				;9222
				;9223	IDIV.16.STEPS:
				;9224		;---------------------------------------;
			    p299;9225		[W3] <-- [W3] UDIV [W0], LONG,		; do divide step
E 409  0E82,0008,1040,22A7 S 2A7;9226		CALL [DIVIDE.7.STEPS]			; do 7 divide steps
				;9227
				;9228	; Enter here from DIVBn flow
				;9229
				;9230	IDIV.8.STEPS:
				;9231		;---------------------------------------;
			    p299;9232		[W3] <-- [W3] UDIV [W0], LONG,		; do divide step
E 40A  0E82,0008,1040,22A7 S 2A7;9233		CALL [DIVIDE.7.STEPS]			; do 7 divide steps
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  282
;    MULDIV.MIC 	     DIVBn, DIVWn, DIVLn								      /REV=
;															     MULDIV
				;9234
				;9235	;	Integer divide, continued.
				;9236	;	Divide complete.  For no overflow cases, adjust sign of quotient.
				;9237
				;9238	;	At this point,
				;9239	;		W2	=	dividend
				;9240	;		Q	=	quotient
				;9241
				;9242		;---------------------------------------;
				;9243		NOP,					; >> Q not readable this cycle
E 40B  4000,0000,2000,4A48 B 448;9244		CASE [STATE.2-0] AT [IDIV.STATE.00]	; case on signs of divisor, dividend
				;9245
				;9246	;= ALIGNLIST *00x	(IDIV.STATE.00, 	IDIV.STATE.01,
				;9247	;=			 IDIV.STATE.10, 	IDIV.STATE.11)
				;9248	;  STATE<2> = 0 --> STATE<2:0> = 0??
				;9249
				;9250	IDIV.STATE.00:
				;9251		;---------------------------------------; divisor +, dividend +:
				;9252		[DST] <-- [Q], LEN(DL), 		; store quotient
				;9253		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 448  0000,0004,24AD,1000 L	;9254		LAST CYCLE				; decode next instruction (no overflow)
				;9255
				;9256	IDIV.STATE.01:
				;9257		;---------------------------------------; divisor +, dividend -:
			    p283;9258		[W0] <-- -[Q], LEN(DL), 		; negate quotient
E 44A  0D00,0054,0400,045C J 45C;9259		GOTO [IDIV.STATE.11.NO.OVERFLOW]	; go store result
				;9260
				;9261	IDIV.STATE.10:
				;9262		;---------------------------------------; divisor -, dividend +:
			    p283;9263		[W0] <-- -[Q], LEN(DL), 		; negate quotient
E 44C  0D00,0054,0400,045C J 45C;9264		GOTO [IDIV.STATE.11.NO.OVERFLOW]	; go store result
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  283
;    MULDIV.MIC 	     DIVBn, DIVWn, DIVLn								      /REV=
;															     MULDIV
				;9265
				;9266	;	Integer divide, continued.
				;9267	;	Divide complete.  For -/-, test for result = largest negative number.
				;9268
				;9269	;	At this point,
				;9270	;		W0	=	negated quotient
				;9271	;		W2	=	dividend
				;9272	;		Q	=	quotient
				;9273	;		alu cc's =	set from quotient negation
				;9274
				;9275	IDIV.STATE.11:
				;9276		;---------------------------------------; divisor -, dividend -:
				;9277		NODST <-- -[Q], LEN(DL),		; negate quotient
			    p276;9278		[W0] <-- PASSB [Q],			; copy positive quotient to W0
E 44E  0D00,8056,0400,2497 S 497;9279		CALL [WAIT.ONE.CYCLE]			; wait for condition codes
				;9280
				;9281		;---------------------------------------;
				;9282		NOP,					; nothing to do...
E 44F  2000,0000,2000,415C B 45C;9283		CASE [ALU.NZV] AT [IDIV.STATE.11.NO.OVERFLOW]	; case on overflow
				;9284
				;9285	;= ALIGNLIST 110x	(IDIV.STATE.11.NO.OVERFLOW,	IDIV.STATE.11.OVERFLOW)
				;9286
				;9287	IDIV.STATE.11.NO.OVERFLOW:
				;9288		;---------------------------------------; alu.v = 0:
				;9289		[DST] <-- [W0], LEN(DL),		; store quotient
				;9290		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 45C  0000,0004,241D,1000 L	;9291		LAST CYCLE				; decode next instruction (no overflow)
				;9292
				;9293	IDIV.STATE.11.OVERFLOW:
				;9294		;---------------------------------------; alu.v = 1:
				;9295		[DST] <-- [W2], LEN(DL),		; store dividend as result
E 45E  0000,0004,243D,0484 J 484;9296		SET PSL CC.IIII 			; set psl cc's, psl map is iiii
				;9297
				;9298	SET.PSL.V:
				;9299		;---------------------------------------;
				;9300		SET PSL(V),				; set psl.v
E 484  0080,2008,200E,9800 L	;9301		LAST CYCLE CHECK OVERFLOW		; decode next instruction
				;9302
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  284
;    MULDIV.MIC 	     DIVBn, DIVWn, DIVLn								      /REV=
;															     MULDIV
				;9303
				;9304	;	Integer divide setup routine.
				;9305	;	This routine sets up the data path for an integer divide.
				;9306	;
				;9307	;	Entry conditions:
				;9308	;		W0	=	divisor
				;9309	;		W2	=	dividend
				;9310	;		Q	=	left justified dividend
				;9311	;		alu cc's =	set from divisor
				;9312	;
				;9313	;	Exit conditions:
				;9314	;		W0	=	!divisor!
				;9315	;		W2	=	dividend
				;9316	;		W3	=	0
				;9317	;		Q	=	!left justified dividend!
				;9318
				;9319	;= ALIGNLIST 011x	(IDIV.SETUP,		IDIV.SETUP.NEG)
				;9320
				;9321	IDIV.SETUP:
				;9322		;---------------------------------------; a<msb> = 0:
				;9323		[W3] <-- [Q], LONG,			; save left justified dividend
E 257  2000,0000,10A0,4181 B 281;9324		CASE [ALU.NZV] AT [IDIV.SETUP.DIVR.POS] ; case on divisor
				;9325
				;9326	IDIV.SETUP.NEG:
				;9327		;---------------------------------------; a<msb> = 1:
				;9328		[W3] <-- -[Q], LONG,			; negate left justified dividend
				;9329		STATE.0 <-- 1,				; flag negative dividend
E 25F  2D00,0050,1008,C181 B 281;9330		CASE [ALU.NZV] AT [IDIV.SETUP.DIVR.POS] ; case on divisor
				;9331
				;9332	;= ALIGNLIST 00xx	(IDIV.SETUP.DIVR.POS,	IDIV.SETUP.DIVR.ZERO,
				;9333	;=			 IDIV.SETUP.DIVR.NEG,				)
				;9334	;  ALU.NZVC set by move --> V = C = 0
				;9335
				;9336	IDIV.SETUP.DIVR.ZERO:
				;9337		;---------------------------------------; alu.nz = 01:
				;9338		[DST] <-- [W2], LEN(DL),		; result is dividend
E 285  0000,0004,243D,05BF J 5BF;9339		SET PSL CC.IIII 			; set psl cc's, psl map is iiii
				;9340
				;9341	DIVIDE.BY.ZERO:
				;9342		;---------------------------------------;
				;9343		SET PSL(V),				; set psl.v
			    p122;9344		RETIRE INSTRUCTION,			; retire instruction
E 5BF  1080,6008,200E,8048 J 048;9345		GOTO [IE.DIVIDE.ERROR..]		; enter exception flows
				;9346
				;9347	IDIV.SETUP.DIVR.NEG:
				;9348		;---------------------------------------; alu.nz = 10:
				;9349		[W0] <-- -[W0], LEN(DL),		; negate divisor
E 289  0D00,000C,0409,0281 J 281;9350		STATE.1 <-- 1				; flag negative divisor
				;9351
				;9352	IDIV.SETUP.DIVR.POS:
				;9353		;---------------------------------------; alu.nz = 00:
				;9354		[W3] <-- [W3] - [W3], LONG,		; clear W3, set alu.c to prime divide loop
				;9355		Q <-- PASSA [W3],			; load !left justified dividend!
E 281  0A82,4020,1040,0800 R	;9356		RETURN					; return to caller
				;9357
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  285
;    MULDIV.MIC 	     DIVBn, DIVWn, DIVLn								      /REV=
;															     MULDIV
;9358	.nobin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  286
;    MULDIV.MIC 	     EDIV										      /REV=
;															     MULDIV
;9359	.TOC	"	EDIV"
;9360	;
;9361	;	This instruction divides two integers and returns both the quotient
;9362	;	and the remainder.
;9363	;
;9364	;	Mnemonic      Opcode	Operation				Spec	AT/DL			Dispatch
;9365	;	--------      ------	---------				----	-----			--------
;9366	;	EDIV		7B	quo.v(m)l <-- divd.rq / divr.rl 	4	rrv(m)m/lqll		EDIV..
;9367	;				rem.wl <-- rem(divd.rq,divr.rl)
;9368	;
;9369	;	Entry conditions:
;9370	;		source queue	=	divr.rl operand
;9371	;					divd.rq operand
;9372	;					quo.ml	operand address (if memory)
;9373	;					rem.ml	operand
;9374	;		dest queue	=	quo.ml result  (if register)
;9375	;					rem.ml result
;9376	;		branch queue	=	none
;9377	;		field queue	=	one valid entry for third (quo) specifier
;9378	;		DL		=	LONG
;9379	;		Ibox state	=	stopped
;9380	;		Mbox state	=	running
;9381	;
;9382	;	Exit conditions:
;9383	;		The PSL condition codes are set.
;9384	;		The result has been written to the destination memory locations or registers.
;9385	;
;9386	;	Condition codes:
;9387	;		N <-- product LSS 0
;9388	;		Z <-- product EQL 0
;9389	;		V <-- overflow or divide by zero	[Integer overflow trap enabled.]
;9390	;		C <-- 0
;9391	;
;9392	;	Notes:
;9393	;		1.  Memory management:	The destination specifiers are coded as type modify
;9394	;		    to allow prechecking of accessibility.
;9395	;		2.  When the first destination is memory and the second destination is
;9396	;		    register, there must be a SYNCHRONIZE MBOX after the memory write.	If
;9397	;		    this is not done, the instruction may complete before the M-Box has a
;9398	;		    chance to report a memory management fault on the first destination.
;9399	;
				;9400	.bin
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  287
;    MULDIV.MIC 	     EDIV										      /REV=
;															     MULDIV
				;9401
				;9402	;	EDIV operation:
				;9403	;
				;9404	;		quo.wl <-- divd.rq / divr.rl
				;9405	;		rem.wl <-- rem(divd.rq, divr.rl)
				;9406	;
				;9407	;
				;9408	;	The following simultaneous reference restriction exists for
				;9409	;	this entry point: [spec 3; spec 4].
				;9410
				;9411	EDIV..:
				;9412		;********** Hardware dispatch **********;
				;9413		[W0] <-- [S1], LONG,			; save divisor, test
				;9414		Q <-- PASSB [S2],			; get low dividend
E 16E  0002,8048,0480,0485 J 485;9415			sim cond k s4.[0]
				;9416
				;9417		;---------------------------------------;
				;9418		[W3] <-- [S1], LONG,			; save high dividend, test sign
E 485  0000,0000,1080,013E J 13E;9419			sim cond k s4.[0]
				;9420
				;9421		;---------------------------------------;
				;9422		VA <-- -[Q],				; negate low dividend if needed
				;9423		[W2] <-- PASSB [Q], LONG,		; save low dividend, test
E 13E  2D00,8053,0C00,41A1 B 1A1;9424		CASE [ALU.NZV] AT [EDIV.DIVR.POS]	; case on divisor test
				;9425
				;9426	;= ALIGNLIST 00xx	(EDIV.DIVR.POS, 	EDIV.DIVR.ZERO,
				;9427	;=			 EDIV.DIVR.NEG, 			)
				;9428	;  ALU.NZVC set by MOV --> V = C = 0
				;9429	;
				;9430	EDIV.DIVR.ZERO:
				;9431		;---------------------------------------; alu.nz = 01:
				;9432		[W0] <-- [W2], LONG,			; quotient result is low dividend
E 1A5  0000,0000,043D,0488 J 488;9433		SET PSL CC.IIII 			; set psl cc's, psl map is iiii
				;9434
				;9435		;---------------------------------------;
				;9436		STATE.2 <-- 1,				; flag divide by zero
			    p294;9437		[W3] <-- 000000[00], LONG,		; remainder result is 0
E 488  0080,2000,1009,85BE J 5BE;9438		GOTO [EDIV.WRITE.RESULT]		; write result
				;9439
				;9440	EDIV.DIVR.NEG:
				;9441		;---------------------------------------; alu.nz = 10:
				;9442		[W0] <-- -[W0], LONG,			; negate divisor
			    p289;9443		STATE.1 <-- 1,				; flag divisor sign
E 1A9  2D00,0008,0409,41F6 B 1F6;9444		CASE [ALU.NZV] AT [EDIV.DIVD.POS]	; case on high dividend test
				;9445
				;9446	EDIV.DIVR.POS:
				;9447		;---------------------------------------; alu.nz = 00:
			    p289;9448		NOP,					; nothing to do...
E 1A1  2000,0000,2000,41F6 B 1F6;9449		CASE [ALU.NZV] AT [EDIV.DIVD.POS]	; case on high dividend test
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  288
;    MULDIV.MIC 	     EDIV										      /REV=
;															     MULDIV
				;9450
				;9451	;	Extended divide, continued.
				;9452	;	Divisor sign processed, check dividend sign.
				;9453
				;9454	;	At this point,
				;9455	;		W0	=	!divisor!
				;9456	;		W2 = Q	=	low dividend
				;9457	;		W3	=	high dividend
				;9458	;		VA	=	- low dividend
				;9459	;		STATE<1> =	sign of divisor
				;9460
				;9461	;= ALIGNLIST 01xx	(EDIV.DIVD.POS, 	EDIV.DIVD.NEG)
				;9462	;  ALU.NZVC set by move --> V = C = 0
				;9463
				;9464	EDIV.DIVD.NEG:
				;9465		;---------------------------------------; alu.n = 1:
				;9466		Q <-- PASSA [VA], LONG, 		; negate low order dividend
				;9467		STATE.0 <-- 1,				; flag dividend sign
E 1FE  E002,4000,20B8,CFEA B 1EA;9468		CASE [SHF.NZ.INT] AT [EDIV.DIVD.NEG.NZ] ; case on low order dividend
				;9469
				;9470	;= ALIGNLIST 101x	(EDIV.DIVD.NEG.NZ,	EDIV.DIVD.NEG.Z)
				;9471
				;9472	EDIV.DIVD.NEG.NZ:
				;9473		;---------------------------------------; alu.z = 0:
			    p289;9474		[W3] <-- NOT [W3], LONG,		; complete negation of dividend
E 1EA  0D80,0020,1000,01F6 J 1F6;9475		GOTO [EDIV.DIVD.POS]			; join common flows
				;9476
				;9477	EDIV.DIVD.NEG.Z:
				;9478		;---------------------------------------; alu.z = 1:
			    p289;9479		[W3] <-- -[W3], LONG,			; complete negation of dividend
E 1EE  0D00,0020,1000,01F6 J 1F6;9480		GOTO [EDIV.DIVD.POS]			; join common flows
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  289
;    MULDIV.MIC 	     EDIV										      /REV=
;															     MULDIV
				;9481
				;9482	;	Extended divide, continued.
				;9483	;	Perform overflow check, start divide.
				;9484
				;9485	;	At this point,
				;9486	;		W0	=	!divisor!
				;9487	;		W2	=	low dividend
				;9488	;		W3'Q	=	!dividend!
				;9489	;		STATE<1:0> =	signs of divisor, dividend
				;9490
				;9491	;	The following compare is intended to check whether divd < divr, that is,
				;9492	;	if divd - divr < 0 (--> alu.c = 0).  However, to start up the divide
				;9493	;	algorithm, alu.c must be 1.  Accordingly, divd - divr > 0 is calculated.
				;9494
				;9495	EDIV.DIVD.POS:
				;9496		;---------------------------------------; alu.nz = 00:
				;9497		[WBUS] <-- [W3] - [W0], LONG,		; compare of divd - divr
				;9498							; if ok, alu.c = 0
E 1F6  0A80,0008,2040,0489 J 489;9499			sim cond k s4.[0]
				;9500
				;9501		;---------------------------------------;
E 489  0A80,0020,2010,0514 J 514;9502		[WBUS] <-- [W0] - [W3], LONG		; make sure alu.c = 1 before first udiv step
				;9503
				;9504		;---------------------------------------;
			    p291;9505		[W3] <-- [W3] UDIV [W0], LONG,		; do divide step
E 514  4E82,0008,1040,425C B 55C;9506		CASE [ALU.NZC] AT [EDIV.NO.OVERFLOW]	; case on overflow test
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  290
;    MULDIV.MIC 	     EDIV										      /REV=
;															     MULDIV
				;9507
				;9508	;	Extended divide, continued.
				;9509	;	Divide overflow.
				;9510
				;9511	;	At this point,
				;9512	;		W2	=	low dividend
				;9513
				;9514	;= ALIGNLIST 110x	(EDIV.NO.OVERFLOW,	EDIV.OVERFLOW)
				;9515
				;9516	EDIV.OVERFLOW:
				;9517		;---------------------------------------; alu.c = 1:
				;9518		[W0] <-- [W2], LONG,			; quotient result is low dividend
E 55E  0000,0000,043D,048A J 48A;9519		SET PSL CC.IIII 			; set psl cc's, psl map is iiii
				;9520
				;9521		;---------------------------------------;
E 48A  0080,2008,200E,848C J 48C;9522		SET PSL(V)				; set psl.v
				;9523
				;9524		;---------------------------------------;
			    p294;9525		[W3] <-- 000000[00], LONG,		; remainder result is 0
E 48C  0080,2000,1000,05BE J 5BE;9526		GOTO [EDIV.WRITE.RESULT]		; write result
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  291
;    MULDIV.MIC 	     EDIV										      /REV=
;															     MULDIV
				;9527
				;9528	;	Extended divide, continued.
				;9529	;	Continue divide, first step (of 33) have been executed.
				;9530
				;9531	;	At this point,
				;9532	;		W0	=	!divisor!
				;9533	;		W2	=	low dividend
				;9534	;		W3'Q	=	!dividend!
				;9535	;		STATE<1:0> =	signs of divisor, dividend
				;9536
				;9537	EDIV.NO.OVERFLOW:
				;9538		;---------------------------------------; alu.c = 0:
			    p299;9539		[W3] <-- [W3] UDIV [W0], LONG,		; do divide step
E 55C  0E82,0008,1040,22A5 S 2A5;9540		CALL [DIVIDE.31.STEPS]			; do next 31 divide steps
				;9541
				;9542		;---------------------------------------;
E 55D  0001,8122,1320,0401 J 401;9543		[W3] <-- [K1]!![W3] RSH [1.], LONG	; undo last shift of remainder
				;9544							; >> Q not readable this cycle
				;9545
				;9546		;---------------------------------------;
				;9547		[W4] <-- -[Q], LONG,			; negate quotient to test for overflow
				;9548		Q <-- PASSB [Q],			; recycle quotient to test for overflow
			    p292;9549		CASE [ALU.NZC] AT [EDIV.REM.NEG],	; case on last step positive or negative
E 401  4D02,8050,1400,421D B 41D;9550			sim cond k s4.[0]
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  292
;    MULDIV.MIC 	     EDIV										      /REV=
;															     MULDIV
				;9551
				;9552	;	Extended divide, continued.
				;9553	;	Cleanup remainder, signs.
				;9554
				;9555	;	At this point,
				;9556	;		W0	=	!divisor!
				;9557	;		W2	=	low dividend
				;9558	;		W3	=	remainder with sign bit forced on
				;9559	;		W4	=	negated quotient
				;9560	;		Q	=	quotient
				;9561	;		STATE<1:0> =	sign of divisor, dividend
				;9562
				;9563	;= ALIGNLIST 110x	(EDIV.REM.NEG,		EDIV.REM.POS)
				;9564
				;9565	EDIV.REM.POS:
				;9566		;---------------------------------------; alu.c = 1:
				;9567		[W3] <-- [W3] ANDNOT [80]000000, LONG,	; fix up remainder from last divide step
E 41F  4480,3C00,1040,4A28 B 428;9568		CASE [STATE.2-0] AT [EDIV.STATE.00]	; case on signs of divisor, dividend
				;9569
				;9570	EDIV.REM.NEG:
				;9571		;---------------------------------------; alu.c = 0:
				;9572		[W3] <-- [W0] + [W3], LONG,		; fix up remainder from last divide step
E 41D  4880,0020,1010,4A28 B 428;9573		CASE [STATE.2-0] AT [EDIV.STATE.00]	; case on signs of divisor, dividend
				;9574
				;9575	;= ALIGNLIST *00x	(EDIV.STATE.00, 	EDIV.STATE.01,
				;9576	;=			 EDIV.STATE.10, 	EDIV.STATE.11)
				;9577	;  STATE<2> = 0 --> STATE<2:0> = 0??
				;9578
				;9579	EDIV.STATE.00:
				;9580		;---------------------------------------; divisor +, dividend +:
			    p293;9581		NOP,					; nothing to do...
E 428  E000,0000,2000,4F27 B 427;9582		CASE [SHF.NZ.INT] AT [EDIV.POS.NO.OVERFLOW] ; case on quotient geq 0
				;9583
				;9584	EDIV.STATE.01:
				;9585		;---------------------------------------; divisor +, dividend -:
			    p293;9586		[W3] <-- -[W3], LONG,			; negate remainder
E 42A  2D00,0020,1000,4113 B 413;9587		CASE [ALU.NZV] AT [EDIV.NEG.OVERFLOW]	; case on quotient leq 0
				;9588
				;9589	EDIV.STATE.10:
				;9590		;---------------------------------------; divisor -, dividend +:
			    p293;9591		NOP,					; nothing to do...
E 42C  2000,0000,2000,4113 B 413;9592		CASE [ALU.NZV] AT [EDIV.NEG.OVERFLOW]	; case on quotient leq 0
				;9593
				;9594	EDIV.STATE.11:
				;9595		;---------------------------------------; divisor -, dividend -:
			    p293;9596		[W3] <-- -[W3], LONG,			; negate remainder
E 42E  ED00,0020,1000,4F27 B 427;9597		CASE [SHF.NZ.INT] AT [EDIV.POS.NO.OVERFLOW] ; case on quotient geq 0
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  293
;    MULDIV.MIC 	     EDIV										      /REV=
;															     MULDIV
				;9598
				;9599	;	Extended divide, continued.
				;9600	;	Overflow checks.
				;9601	;		If positive result expected, require result geq 0.
				;9602	;		If negative result expected, require result leq 0.
				;9603
				;9604	;	At this point,
				;9605	;		W3	=	remainder, sign adjusted
				;9606	;		W4	=	negated quotient
				;9607	;		Q	=	quotient
				;9608
				;9609	;= ALIGNLIST 011x	(EDIV.POS.NO.OVERFLOW,	EDIV.POS.OVERFLOW)
				;9610
				;9611	EDIV.POS.NO.OVERFLOW:
				;9612		;---------------------------------------; shf.n = 0:
				;9613		[W0] <-- [Q], LONG,			; save quotient in W0
			    p294;9614		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 427  0000,0000,04AD,05BE J 5BE;9615		GOTO [EDIV.WRITE.RESULT]		; write result
				;9616
				;9617	EDIV.POS.OVERFLOW:
				;9618		;---------------------------------------; shf.n = 1:
				;9619		[W0] <-- [W2], LONG,			; save quotient (low dividend) W0
			    p290;9620		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 42F  0000,0000,043D,055E J 55E;9621		GOTO [EDIV.OVERFLOW]			; join overflow code
				;9622
				;9623	;= ALIGNLIST 001x	(EDIV.NEG.OVERFLOW,	EDIV.NEG.ZERO,
				;9624	;=			 EDIV.NEG.NO.OVERFLOW,			)
				;9625
				;9626	EDIV.NEG.OVERFLOW:
				;9627		;---------------------------------------; alu.nz = 00:
				;9628		[W0] <-- [W2], LONG,			; save quotient (low dividend) in W0
			    p290;9629		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 413  0000,0000,043D,055E J 55E;9630		GOTO [EDIV.OVERFLOW]			; join overflow code
				;9631
				;9632	EDIV.NEG.ZERO:
				;9633		;---------------------------------------; alu.nz = 01:
				;9634		[W0] <-- [W4], LONG,			; save quotient in W0
			    p294;9635		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 417  0000,0000,045D,05BE J 5BE;9636		GOTO [EDIV.WRITE.RESULT]		; write result
				;9637
				;9638	EDIV.NEG.NO.OVERFLOW:
				;9639		;---------------------------------------; alu.nz = 10:
				;9640		[W0] <-- [W4], LONG,			; save quotient in W0
			    p294;9641		SET PSL CC.IIII,			; set psl cc's, psl map is iiii
E 41B  0000,0000,045D,05BE J 5BE;9642		GOTO [EDIV.WRITE.RESULT]		; write result
;    NVAXBM.ACR 	     MICRO2  1Q(01)    30-JUN-92  16:10:09	ALLOC 30-Jun-92 16:10:55  /LINK=		   Page  294
;    MULDIV.MIC 	     EDIV										      /REV=
;															     MULDIV
				;9643
				;9644	;	Extended divide, continued.
				;9645
				;9646	;	At this point,
				;9647	;		W3	=	remainder, sign adjusted
				;9648	;		W0	=	quotient
				;9649	;		STATE<2> =	divide by zero flag
				;9650
				;9651	;= ALIGNLIST 100x	(EDIV.MEM.DEST, 	EDIV.RMODE.DEST,
				;9652	;=